implementation and testing of adders using bist

IMPLEMENTATION AND TESTING OF ADDERS USING

BIST

A Mini-Project Report

Submitted in partial fulfillment of the requirements for the award of the degree

Of

BACHELOR OF TECHNOLOGY

IN

ELECTRONICS AND COMMUNICATION ENGINEERING

By

Veeramachaneni Deepthi (09BN1A04A0)

Under the guidance Of

Mr P.Nataraju M.Tech,

Asst. Professor ECE,TECA.

Department Of Electronics and Communication Engineering

TENALI ENGINEERING COLLEGE(Affiliated to JNTU KAKINADA, Approved by AICTE)

ANUMARLAPUDI (POST), Via SANGAMJAGARLAMUDI TENALI (R.M.S), GUNTUR (Dt.) - 522213.

2012-13

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

BONAFIDE CERTIFICATE

This is to certify that this Project entitled “Implementation and Testing of

Adders using BIST” is the bonafide work of Veeramachaneni Deepthi

(09BN1A04A0), who carried out the project under our supervision .

(Mr P.Nataraju M.Tech) (Mr. A. Nagaraju M.Sc., M.Tech.)Internal Guide Head of the Department

Submitted for Viva voice Examination held on__________________

Internal Examiner External Examiner

TENALI ENGINEERING COLLEGE

[Sponsored by JAMPALA GOPALA RAO EDUCATION SOCIETY] (Affiliated to JNTU KAKINADA, Approved by AICTE)

ANUMARLAPUDI(POST), Via SANGAMJAGARLAMUDI

TENALI (R.M.S), GUNTUR (Dt.) - 522213.

DECLARATION

I VEERAMACHANENI DEEPTHI (09BN1A04A0), hereby

declare that the Mini - Project Report entitled “IMPLEMENTATION AND

TESTING OF ADDERS USING BIST”is the bonafide work done by me

under the guidance of Mr. P.Nataraju M.Tech, Asst. Professor in ECE

Department at Tenali Engineering College, Anumarlapudi, is submitted in

partial fulfillment of the requirements for the award of the degree of B.Tech

in Electronics and Communication Engineering.

NAME OF CANDIDATE SIGNATURE OF CANDIDATE

Veeramachaneni Deepthi

(09BN1A04A0)

DATE:

PLACE: TECA

ACKNOWLEDGEMENT

My deep sense of gratitude goes to our beloved Director, Prof. J. Jawahara Rao garu

who provided all facilities and necessary encouragement during the course of study.

I extend my gratitude and sincere thanks to our Principal, Dr. G. Srinivasa Rao garu for

his support.

I take the privilege to thank our Head of the Department, Mr. A. Nagaraju garu for his

support and encouragement.

I dedicate my whole hearted thanks to our guide, Mr P.Nataraju for his commendable

inspiring guidance, valuable advice, encouragement and motivation given to succeed in

our endeavors.

I extend my sincere thanks to all of our Teachers.

Last but not the least; I sincerely thank my parents, friends and all well wishers for

their loving prayers for successful completion of this project.

CHAPTER 3

FAULT DETECTION 11

3.1 FAULT DETECTION 11

CHAPTER 4ADDERS 14

4.1 BASIC ADDER UNIT 14

4.1.1 HALF ADDER 14

4.1.2 FULL ADDER 15

4.2 RIPPLE CARRY ADDER 16

4.3 CARRY LOOK-AHEAD ADDER 17

4.4 CARRY SAVE ADDER 20

CHAPTER 5INTRODUCTION TO VHDL 21

5.1 DEFINITION 21

5.2 FEATURES OF VHDL 21

5.3 DESIGN FLOW IN VHDL 21

5.4 MODELING TECHNIQUES 22

5.4.1 BEHAVIORAL MODELING 23

5.4.2 DATAFLOW MODELING 24

5.4.3 STRUCTURAL MODELING 24

5.5 OPERATORS 27

5.6 APPLICATIONS 28

CHAPTER 6RESULTS 29

6.1 OUTPUT WAVE FORMS 29

6.1.1 FULL ADDER 29

6.1.2 RIPPLE CARRY ADDER 29

6.1.3 CARRY LOOK AHEAD ADDER 30

6.1.4 CARRY SAVE ADDER 30

6.1.5 BILBO SERIAL SCAN MODE 31

6.1.6 BILBO LFSR MODE 31

6.1.7 BILBO D-FF MODE 32

6.1.8 BILBO MISR MODE 32

6.2 TECHNOLOGY SCHEMATIC 33

6.2.1 FULL ADDER 33



6.2.4 CARRY SAVE ADDER 36

6.2.5 BILBO 37

6.3 SIMULATION RESULTS OF STUCK AT FAULTS 38



CHAPTER 7 40CONCLUSION

7.1 CONCLUSION 407.2 FUTURE ENHANCEMENT 40

REFERENCES

LIST OF FIGURES

FIGURE 2.2 BASIC BIST ARCHITECTURE 4

FIGURE 2.3 DESIGN FOR TESTABILITY 4

FIGURE 2.4 BIST STRUCTURE 5

FIGURE 2.4.1 LFSR SEQUENCE GENERATOR 6

FIGURE 2.5 GENERAL BILBO STRUCTURE 8

FIGURE 2.5.1 SERIAL SCAN MODE 9

FIGURE 2.5.2 LFSR PATTERN GENERATOR 9

FIGURE 2.5.3 D FLIP FLOP MODE 10

FIGURE 2.5.4 MISR MODE 10

FIGURE 3.1 CIRCUIT UNDER TEST (CUT) 11

FIGURE 3.2 FAULTY CIRCUIT 12

FIGURE 4.1.1 HALF ADDER 14

FIGURE 4.1.2 FULL ADDER 15

FIGURE 4.1.3 REALIZATION OF FULL ADDER USING 2 HALF ADDERS 16

FIGURE 4.2 RIPPLE CARRY ADDER 16

FIGURE 4.2.1 CARRY PROPAGATION FOR RIPPLE CARRY ADDER 17

FIGURE 4.3 CARRY LOOK AHEAD ADDER 19

FIGURE 4.3.1 GENERATION OF SUM AND CARRY IN CARRY LOOK

AHEAD ADDER 19

FIGURE 4.4 CARRY SAVE ADDER 20

FIGURE 5.3 DESIGN FLOW CHART 22

FIGURE 5.3.1 VHDL PROGRAM STRUCTURE 22

FIGURE 5.4 MODELING TECHNIQUES 22

FIGURE 5.5 PROPERTIES USED IN THE PROJECT 27

FIGURE 6.1.1 WAVE FORM OF FULL ADDER 29

FIGURE 6.1.2 WAVE FORM OF RIPPLE CARRY ADDER 29

FIGURE 6.1.3 WAVE FORM OF CARRY LOOK AHEAD ADDER 30

FIGURE 6.1.4 WAVE FORM OF CARRY SAVE ADDER 30

FIGURE 6.1.5 WAVE FORM OF SERIAL SCAN MODE 31

FIGURE 6.1.6 WAVE FORM OF LFSR MODE 31

FIGURE 6.1.7 WAVE FORM OF D FF MODE 32

FIGURE 6.1.8 WAVE FORM OF MISR MODE 32

FIGURE 6.2.1 TECHNOLOGY SCHEMATIC OF FULL ADDER 33

FIGURE 6.2.2 TECHNOLOGY SCHEMATIC OF RIPPLE CARRY ADDER 34

FIGURE 6.2.3 TECHNOLOGY SCHEMATIC OF CARRY LOOK AHEAD

ADDER 35

FIGURE 6.2.4 TECHNOLOGY SCHEMATIC OF CARRY SAVE ADDER 36

FIGURE 6.2.5 TECHNOLOGY SCHEMATIC OF BILBO 37

FIGURE 6.3.1 SIMULATION RESULTS OF STUCK AT FAULT FOR

RIPPLE CARRY ADDER 38

FIGURE 6.3.2 SIMULATION RESULTS OF STUCK AT FAULT FOR

CARRY LOOK AHEAD ADDER 39

LIST OF TABLES

PAGE NO

TABLE 2.4.1 SEQUENCES GENERATED USING LFSR 6

TABLE 2.5 BILBO MODES 8

TABLE 3.1 RESPONSE OF FAULT FREE CIRCUIT 12

TABLE 3.2 RESPONSE OF FAULTY CIRCUIT 13

TABLE 4.1.2 TRUTH TABLE OF FULL ADDER 15

TABLE 5.5 OPERATORS 27

ABBREVATIONS

S.NO Short Form Full Form

1. ATE Automatic Test Equipment

2. ASIC Application Specific Integrated Circuit

3. BIST Built In Self Test

4. BILBO Built In Logic Block Observer

5. CUT Circuit Under Test

6. CLB Configurable Logic Blocks

7. DUT

Device Under Test

8. DFT Design For Testability

9. HDL Hardware Description Language

10. IC Integrated Circuits

11 LFSR Linear Feed Back Shift Register

12. MISR Multiple Input Signature Analysis

13. ORA Output Response Analyzer

14. PRPG Pseudo Random Pattern Generator

15. RAM Random Access Memory

16. TPG Test Pattern Generator

17. VHSIC Very High Speed Integrated Circuit

CHAPTER 1

INTRODUCTION

In this chapter a brief introduction to VLSI is presented. Along with this objective of the project and the software used is also illustrated here.1.1 INTRODUCTION TO VLSI VLSI field involves packing more and more logic devices into smaller and smaller areas. It has not only reduced the size and the cost but also increased the complexity of the circuits. The positive improvements have resulted in significant performance/cost advantages in VLSI systems.

Testing of integrated circuits (ICs) is of crucial importance to ensure a high level of quality. The impact of testing affects areas of manufacturing as well as those involved in design. Given this range of design involvement, how to go about best achieving a high level of confidence in IC operation is a major concern. This desire to attain a high quality level must be tempered with the cost and time involved in this process. These two design considerations are at constant odds. It is with both goals in mind (effectiveness vs. cost/time) that Built-In-Self Test (BIST) has become a major design consideration in Design-For-Testability (DFT) methods.

This work presents methodology to detect faults using Built in Self Test (BIST) and other various Designs for Testability (DFT) methods. It also introduces Automatic Test Pattern Generation for maximum fault coverage. The task of determining whether the chip is working properly or not is very tedious. However, if chip is not properly fabricated, they can cause system failure and result in heavy loss in economy. System failure results difficulty in debugging.

The debugging cost grows exponentially as we move from chip to board level and then towards the system level. As the number of transistor integrated in the chip increases, task to test the functionality of chip become more and more difficult. To overcome these design issues, Design for Testability has become more important.1.2 OBJECTIVE

The main objective is designing and implementation of various adders with self testing (using built in self test), which can be used in any processor application, as adders are the basic building blocks in many digital system. In addition to the designing part, we test the designed adders to detect whether the adder is fault free or not.

1.3 SOFTWARE

The software used is VHDL. VHDL is an acronym for VHSIC Hardware Description Language. The word 'hardware' The language VHDL covers the complete range of applications and can be used to model (digital) hardware in a general way. Hardware Description Language (HDL) = "Programming"-language for modeling of (digital) hardware.

VHDL features have three important modeling techniques: Behavioral Modeling

Dataflow Modeling

Structural Modeling

1.3.1 Xilinx ISE

The Integrated Software Environment (ISE) is the Xilinx design software suite that allows you to take your design from design entry through Xilinx device programming. The ISE Project Navigator manages and processes your design through the following steps in the ISE design flow

Design Entry

Synthesis

Implementation

Verification

Device Configuration

CHAPTER 2

BUILT IN SELF TESTING (BIST)

Digital system is tested during its lifetime on numerous occasions. It is very important to have quick and very high fault coverage testing. This chapter explains the need for self testing. BIST can be implemented in many different ways, one such advanced method is BILBO (Built in Logic Block Observer).2.1 OVERVIEW

One common and widely used in semiconductor industry for IC chip testing is to ensure that this is to specify test as one of the system functions and thus becomes self-test. BIST is one of the most popular test solutions to test the embedded cores. Main advantage of this methodology is that the test patterns are not applied by external Automatic Test Equipments (ATEs) but generated by inbuilt testing circuit. This aspect impacts the cost/time constraint. Also it saves the memory requirement.

In addition, BIST can provide at speed, in system testing of the Circuit-Under-Test (CUT). This is crucial to the quality component of testing. In addition, BIST can overcome pin limitations due to packaging, make efficient use of available extra chip area and provide more detailed information about the faults present. All these benefits are plentiful motivations for BIST. The basic idea of BIST, in its most simple form, is to design a circuit so that the circuit can test itself and determine whether it is “good” or “bad” (fault-free or faulty, respectively). This typically requires additional circuitry whose functionality must be capable of generating test patterns as well as providing a mechanism to determine if the output responses of the circuit under test (CUT) to the test patterns correspond to that of a fault-free circuit.

Test pattern generation is the major step in BIST that mainly affects the power consumption. In order to reduce the switching activity during test mode, several test pattern generators are proposed .On a very basic level, BIST needs a stimulus Test Pattern Generator (TPG), a circuit to be tested, a way to analyze the results, and a way to compress those results for simplicity and handling.

2.2 BASIC BIST ARCHITECTURE A representative architecture of the BIST circuitry as it might be incorporated into

the CUT is illustrated in the block diagram of Figure below.

Fig 2.2 Basic BIST ArchitectureThe two essential functions include the test pattern generator (TPG) and output

response analyzer (ORA). While the TPG produces a sequence of patterns for testing the CUT, the ORA compacts the output responses of the CUT into some type of Pass/Fail indication. This BIST architecture includes two essential functions. The two essential

functions include the test pattern generator (TPG) and output response analyzer (ORA). While the TPG produces a sequence of patterns for testing the CUT, the ORA compacts the output responses of the CUT into some type of Pass/Fail indication.2.3 DESIGNS FOR TESTABILITY

Fig 2.3 Design for TestabilityThe mechanics of testing, as illustrated in below Figure, are similar at all levels of

testing, including design verification. A set of input stimuli is applied to a circuit and the

output response of that circuit is compared to the known good output response, or

expected response, to determine if the circuit is "good" or "faulty". There are various

testing techniques of a circuit. Basic testing flow is shown above.

2.4 BIST STRUCTURE

Generate test vectors, apply them to the circuit under test (CUT) or device under

test (DUT), and then verify the response.

Fig 2.4 BIST Structure

Fig shows a simple BIST block diagram which uses a linear feedback shift

register (LFSR) to generate the test vectors and multiple input signature register (MISR)

to verify the output against the correct response of the circuit under test.

A general BIST includes the following:

1. Pseudo random pattern generator (PRPG)

2. BIST Response Compaction

3. Output response analyzer (ORA)

2.4.1 Pseudo Random Pattern Generator

To perform test on any circuit, a Pseudo random pattern generator use mostly

linear feedback shift register (LFSR) to generate input test vectors. When the outputs of

the flip-flops are loaded with a seed value i.e anything except all 0s, which would cause

the LFSR to produce all 0 patterns and when the LFSR is clocked, it will generate a

pseudo random pattern of 1s and 0s.

Standard LFSR

The main part of BIST is LFSR which can generate random numbers which are

used to identify the physical faults in the IC. Every LFSR has a characteristic polynomial

that describes its behaviour.

Fig

2.4.1 LFSR

Sequence

Generator

Q0*=Q1 XOR Q2

Q1*=Q0

Q2*=Q1

Q0* Q1* Q2* Q0Q1Q2

1 1 1 111 (7)

0 1 1 011 (3)

0 0 1 001 (1)

1 0 0 100 (4)

0 1 0 010 (2)

1 0 1 101 (5)

1 1 0 110 (6)Table 2.4.1 Sequences generated using LFSR

A Linear Feedback Shift Register is a sequential shift register with combinational logic. It generates pseudo-random cycles through a sequence of binary values. A linear feedback shift register can be formed by performing exclusive-OR on the outputs of two or more of the flip-flops together and feeding those outputs back into the input of one of the flip flops.The standard LFSR method has been used as the test pattern generator for the BIST. It consists of D flip-flops and linear exclusive-OR gates which is shown in figure.2.4.2 BIST Response Compaction

During BIST, for every test pattern that being generated, the CUT produces a set

of output values. In order to ensure the chip is fault free, every output values from the

CUT for each test pattern will need to compare with the correct output values obtained

from the simulations. This is a tedious and time consuming process. Thus, it is necessary

to reduce the enormous of circuit responses to a manageable size that can be either store

in the chip or can easily compared with the golden response values.

2.4.3 Output Response Analyser

The on-chip storage of the entire test input vectors with their corresponding

outputs are stored in RAM. After applying the input, Outputs are checked and compared

with the stored ones. If stored data is same as the output of the circuit then circuit is fault

free otherwise it is fault. In BIST, both the Test Pattern Generation (TPG) and Output

Response Analyzer (ORA) are incorporated inside the chip. Assuming that all levels of

hierarchy uses BIST, each element test itself and transmits the result to the higher level of

hierarchy.

2.4.4 CUT (Circuit Under Test)

The system that is to be tested is termed as DUT. It is the circuit of the IC that is

going to be checked for any defects after its manufacturing. Any digital design

represented in one of the Hardware Description Languages (HDL’s) is used as a DUT.

2.4.5 Signature Analysis

Signature Analysis is a compression technique based on the concept of cyclic

redundancy checking .The good and faulty circuits produce different signatures. Test

Patterns for BIST can be generated at-speed by an LFSR with only a clock input.

The outputs of the circuit-under-test must be compared to the known good response. In general, collecting each output response and off-loading it from the circuit under test for comparison is too inefficient to be practical. The general solution is to compress the entire output stream into a single signature value.2.4.6 MISR (Multiple Input Signature Register)

Multiple-input signature register (MISR) is the solution that compacts all outputs

into one LFSR. It works because LFSR is linear and obeys superposition principle. All

responses are superimposed in one LFSR. The final remainder is XOR sum of remainders

of polynomial divisions of each Primary Output by the characteristic polynomial. Its

output develops a signature based on the effect of all the bits fed into it. If any bit is

wrong, the signature will be different from the expected value and a fault will have been

detected. A Multiple Input Signature-analysis Register (MISR) can be used to reduce the

amount of hardware required to compress a multiple bit stream. The MISR provides an

alternative to using multiple Linear Feedback Shift Registers (LFSRs) in parallel and

separately comparing the error polynomials.

2.5 BUILT IN LOGIC BLOCK OBSERVER (BILBO)

A BILBO (built-in logic block observer) combines normal flip flops with a few

additional gates. Built-in logic block observer (BILBO) has become one of the most

widely accepted techniques for self-testing of complex digital IC’s. This technique is

based on grouping the storage elements of the circuit in the two registers which give this

technique its name. A BILBO register provide four different modes. With each of its

stages acting as independent registers; as a generator of pseudo random sequences; as

analyser of multiple-input signatures; and reset of all stages.

Fig 2.5 General BILBO Structure

B1 B2 MODE

0 0 Serial Scan mode

0 1 LFSR mode

1 0 D Flip Flop mode

1 1 MISR Mode

Table 2.5 BILBO Modes

2.5.1 BILBO In Serial Scan Mode

B1=B2=0.BILBO acts as serial shift register. Data are serially clocked into the

register through SI while the register contents can be simultaneously read parallel at the

output, or clocked out through the serial output SO.

Fig 2.5.1 Serial Scan Mode

2.5.2 BILBO In LFSR Pattern Generator Mode

Here B1=0, B2=1 in this mode BILBO is used to Generate Test Sequences. These

test sequences (input test vectors) are then applied to the Circuit under Test.

Fig 2.5.2 LFSR Pattern Generator

2.5.3 BILBO IN D FLIP-FLOP MODE

B1=1, B2=0i n this mode we can externally apply the inputs say D1, D2….Dn.

These inputs are then given to the D Flip flop and then forwarded as Q1, Q2….Qn.

Fig 2.5.3 D Flip Flop Mode

2.5.4 BILBO IN MISR MODE

Here B1=B2=1, The BILBO is converted into Multiple Input Signature Register.

In this mode, it may be used for performing parallel signature analysis or for generating

pseudo random sequences.

Fig 2.5.4 MISR Mode

CHAPTER 3FAULT DETECTION

There are various kinds of faults which can affect the output of any circuit, one

such fault is stuck at fault and this fault is illustrated in this chapter.

3.1 FAULT DETECTION

Consider the circuit shown in figure. The circuit can be expressed using Boolean

equation as,

Out [0] = In [0] + In [1] + In [2]Out [1] = In [0] . In [1]. In [2]Out [2] = (In [0] . In [1]) + In [2]

We have three input bits and three output bits for the given circuit to be tested. So we design an LFSR with three output bits to generate the test vectors. Let the LFSR be of maximal length so that we get the test vector sequence or pseudo random binary sequence as {111, 011, 001, 100, 010, 101, and 110} as explained earlier.

This pseudo random binary sequence is applied to the circuit under test and the output is recorded. The output at the end of 7th clock is taken as the signature.

Fig 3.1 Circuit Under Test (CUT)

Clock Pulse LFSR Output Output of CUT MISR outputs Signature

1 111 111 000

110

2 011 101 110

3 001 001 000

4 100 101 001

5 010 001 111

6 101 101 100

7 110 101 110

Table 3.1 Response of fault free circuit

From the table we can see that the signature value is 110 for fault free circuit.Now considers the circuit in the presence of a fault. Let the circuit has a stuck at zero (s-@-0) fault at the input of the OR gate for the computing out bit. For the 4th clock tick the faulty circuit gives incorrect output. But for the 5th clock tick the output is same in the presence and absence of fault, but the multiple input signature register output remain different ever after the first occurrence of the fault. Also when the complete pseudo random binary sequence is applied to the circuit under test, i.e. at the end of 7 clock ticks, we take the output of signature register as the signature of the circuit under test.

Fig 3.2 Faulty circuit

Clock Pulse LFSR output Output of CUT MISR outputs Signature

1 111 111 000

100

2 011 101 110

3 001 001 000

4 100 001 001

5 010 001 011

6 101 001 111

7 110 001 100

Table 3.2 Response of faulty circuit

We can see that the signature values computed for correct and faulty circuit are different. Hence we can conclude that verifying the signature of a circuit, on applying the complete pseudo random binary sequence, to the signature value computed earlier or generated by a fault free circuit is sufficient to determine whether the circuit is faulty or operating correctly. The MISR propagates the fault from the clock cycle where it appeared first till the end of the input sequence with the help of the feedback.

The test pattern can be repeated after resetting the multiple input signature register. When the test pattern is repeated, the responses remain the same as long as the fault is present. When fault is detected in an IC right after manufacturing, we can easily remove it. But if the fault is to be detected after integrating the IC to a PCB, the cost of finding the fault as well as correcting it is higher. This cost keeps increasing as the fault detection stage is later in the production procedure.

CHAPTER 4ADDERS

Addition is a fundamental operation for any digital system, digital signal processing or control system. A fast and accurate operation of a digital system is greatly influenced by the performance of the resident adders. In this chapter various adders are explained. Adders are also very important component in digital systems because of their extensive use in other basic digital operations such as subtraction, multiplication and division. Hence, improving performance of the digital adder would greatly advance the execution of binary operations inside a circuit compromised of such blocks. The performance of a digital circuit block is gauged by analyzing its power dissipation, layout area and its operating speed. 4.1 BASIC ADDER UNIT

The most basic arithmetic operation is the addition of two binary digits, i.e. bits. A combinational circuit that adds two bits, according the scheme outlined below, is called a half adder. A full adder is one that adds three bits, the third produced from a previous addition operation. One way of implementing a full adder is to utilizes two half adders in its implementation. The full adder is the basic unit of addition employed in all the adders that are implemented in this project. 4.1.1 Half Adder A half adder is used to add two binary digits together, A and B. It produces S, the sum of A and B, and the corresponding carry out Co. Although by itself, a half adder is not extremely useful, it can be used as a building block for larger adding circuits (FA). One possible implementation is using two AND gates, two inverters, and an OR gate instead of a XOR gate as shown in Fig. 4.1.

Fig 4.1.1 Half Adder

Boolean expressions for sum and carry are

Sum = A ⨁ B= A′B + AB′

Carry = AB

4.1.2 Full Adder

A full adder is a combinational circuit that performs the arithmetic sum of three

bits: A, B and a carry in, C. Also, as in the case of the half adder, the full adder produces

the corresponding sum, S, and a carry out Co. A full adder may be designed by two half

adders in series as shown in below Figure .The sum of A and B are fed to a second half

adder, which then adds it to the carry in C (from a previous addition operation) to

generate the final sum S. The carry out is the result of an OR operation taken from the

carry outs of both half adders.

Boolean expressions for sum and carry are

Sum = C (A B)

Carry = AB + C (A B)

Table 4.1.2 Truth Table of Full Adder

Fig 4.1.2 Full Adder

Fig 4.1.3 Realization of Full Adder Using Two Half Adders

A B C Sum Carry0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

4.2 RIPPLE CARRY ADDERThe ripple carry adder is constructed by cascading full adders (FA) blocks in

series. One full adder is responsible for the addition of two binary digits at any stage of

the ripple carry. The carryout of one stage is fed directly to the carry-in of the next stage.

For an n-bit parallel adder, it requires n computational elements (FA). Figure

shows an example of a parallel adder: a 4-bit ripple-carry adder. It is composed of four

full adders. The augend’s bits of x are added to the addend bits of y respectfully of their

binary position. Each bit addition creates a sum and a carry out. The carry out is then

transmitted to the carry in of the next higher-order bit. The final result creates a sum of

four bits plus a carry out (c4).

Fig 4.2 Ripple Carry Adder

Even though this is a simple adder and can be used to add unrestricted bit length

numbers, it is however not very efficient when large bit numbers are used. One of the most serious drawbacks of this adder is that the delay increases linearly with the bit length. Each full adder has to wait for the carry out of the previous stage to output steady-state result. Therefore even if the adder has a value at its output terminal, it has to wait for the propagation of the carry before the output reaches a correct value.

Taking the example shown below, the addition of x3 and y3 cannot reach steady state until c3 becomes available. In turn, c4 has to wait for c3, and so on down to c1. If one full adder takes Tfa seconds to complete its operation, the final result will reach its steady-state value only after 4Tfa seconds. Its area is nA fa. A small improvement in area consumption can be achieved if it is known in advance that the first carry in (c0) will always be zero. (If so, the first full adder can be replacing by a half adder).

A B

Co Ci

S

A B

Co Ci

S

A B

Co Ci

S

A B

Co Ci

S

A(3) B(3) A(2) B(2) A(1) B(1) A(0) B(0)

Cout C(4) C(3) C(2) C(1) C(0) Cin

S(3) S(2) S(1) S(0)

Fig 4.2.1 Carry Propagation for Ripple Carry Adder

The delay of ripple carry adder is linearly proportional to n, the number of bits,

therefore the performance of the RCA is limited when n grows bigger. The advantages of

the RCA are lower power consumption as well as a compact layout giving smaller chip

area.

4.3 CARRY LOOK-AHEAD ADDER

In the ripple-carry adder, its limiting factor is the time it takes to propagate the

carry. The carry look-ahead adder solves this problem by calculating the carry signals in

advance, based on the input signals. The result is a reduced carry propagation time.

The Propagate P and generate G in a full-adder, is given as:

Carry propagate: Pi = Ai Bi

Carry generate: Gi = Ai.Bi

Here both propagate and generate signals depend only on the input bits and thus

will be valid after one gate delay. The new expressions for the output sum and the

carryout are given by:

Si = Pi Ci-1

Ci+1= Gi + PiCi

These equations show that a carry signal will be generated in two cases:

1) If both bits Ai and Bi are 1

2) If either Ai or Bi is 1 and the carry-in Ci is 1.

Let's apply these equations for a 4-bit adder:

C1 = G0 + P0C0

C2 = G1 + P1C1 = G1 + P1 (G0 + P0C0) = G1 + P1G0 + P1P0C0

y0 x0

C4 C3 C2 C1C0

S3 S2 S1 S0

FA FA FA

FA

y1 x1 y2 x2 y3 x3

C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0

C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

These expressions show that C2, C3 and C4 do not depend on its previous carry-

in. Therefore C4 does not need to wait for C3 to propagate. As soon as C0 is computed,

C4 can reach steady state. The same is also true for C2 and C3

The general expression is

Ci+1= Gi + PiGi-1 + PiPi-1Gi-2 + ……. PiPi-1….P2P1G0 + PiPi-1 ….P1P0C0.

For example:

A: 1 1 0 1

B: 0 1 1 0

P: 1 0 1 1

G: 0 1 0 0

C: 0 1 0 0 0

S 0 0 1 1

Co 1 0 0 0 0

Carry look-ahead adder’s structure can be divided into three parts: the

propagate/generate generator, the sum generator and the carry generator

Fig 4.3 Carry Look Ahead Adder

Fig 4.3.1 Generation of Sum and Carry in Carry Look Ahead Adder

4.4 CARRY SAVE ADDERCarry save technique can be used when adding together several numbers. A

carry-save adder is a type of digital adder, used in computer micro architecture to compute the sum of three or more n-bit numbers in binary. It differs from other digital adders in that it outputs two numbers of the same dimensions as the inputs, one which is a sequence of partial sum bits and another which is a sequence of carry bits. Carry save adder is used to compute sum of three or more n-bit binary numbers. Carry save adder is same as a full adder. Figure has 3 inputs a,b,c which are given to full adder as inputs and produces partial sum and carry as S and C as shown in the following example:

The final addition is then computed as:1. Shifting the carry sequence C left by one place.

2. Placing a 0 to the front (MSB) of the partial sum sequence S.

3. Finally, a ripple carry adder is used to add these two together and computing the

resulting sum.

For example

X: 1 0 0 1 1

Y: 1 1 0 0 1

Z: 0 1 0 1 1

S: 0 0 0 0 1

C: 1 1 0 1 1

Sum: 1 1 0 1 1 1

Fig 4.4 Carry Save Adder

CHAPTER 5INTRODUCTION TO VHDL

5.1 DEFINITIONVHDL stands for “VHSIC Hardware Description Language.” VHSIC, in turn

stands for “Very High Speed Integrated Circuit”. The word 'hardware', however, is used in a wide variety of contexts which range from complete systems like personal computers on one side to the small logical gates on their internal integrated circuits on the other side.

This is why different descriptions exist for the hardware functionality. Complex systems are often described by the behavior that is observable from the outside. The description of a basic logic gate, on the other hand, may consist of only one Boolean equation. This is a very short and precise description. Hardware Description Language (HDL) = "Programming"-language for modeling of (digital) hardware.5.2 FEATURES OF VHDL

The VHDL Hardware Description Language has the following features Designs may be decomposed hierarchically.

Each Design element has both a well-defined interface (for connecting it to other

elements) and a precise behavioral specification (for simulating it).

Behavioral specifications can use either an algorithm or an actual hardware

structure to define an element’s operation.

Concurrency, timing, and clocking can all be modeled. VHDL handles

asynchronous as well as synchronous sequential-circuit structures.

5.3 DESIGN FLOW IN VHDLVHDL was designed with principles of structured programming in mind,

borrowing ideas from the Pascal and Ada software programming languages. A key idea is to define the interface of a hardware module while hiding its internal details. Thus, a VHDL entity is simply a declaration of module’s inputs and outputs, while a VHDL architecture is a detailed of the module’s internal structure or behavior.

Fig: 5.3 Design flow chart

Fig: 5.3.1 VHDL program structure

5.4 MODELING TECHNIQUES

Fig: 5.4 Modeling Techniques

VHDL features also three important modeling techniques:

Behavioral Modeling

Dataflow Modeling

Structural Modeling

5.4.1 Behavioral ModelingAt the most fundamental level, the behavior of a module is described by signal

assignment statements within processes. The basis for sequential modeling is the process construct.

1. Process: A process statement is the main construct in behavioral modeling that

allows you to use sequential statements to describe the behavior of a system over

time.

2. If Statements: The if statement executes a sequence of statements whose sequence

depends on one or more conditions.

3. Case statements: The case statement executes one of several sequences of

statements, based on the value of a single expression.

4. Loop statements: A loop statement is used to repeatedly execute a sequence of

sequential statements. There are two types of iteration schemes:

basic loop

while … loop

5. Next and Exit Statement: The next statement skips execution to the next iteration

of a loop statement and proceeds with the next iteration.

6. Wait statement: The wait statement will halt a process until an event occurs.

7. Null statement: The null statement states that no action will occur.

The syntax is null;

8. Assertion Statement: Used for internal consistency check or error message

generation.

[label:] assert Boolean condition [report string] [severity name];

9. Report Statement: Used to output messages.

[label:] report string [severity name];

10. Subprograms: Sub programs are divided into Functions and Procedures. Both

procedures and functions written in VHDL must have a body and may have

declarations. Procedures perform sequential computations and return values in

global objects or by storing values into formal parameters

11. Procedure Call Statement: Call a procedure.

[label:] procedure-name [(actual parameters)];

5.4.2 Dataflow ModelingA dataflow model specifies the functionality of the entity without explicitly

specifying its structure. This functionality shows the flow of information through the entity, which is expressed primarily using concurrent signal assignment statements and block statements. This is in contrast to the behavioral style of modeling in which the functionality of the entity is expressed using statements that are executed sequentially.Concurrent Statements

Signal Assignment Statement: The signal assignment statement is typically

considered as a concurrent statement rather than as a sequential statement. It can

be used as a sequential statement but has the side effect of obeying the general

rules for when the target actually gets updated.

Variable Assignment Statement: Assign the value of an expression to a target

variable.

[Label:] target: = expression;

Block Statement: A block statement is a concurrent statement. It can be used for

three major purposes:

a. To disable signal drivers by using guards.

b. To limit scope of declarations, including signal declarations.

c. To represent a portion of a design.

5.4.3 Structural ModelingA structural description of a system is expressed in terms of subsystems

interconnected by signals. Each subsystem may in turn be composed of an interconnection of subsystems, and so on, until we finally reach a level consisting of primitive components, described purely in terms of their behavior.

A structural description can best be compared to a schematic block diagram that can be described by the components and the interconnections. VHDL provides a formal way to do this by

Declaring a list of components being used.

Declaring signals which define the nets that interconnect components.

Label multiple instances of the same component so that each instance is uniquely

defined.

VHDL Structural Elements

The main units in VHDL are entities, architectures, configurations and packages

(together with package bodies).

Entity : Interface

Architecture : Implementation, behavior, function

Configuration : Model chaining, structure, hierarchy

Package : Modular design, standard solution, data types, Constants

a.Entity

While an entity describes an interface consisting of the port list most of the time,

architecture contains the description of the function of the corresponding module. In

general, a configuration is used for simulation purposes, only. In fact, the configuration is

the only simulatable object in VHDL as it explicitly selects the entity/architecture pairs to

build the complete model. Packages hold the definition of commonly used data types,

constants and subprograms. By referencing a package, its content can be accessed and

used

Entity entity-nameisport(signal-names: mode signal-type;signal-names: mode signal-type; …….

signal-names: mode signal-type); end entity-name;b.Architecture

An architecture body describes the internal view of an entity. It describes the

functionality or the structure of the entity. The syntax of an architecture body is:

Architecture is split into an optional declarative part and the definition part. The

declarative part is located between the keywords ' is ' and ' begin '. New objects that are

needed only within the architecture constants, data types, signals, subprograms, etc. can

be declared here.

Architecture architecture-nameof entity-name istype declarationssignal declarationsconstant declarationsfunction definitionsprocedure definitionscomponent declarations

beginconcurrent-statement……...concurrent-statement

end architecture-name;c.Configuration:

A Configuration statement is used to bind a component instance to an entity-

architecture pair.

d.Package:

The VHDL design unit package is used to store data that will be accessed by

multiple modules. This usually includes constants, data types, sub-types, sub-program

declarations, etc

Package Body:

The package body is a dependent unit of the package. It is used to store details of

the objects declared in the package. This includes sub-programs, algorithms, etc

Library:

Usually referred to as the work library. This is an actual sub-directory or physical

location used to store all compiled design units. Each simulator or synthesis tool will

create such a structure

5.5 OPERATORSVHDL supports different classes of operators that operate on signals, variables

and constants.

Class

1.Logical operators And Or Nand Nor xor Xnor

2.Relational operators = /= < <= > >=

3. Shift operators Sll Srl Sla Sra rol Ror

4.Addition operators + = &

5. Unary operators + -

6. Multiplying operators * / Mod Rem

7. Miscellaneous operators ** Abs Not

Table 5.5 operators

The following table gives the properties used in our project

Fig 5.5 Properties used in the project

5.6 APPLICATIONSVHDL is used mainly for the development of Application Specific Integrated

Circuits (ASIC s). Tools for the automatic transformation of VHDL code into a gate-level

net list were developed already at an early point of time. This transformation is called

synthesis and is an integral part of current design flows.

For the use with Field Programmable Gate Arrays (FPGA s) several problems exist. In the first step, Boolean equations are derived from the VHDL description, no matter, whether an ASIC or a FPGA is the target technology. But now, this Boolean code has to be partitioned into the configurable logic blocks (CLB) of the FPGA. This is more difficult than the mapping onto an ASIC library. Another big problem is the routing of the CLB s as the available resources for interconnections are the bottleneck of current FPGAs.

While synthesis tools cope pretty well with complex designs, they obtain usually only suboptimal results. Therefore, VHDL is hardly used for the design of low complexity Programmable Logic Devices (PLD s).

An ongoing field of research is the hardware/software design. The most interesting question is which part of the system should be implemented in software and which part in hardware. The decisive constraints are the costs and the resulting performance.

CHAPTER 6RESULTS

The output of the project is to obtain various characteristics of the adders like RTL schematic, stuck at faults, fault coverage. 6.1 OUTPUT WAVE FORMS6.1.1 FULL ADDER

Fig 6.1.1 Wave Form of Full Adder 6.1.2 RIPPLE CARRY ADDER

Fig 6.1.2 Wave Form of Ripple Carry Adder

6.1.3 CARRY LOOK AHEAD ADDER

Fig 6.1.3 Wave Form Of Carry Look Ahead Adder

6.1.4 CARRY SAVE ADDER

Fig 6.1.4 Wave Form Of Carry Save Adder

6.1.5 BILBO SERIAL SCAN MODE

Fig 6.1.5 Wave Form Of Serial Scan Mode6.1.6 BILBO LFSR MODE

Fig 6.1.6 Wave Form Of LFSR Mode

6.1.7 BILBO D FF MODE

Fig 6.1.7 Wave Form Of D FF Mode6.1.8 BILBO MISR MODE

Fig 6.1.8 Wave Form Of MISR Mode

6.2 TECHNOLOGY SCHEMATIC 6.2.1 FULL ADDER

Fig 6.2.1 Technology schematic of full adder

6.2.2 RIPPLE CARRY ADDER

Fig 6.2.2 Technology schematic of ripple carry adder


Fig 6.2.3 Technology schematic of carry look ahead adder

6.2.4 CARRY SAVE ADDER

Fig 6.2.4 Technology schematic of carry save adder

6.2.5 BILBO

Fig 6.2.5 Technology schematic of BILBO

6.3 SIMULATION RESULTS OF STUCK AT FAULTS6.3.1 RIPPLE CARRY ADDER

Fig 6.3.1 Simulation Results of Stuck at Fault for Ripple Carry Adder

No. of faults introduced: 58No. of faults detected: 55

Percentage of fault coverage:5558

*100 = 94.82


Fig 6.3.2 Simulation Results of Stuck at Fault for Carry Look Ahead Adder

No. of faults introduced: 58No. of faults detected: 57

Percentage of fault coverage:5758

*100 = 98.27

CONCLUSION

In this project, we have implemented and tested various types of adders which includes ripple carry, carry look ahead and carry save adder using self test(BILBO).Apart from the designing part, we test the designed adders to find whether the circuit is faulty or not. The simulator used is ISE with Xilinx 7.1 version.

Adders are one of the most important components of many systems. Adders are very important basic component in digital systems, because of their extensive use in other basic digital operations such as subtraction, multiplication and division. So we always need to find a better solution in case of adders.

The adders should always consume less power and produce less delay. So through our project we tried to determine which of the three adders works the best. Also as the number of bits used for adders increases, the circuit becomes more complex for testing. Main advantage of this project is that the test patterns are not applied by external Automatic Test Equipments (ATEs) but generated by inbuilt testing circuit. This aspect impacts the cost/time constraint. Also it saves the memory requirement. The biggest advantage of using this project is, the designed circuits can test itself and determine whether it is good or bad using fault coverage.

FUTURE ENHANCEMENT The VLSI field involves packing more and more logic devices into smaller and smaller areas by which the complexity of the circuits increases. Testing of such complex circuits is very difficult. One of the major concerns in testing is the large volumes of test data for reasonably large circuits. As the test data increases the memory required for storing them also increases.

Some of the future work that can be performed along this project may be designing of all the available adders and to compare them with their delays, power consumptions. Along with designing part, the adders can also be tested to find their fault coverage. When longer sequences are used, signature analysis gives high fault coverage.

REFERENCES

1) L.T.Wang, Cheng-Wen Wu and Xiaoqing Wen, “VLSI Test Principles &

Architectures Design for testability”.

2) M.J. Smith, “Application Specific Integrated Circuits”.

3) Charles E. Stroud, “A Designer’s Guide to Built-In Self-Test”, University of North

Carolina at Charlotte, ©2002 Kluwer Academic Publishers New York, Boston,

Dordrecht, London, Moscow.

4) Morling R. C. S., “Designing for Testability”, MSc VLSI System Design, Univ. of

Westminster, Dec. 2000.

5) Psarakis, M., D. Gizopoulos and A. Paschalis, “Test Generation and Fault Simulation

for Cell Fault Model Using Stuck at Fault Model Based Test Tools”, Electronic

Testing Journal: Theory and Applications, vol. 13, no:3, Dec. 1998.

URL’S

1) http://www.wikipedia.com

2) http://www.xilinx.com

3) http://www.examsadda.com/2011/01/vlsi-introduction-to-vlsi-circuits-and.html

TEXTBOOKS

1) Circuit Design using VHDL, by Pedroni .

2) VHDL by Sjoholm Stefan.

3) VHDL by B Bhaskar.

4) Introduction to VLSI systems by Carver mead-lynn convay

5) Basic VLSI design 3rd edition by Douglas.A.Pucknell

6) Fault coverage problems in reconfigurable VLSI systems by RanLibeskind-Hadas

7) VHDL for programmable logic by Kevin skahill.

implementation and testing of adders using bist

Documents