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Implementation of a noise subtraction algorithm using Verilog HDL University of Massachusetts, Amherst Department of Electrical & Computer Engineering, Course 559/659 by Perry Levy, Aseem Pangotra, Stephan Stiglmayr and Thomas Kunkel Team Leader: Prof. Maciej Ciesielski

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Implementation of a noise subtraction algorithm using Verilog HDL University of Massachusetts, Amherst Department of Electrical & Computer Engineering, Course 559/659 by Perry Levy, Aseem Pangotra, Stephan Stiglmayr and Thomas Kunkel Team Leader: Prof. Maciej Ciesielski. - PowerPoint PPT Presentation

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Page 1: Implementation of a noise subtraction algorithm using Verilog HDL

Implementation of a noise subtractionalgorithm using Verilog HDL

University of Massachusetts, AmherstDepartment of Electrical & Computer Engineering, Course 559/659

by Perry Levy, Aseem Pangotra, Stephan Stiglmayr and Thomas KunkelTeam Leader: Prof. Maciej Ciesielski

Page 2: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

Time to frequency transformation

Subtraction of magnitudes

Distortion correction

Frequency to time transformation

AlgorithmAlgorithm

Modules

FFT

Subtraction

In- / Output

Page 3: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

Algorithm

ModulesModules

FFT

Subtraction

In- / Output

Page 4: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

Serial data

Shifts of 16bits

Storing in 1032 x 32bit memory

Flushing memory to FFT after receiving of 256 pairs of

data

Algorithm

Modules

FFT

Subtraction

In- / OutputIn- / Output

Page 5: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

State machine

storing data in memory

Flushing memory

Buffering dataEmptyingbuffer

Reset 256 pairs

Memflushed

Buffer emptied

Algorithm

Modules

FFT

Subtraction

In- / OutputIn- / Output

Page 6: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

Block Diagram

Data

SCLK

LRCLK

Reset Data

Address

WR RD

Flushing

EnableDone

Hold

Data

Real part

Imaginary

Valid

OutputSerial shifter

16bit counter

Address generator

Buffer

Finite state machine

1024 x 32bitRAM

Algorithm

Modules

FFT

Subtraction

In- / OutputIn- / Output

Page 7: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

Parallel input and output of variables

16Bit address, 8Bit data (compatible to microcontroller)

Preset values when resetting

Algorithm

Modules

FFT

Subtraction

In- / OutputIn- / Output

Page 8: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

Implementation of Radix 2 algorithm

Window length 1024

16Bit fixed point arithmetics

2 FFTs at the same time by using real and imaginary signal

Reconstruction afterwards needed

Algorithm

Modules

FFTFFT

Subtraction

In- / Output

Page 9: Implementation of a noise subtraction algorithm using Verilog HDL

C k Ak W k B k Dk AK W k B k

Noise-subtracting algorithm

Butterfly structure as fundamental cell

Algorithm

Modules

FFTFFT

Subtraction

In- / Output

Page 10: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

-1

-1

-1

-1

-1

-1

-1 -1

-1

-1

-1

W0

W0

W2

W2 W3

W0

W2

W1

f(0)

f(7)

F(0)

F(1)

F(2)

F(3)

F(4)

F(5)

F(6)

F(7)

Signal-flow Graph for 8 point FFT

Algorithm

Modules

FFTFFT

Subtraction

In- / Output

Page 11: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

Sequential implementation

1Bit shiftdown after each step to prevent overflow

RAM 1024 x 32Bit

Controller (Finite state machine)

Address generator

Coefficient ROM

Algorithm

Modules

FFTFFT

Subtraction

In- / Output

Page 12: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

ram

_a

dd

r1

Controller

Address Generator

RAM

ButterflyProcessor

Coeff. ROMrom_addr

ram

_a

dd

r2 twiddle

write_enread_en

DataBus

io_

mo

de

fft_

mo

de

inp

ut_

mo

de

fft_

do

ne

io_

do

ne

bus_select

Data In

Data Out

input_readyoutput_ready

10

10

10

32

32 32

32

FFT PROCESSOR

Block Diagram

Algorithm

Modules

FFTFFT

Subtraction

In- / Output

Page 13: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

Delay estimation

• Input: 512

• FFT processing: 2*512*10

• output: 512

Sum 11264 clock cycles

Algorithm

Modules

FFTFFT

Subtraction

In- / Output

Page 14: Implementation of a noise subtraction algorithm using Verilog HDL

0 2000 4000 6000 8000 10000 120000

100

200

300

400

500Verilog output

ab

s(X

1)

0 2000 4000 6000 8000 10000 120000

100

200

300

400

500Matlab FFT (32 bit float)

frequency

ab

s(X

2)

Noise-subtracting algorithm

Simulations

Algorithm

Modules

FFTFFT

Subtraction

In- / Output

Page 15: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

Spectra reconstruction

12F k F nk

12F k F nk

12F k F nk

12F k F nk

Re

ImRe

Im

Re

ImAlgorithm

Modules

FFTFFT

Subtraction

In- / Output

Page 16: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

Error compared to 32bit floating point

0 2000 4000 6000 8000 10000 120000

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4Absolute Error

Algorithm

Modules

FFTFFT

Subtraction

In- / Output

Page 17: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-1

-0.5

0

0.5

1x 10

4 Time window weighted with hanning function (dumped from FFT memory)

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-1

-0.5

0

0.5

1x 10

4

)5002sin()17002cos( tjtx

Error compared to 32bit floating point

Algorithm

Modules

FFTFFT

Subtraction

In- / Output

Page 18: Implementation of a noise subtraction algorithm using Verilog HDL

0 1000 2000 3000 4000 5000 60000

1

2

3

4x 10

5 Recontructed Spectra

MatlabVerilog

0 1000 2000 3000 4000 5000 60000

1

2

3

4x 10

5

frequency [Hz]

(absolute values plotted)

Noise-subtracting algorithm

Error compared to 32bit floating point

Algorithm

Modules

FFTFFT

Subtraction

In- / Output

Page 19: Implementation of a noise subtraction algorithm using Verilog HDL

C.O.R.D.I.C

• An acroynm for:

– Coordinate Rotation DIgital Computer

Page 20: Implementation of a noise subtraction algorithm using Verilog HDL

CORDIC? WHY USE IT?

CORDIC was derived by Volder in the 50’s to calculate trigonometric function.

CORDIC can also calculate hyperbolic, linear and logarithmic functions.

CORDIC processing offers high computational rates fast enough for demanding DSP tasks.

Hardware-efficient algorithm, requires only shifts and adds.

Page 21: Implementation of a noise subtraction algorithm using Verilog HDL

THE CORDIC ALGORITHM• Provides an iterative

method of performing vector rotations by arbitrary angles using only shifts and adds.

• Multiplication by tangent term can be avoided if the rotation angles are restricted to tan()=2^-i.

• In digital hardware = simple shift operation.

The individual equations can be rewritten rearranged so that:

The basic CORDIC-equations for rotation and vectoring mode:

Page 22: Implementation of a noise subtraction algorithm using Verilog HDL

Vectoring and Rotation Modes

• Rotation mode performs Polar to Cartesian transformation by rotating the input vector by a specified angle (given as an argument).

• Vectoring mode performs Cartesian to Polar transformation by rotating input vector to the x-axis while recording the angle required to make that rotation.

Page 23: Implementation of a noise subtraction algorithm using Verilog HDL

Word-Parallel Pipelined CORDIC

• CORDIC Processor core built around three fundamental modules:– Pre-Processor: manipulates inputs to fit in -1 to +1

rad. so that the algorithm covers entire 2 range.– CORDIC core: performs actual algorithm in parallel

using a pipeline of CordicPipe blocks.– Post-Processor: places results in correct quadrant.

Page 24: Implementation of a noise subtraction algorithm using Verilog HDL

RECTANGULAR TO POLAR CONVERSION

• Takes two 16-bit signed words as inputs (Xin,Yin)

• CORDIC core returns equivalent polar coordinates where Rout is the magnitude and Aout is the angle.

• Outputs are in fractional format with the upper 16-bits represent decimal value and lower 4-bits represent fractional value.

Page 25: Implementation of a noise subtraction algorithm using Verilog HDL

POLAR TO RECTANGULAR CONVERSION

• Takes 16-bit magnitude from subtraction and stored angle as inputs (Rin, Ain).

• CORDIC core returns equivalent rectangular coordinates Xo and Yo.

• Core only converges in the range -90 to +90 degrees, must write a pre and post processor so that algorithm covers entire 2 range.

Page 26: Implementation of a noise subtraction algorithm using Verilog HDL

FUTURE WORK

Need to write test bench for rect2polar and polar2rect modules.

Need to finish writing pre and post processor for polar2rect module.

Need to connect my modules to my partners modules.

Need to test and verify that they work well together.

Page 27: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

16

Alpha

Beta

Sub

Comp asel

b

1 if x>y, else 0x

Block diagram

Algorithm

Modules

FFT

SubtractionSubtraction

In- / Output

Page 28: Implementation of a noise subtraction algorithm using Verilog HDL

Noise-subtracting algorithm

• Inputs: two, 16 unsigned bits each ( A and B)• Multiplication: Alpha and Beta terms• Subtraction: ((original A)-(Alpha*B))• Comparators: (A > B) out =1, else out =0• Multiplexer: (Inputs: Select, A*Beta, subtractor output) Select = 1, final_out = x Select = 0, final_out = y

Algorithm

Modules

FFT

SubtractionSubtraction

In- / Output

Page 29: Implementation of a noise subtraction algorithm using Verilog HDL

FUTURE WORK

Connect all modules together. Need to write and verify RTL code. Synthesize all code and implement in FPGA. Test FPGA.


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