implementation of digital system
TRANSCRIPT
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Implementation
of
Logic Circuits
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Digital Systems
Combinational Logic Circuits
Sequential Circuits
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Three main types of chips
Standard chips
Programmable Logic Devices Custom Chips
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Standard Chips
Fixed Functionality
7400-series standard chips
SSI (Small Scale Integrated circuit) :less than 10 gates
MSI (Medium Scale Integrated circuits) : about 10 to100 gates
LSI (Large Scale Integrate circuits) : about 100 to10,000 gates
VLSI (Very Large Scale Integrated circuits) : over10,000 to 100,000 gates
ULSI (Ultra Large Scale Integrated Circuits) : over100,000 gates
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PLD (Programmable Logic Devices)
prefabricated, contain logic gates and
programmable switches
PLA (Programmable Logic Array), PAL(Programmable Array Logic), CPLD
(Complex Programmable Logic Devices)
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PLA (Programmable Logic Array)
Implement m functions ofn variables
ROM function withn inputs / m outputs (Fig. 3.24)
Logic (Boolean) functions in Sum-of-product
A collection of AND gates th
at feed a set of OR gates (Both
AND and OR gates are programmable) (Fig. 3.25)
Example Fig. 3-26. 3-inputs, 4-products term, 2-outputs (Fig.3.27)
Commercial PLA, 10-inputs, 32-products term, 8-outputs
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Two difficulties for manufacture PLA:
They were hard to fabricate correctly
Th
ey reduce th
e speed-performance of circuitsimplemented in the PLA s.
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PAL (Programmable Array Logic)
AND plane is programmable, OR plane is
fixed.
They are simpler to manufacture. less expensive than PLA
offer better performance
Example Fig.3.28. 3-inputs, 4-product terms,2-outputs
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Comparison between PLA and PAL
Fig. 3.27. 4-product terms for one OR gate
Fig. 3.28. 2-product terms for one OR gate PLA offer less flexibility
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CPLD (Complex Programmable Logic
Device)
CPLD Multiple PAL-like blocks on a single
chip with internal wiring resources to connect
the circuit block.
(Fig. 3.32) (Fig. 3.33)
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FPGA field programmable gate array
support relatively large logic circuit dont contain AND and OR planes
provide logic blocks for implementation of the
required function
logic blocks, I/O blocks (for connecting to the pins of
the package), interconnection wires and switches.
logic blocks: two-dimensional array
interconnection wires : horizontal/ vertical routing channel
Fig. 3.35
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Programmable connection exist between the I/O blocksand interconnection wires.
Implement 100,000 gates in size
Each logic block contain a small enough logic function
The logic blocks are programmed to realize thenecessary functions and routing channels are
programmed to make the required interconnection (Fig.
3.36) (Fig. 3.37) (Fig. 3.39) FPGA is volatile (loss the stored content when the
power supply is turned off)
PROM holds the data permanently
Loading automatically PROM FPGA
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PLD (Programmable Logic Device)
user programmability
consume a significant amount of space on the
chip
reduce the speed of operation of the circuit
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Custom chip
complete flexibility to decide
the size of the chip
th
e no. of transistors th
e ch
ip contain the placement of each transistor on the chip
the way the transistor are connected together
define exactly where on the chip each transistor
and wire is situated (chip layout)
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Custom Chip
A very large amount of transistors
( 1,000,000 transistors)
High speed performance Small area is needed and reduce the cost
Takes a considerable amount of time
ASIC (Application Specific Integrated Circuit)
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Standard Cell Technology
The available gates are pre-built and are stored
in a library that can be accessed by t
he
designer
Fig. 3.40
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Gate Array Technology
Parts of the chip prefabricated, the other partsare custom fabricated
ICs are fabricated in a sequence of steps
some steps to create transistors
the other steps to create to connect the transistortogether.
Fig. 3.41 Fig. 3.42
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Design of Logic CircuitsA typical CAD System comprises tools for performing the
following tasks: Design entry: enter a description of the desired circuit in the
form of truth table, schematic diagrams, or VHDL code
Initial synthesis: generate an initial circuit, based on dataentered during the design entry stage
Functional simulation: verify the functionality of the circuit,based on inputs provided by the designer
Logic synthesis and optimization: derive an optimized circuit
Physical design: determine how to implement the optimized
circuit in a given target technology, for example, in a PLD chip Timing simulation: determine the propagation delays that are
expected in the implemented circuit
Chip configuration: configures the actual chip to realize thedesign circuit
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Design entry: enter a description of the desired circuit in the form
of truth table, schematic diagrams, or VHDL code
j Description of the circuit being design
j Done by designer because it requires design experience and intuition
j There are three design entry methods:i Using truth table: only for function with a small number of variables, not
appropriate for large circuits
i Using schematic capture:
i Using the graphics capabilities of a computer and a computer
mouse to allow the user to draw a schematic diagram
j The collection of symbols is called a library
j The tool provides a graphical way of interconnecting the gates to create
a logic network (Graphic Editor)
j A disadvantage of using schematic capture is that every commercial tool has a
unique user interface and functionality Writing source code in a HDL
j 1980s IC technology standard design practices for digital circuits
IEEE Standard : VHDL / Verilog HDL
: IEEE 1076 (1987) (original)
: IEEE 1164 (1993) (revised)
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VHDL (Very High Speed Integrated Circuit
HardwareDescription Language)
Two purposes :
A documentation language for describing
the structure of complex digital circuitsModeling the behavior of the digital circuit
CAD tools are used to synthesize the VHDL
code into a hardware implementation VHDL is an extremely complex sophisticated
language
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VHDL offers a number of advantages :
VHDL provides design portability
A circuit specified in VHDL can be
implemented in different types of chips
Each CAD tool provided by differentcompanies without having to change the
VHDL specification
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Initial synthesis:
generate an initial circuit, based on dataentered during the design entry stage
translating or compiling VHDL code into anetwork of logic gates
manipulate the users design to automaticallyproduce an equivalent but better circuit (logicsynthesis or logic optimization)
determine exactly how the circuit will berealized in a specific hardware technology
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Functional simulation:
verify the functionality of the circuit, based
on inputs provided by the designer(functional simulator)
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Logic synthesis and optimization:
derive an optimized circuit
depends on the type of logic resourcesavailable in the target chip and on the
particular CAD system that is used
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Physical design:
determine how to implement the optimizedcircuit in a given target technology, for
example, in a PLD chip
there are two main parts :
placement: determine where in the target device
each logic function in the optimized circuit will
be realized
routing : decide which of the wires in the chip areto be used to realize the required interconnections
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Timing simulation: determine the
propagation delays that are expected in the
implemented circuit
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Chip configuration: configures the actual
chip to realize the design circuit