implementation of mcm and general based structures …

IMPLEMENTATION OF MCM AND GENERAL BASED STRUCTURES USING

CARRY SAVE ADDER

N Udaya Kumar1, A Krishna Vamsi2and K Bala Sindhuri3

1Professor, SRKR Engineering College, Bhimavaram, AP ,India

2 PG Student, SRKR Engineering College, Bhimavaram, AP, India

3 Assistant Professor, SRKR Engineering College, Bhimavaram, AP, India

[email protected], [email protected], [email protected]

Abstract

In FIR filter designing, Multiple-Constant-Multiplication (MCM) based structures have been employed for its

robust scheme of reduced number of additions for the multiplication process. This MCM technique is highly

productive for higher order filter designs that especially deal with fixed coefficients, it enables best way of block

processing in FIR filters and provides performance-scalable structures which exhibit improvement in area-delay

efficiency. In this paper, the MCM based structures are reviewed and an performance analysis of the existing general

structures is proposed and done with the help of the multiplexer based adders which are used in the Ripple Carry

Adder (RCA) and the Carry Save Adder (CSA) designs. To be precise, these two variants of the adder designs that are

being used in filter designing are modified by instantiating four multiplexer-based designs in them and reviewing the

performance of the filter structures for every modified design. This proposed work was done on Vivado v2017.2

software with Verilog HDL as the target language and the simulated results of these proposed designs are noted,

analysed and are presented in this paper with the conclusion. Thus, by the comparison of the different designs it paves

way for the enhanced further implementation of the MCM scheme and its general structures.

Keywords—MCM (multiple constant multiplecation), carry save adder, full adder, half adder, multiplexer based adder, ripple carry adder, block fir filter.

1. Introduction

As environment mostly rely on present technology, where technology glance the usage of materials tools and

machines which makes work done by humans easier. Technological enhancement leads the development, where the

development of human is only possible with advancement in technology. In day to day life humans got dependent on

technology for their productive work in easy mode. There are various gadgets that humans depend on day to day life

like personal systems and handy devices. To make these systems and handy devices work more efficient we need to

update their functioning according to the present technology. Development of devices can be explained by their speed

and consumption of low power.

In various technological applications in VLSI and digital signal processing plays a most significant part in technology

development. In earlier days we pay a penalty of power consumption, area and delay. Previous versions faced

problems in arithmetic calculations due to vast architecture and huge power consumption. The main fundamentals of

International Journal of Research

Volume VIII, Issue V, MAY/2019

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digital circuits are consumption of low power and with high speed. Reducing the power consumption of a system

vary depending on their applications. Considering personal systems and mobile gadgets consumes power depending

on their applications and working, whereas mobile gadgets require less power with less weight and with less cost,

compared to that of laptops required to consume less power than total power dissipation. Many filter structures have

been proposed by various researchers, till today there are finding many structures for achieving energy saving devices.

The researchers have proved there are various scopes for optimization.

Lower the power dissipation of systems lower the electricity consumed and lower the impact on the present

environment. Filters are the devices which performs signal processing to remove unwanted signal especially and to

allow to required signal. Thus, the design of fir filter must be careful to consume less power. To implement the fir

filter block multiplication of inputs with the filter coefficients. The filter coefficients are constant, so multiplying

these constants with inputs is called constant multiplication. The constant multiplication may be single constant or

multiple constant multiplication[1] Such as single constant multiplication is referred as one filter coefficients is

multiplied with input, whereas multiple constant multiplication is referred as multiple filter coefficients is multiplied

with the input.

2. EXISTING METHOD

In case of existing method, Here MCM(multiple constant multiplication) refers to an arithmetic operation that

drives by multiplying a set of fixed-point constants C, C(0), C(1), C(2),……,C(n-2), C(n-1) with similar fixed point

variable x. In this existing method it has block FIR filter which consists of five stages [2-3]. These five stages are

nothing but the registers and adders used for conversion and addition. Registers used in this technique are

(SIPO),(PIPO) & (PISO) and the adder used in this are ripple carry adder. In this serial to parallel conversion is done

in (SIPO) and parallel to parallel conversion in (PIPO) and parallel to serial conversion is done in (PISO), similarly

adder is used for addition operation as shown in Figure .1.

Figure 1. Generalized block diagram.

In this existing method consists of L-way N-tap fir filter. The way (L) points the number of inputs for fir filter,

where it is simply a delay or coefficient pair and ‘N’ indicates either the amount of required memory and filtering for

implementations of filter or number of calculations required. More taps refer more stopband attenuation and narrow

filters, etc. In case of N-way L-tap FIR filter, defines that in a way

1) N+L-1 recent samples are used for computation.

2) A serial-in parallel-out block gives N outputs.

3) Parallel -in parallel-out register gives N+L-1 outputs.



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4) The constant multiplication block provides necessary add and shift operations to generate L output samples.

5) Parallel in serial out registers accepts all the ‘N’ output samples from adder trees and delivers them out sequentially

in subsequent L cycles.

In general, for an N-tap, L-way block fir filter,(N+L-1) most recent inputs samples are used in the computation, and

(N+L-3) units can be constructed for resource sharing optimization. The maximum number of constants in the MCM

units (order of MCM) is M=min (L, N).for those MCM units, the order of MCM increases from 2 to M

(corresponding to the second to the Mth input samples), and decreasesfrom Mto2

In this existing method the adder tree usedis general ripple carry adder[4-6].Ripple carry adder is used to ripple the

carry. In this ripple carry adder full adder blocks are in a sequential chain blocks where the carry is rippled shows that

carry is propagated from initial block to final block. After inputs is loaded, registers converts the data whereas serial

to parallel conversion is don next to that parallel to parallel conversion is done so after arithmetic operations are

carried away by MCM (multiple constant multiplication) block. Then values are given to adder tree used here is

general ripple carry adder where the final sum and carry are loaded in parallel to serial conversion and outputs are

obtained. But due to usage of ripple carry adder leads to increase in delay and more power consumption. In case ripple

carry adder sum has to wait until the carry from the previous stage arrived. To modify the above drawbacks using

ripple carry is replaced by carry save adder in the proposed method[7-8]. The block diagram of carry save adder is

shown in Figure 2.

Figure2. Block diagram of modified carry save adder.

3. PROPOSED METHODOLGY

In this section,there is a clear discussion of proposed architecture. In this proposed method for L-way N-tap,

consideredmethods in thiswork are are 2-way 8tap, 4-way 8tap & 8-way 8tap. To give clear explanation regarding

these architectures, further look into the organization of these above discussed architectures in detailed manner

3.1. 2-way 8tap architecture:

The stages of 2-way 8-tap filter are

SIPO: the serial-in parallel-out (SIPO) registers is of order 2. The SIPO registers gathers an input block of 2 new

samples and feeds them in parallel for every 2 cycles to first 2 locations of PIPO register.

PIPO: The parallel-in parallel-out register is of size 9. Whenever the SIPO register feed the 2 new samples, the old

values are shifted by 2 positions to the right and last two values are discarded.



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ARITHMETIC BLOCK: The 2-way 8-tap filter consists of 8filter constants, (h0, h1, h2, h3, h4, h5, h6, h7). This

block consists of 2 SCM units and 7 MCM units. The MCM units are constructed for resource sharing optimization.

The maximum order MCM units is given by min (2, 8) =2

ADDER BLOCK: The adders used here are carry save adder and ripple carry adder. It consists of two adder trees

each of which can add up to 8 inputs. The inputs to adder tree are given by the SCM and MCM. The adder block

generates two outputs and loaded into PISO of size 2.

PISO: the parallel in serial out register accepts the output samples and delivers them out sequentially in the

subsequent of 2 cycles. The architecture of 2-way 8-tap block FIR filter is depicted belowFigure 3.

Figure3. Block diagram of 2-way 8-tap

As explained earlier about 2-way 8-tap this process carries out familiar to both 4-way 8-tap and 8-way 8-tap the

blocks that existed in 2-way 8-tap are repeated same in both 4-way 8-tap and 8-way 8-tap. But the changes that makes

the differences are order of MCM, where 4-way 8-tap has 4 location cycles and register size to note is 13. Here the

order increases from 2 to 4 and decreased from 4 to 2, hence it can be referred in figure 4. The minimum order is

given by min (4, 8) =4. The same content is to be explained in 8-way 8tap as the order is increased from 4 to 8 and

decreased from 8 to 4 with 8 location cycles and register to be noted is of size is 15.



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Figure 4. Block diagram of 4-way 8-tap.

To overcome the drawback of existing method adder tree used in this are carry save adder. To get clear view

regarding carry save adder used, here it is an extension to the previous adder. In carry save adder consists of 3:2

counter which implies 3 inputs and 2 outputs. i.e... (X, Y,Z) are inputs and the outputs are sum and carry i.e.… (C, S).

The proposed adder consists of full adders cascaded sequentially in two half’s that lower half and upper half. Where

as in upper half contains a continuous chain of full adders with three inputs and gets partial outputs and these partial

outputs are connected to lower block, here lower blocks initially consist of half adder later followed by full adder and

ends with half adder for better view refer Figure.2.To extent this work the general ripple carry adder and carry save

adder are modified with full adder. This modified full adders are replaced by multiplexer-based adders. Various

multiplexer-based adder is used in both ripple carry adder and carry save adder [9-10]. This reduces the more power

consumption and reduces the delay. To get better knowledge regarding this multiplexer based adders are derived

below.The multiplexer based full adder consists of two 2:1 multiplexer and one Not gates. Here A, ~A and B, A are

inputs of the two multiplexers. The output of XOR gate is given to the selection line for two multiplexers, these two

multiplexers outputs are sum and carry respectively . The inputs for XOR gates are Cin, B is shown in below Figure.5.

Figure 5. Full adder using two 2:1 multiplexers.Figure. 6. Full adder using two 4:1 multiplexers and a Not gate

In this modified full adder consists of two 4:1 multiplexers here a, b are two selection lines for both the multiplexers C is the only

input to the multiplexer that gives sum as output, 0,c,1 are the inputs for the multiplexer that gives carry as the output.After

studying the conventional full adder design, a multiplexer based design is modeled by identifying its operation using truth table



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and the input and output values when logic 0 and logic 1 as input at the consequent input line. Using this multiplexer-based adder

designs it can be observed that there is a maximum reduction in the gate count of the logic design, thus making it an efficient

implementation and this is shown in above Figure 6.

Figure 7.Full adder using two 2:1 multiplexers. Figure. 8. Full adder using five 2:1 multiplexers

A multiplexer based design is modeled by analyzing its operation using truthtable. The analysis consists of input,

output relationship when logic 0, logic 1 are given as inputs at respective input line.Multiplexer based full adder

consists of XOR, XNOR, AND, OR gates and 2:1 multiplexer.Each gate output is provided as one of the inputs to

the respective multiplexer. Sum and carry are the outputs of the two multiplexers and this is shown in Figure 7.

Multiplexer based full adder consists of five 2:1 multiplexer and two Not gates. Here inputs of the three

multiplexers consists of ‘c’, inverted c,‘0’ and ‘1’ input combinations, here inverted c is obtained by using Not gate,

‘A’ is the selection line for the three 2:1 multiplexers and B is selection for the other two 2:1 multiplexers. The

outputs of first stage 2:1 multiplexers are given as inputs to the next stage 2:1 multiplexers. In this second stage two

2:1 multiplexer produce sum and carry outputs respectively for better understanding refer Figure 8.To extent this work

the general ripple carry adder and carry save adder are modified with full adder. This modified full adders are

replaced by multiplexer based adders. Various multiplexer based adder are used in both ripple carry adder and carry

save adder. Toshow the performance analysis of both adders.

4. Results and Comparison

This proposed design is synthesized and simulated in Xilinx’s synthesis tool. The simulation results for 2-way 8-tap

are

Inputs for FA1, FA2, FA3, FA4 ‘x’, ‘RST’, ‘CLK’, ‘INP’ and constants (h0, h1, h2, h3, h4, h5, h6, h7) are given

in both hexadecimal and numerical value as ‘FF’, ‘1’s and ‘0’s and the obtained outputs are in hexadecimal values

for FA1,FA2, FA3, FA4 are ec, ec, f3, ec. are shown in Figure 8-11.



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Figure 8. simulated results for mcm modified carry save adder fa1Figure 9. simulated results for mcm modified carry save adder fa2

Figure 10. simulated results for mcm modified carry save adder fa3 Figure 11. Simulated results for mcm modified carry save adder fa4

The simulation results for 4-way 8-tap are

Inputs for FA1, FA2, FA3, FA4 ‘x’, ‘RST’, ‘CLK’, ‘INP’ and constants (h0, h1, h2, h3, h4, h5, h6, h7) are given in both

hexadecimal and numerical value as ‘FF’, ‘1’s and ‘0’s and the obtained outputs are in hexadecimal valuesfor FA1,FA2, FA3,

FA4 are f1, f1, ec, ec. are shown in Figure 12-15.

Figure 12. simulated results for mcm modifiedcarry save adder fa1Figure13. Simulated results for mcm modified carry save adder fa2

Figure 14. simulated results for mcm modifiedcarry save adder fa3Figure 15. Simulated results for mcm modified carry save adder fa4

The simulation results for 8-way 8-tap are



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Inputs for FA1, FA2, FA3, FA4 ‘x’, ‘RST’, ‘CLK’, ‘INP’ and constants (h0, h1, h2, h3, h4, h5, h6, h7) are given in

both hexadecimal and numerical value as ‘FF’, ‘1’s and ‘0’s and the obtained outputs are in hexadecimal valuesfor FA1,FA2,

FA3, FA4 are f1, ee, ee, ec. are shown in Figure. 16-19.



For better understanding refer below comparison table between MCM (multiple constant multiplication) modified

ripple carry adder and modified carry save adder

TABLE .1 COMPARISON OF DELAY, POWER AND LUT’S IN 2-WAY 8-TAP, 4-WAY 8TAP, 8-WAY

8TAP WITH MODIFIED CSA (M CSA)

TYPES OF FILTERS

Full

adder

structures

LUT’S

DELAY

(ns)

POWER

(watts)

2-way 8-tap using M

CSA

FA1 4692 6.213 62.916

FA2 4616 6.504 62.59

FA3 4570 6.588 63.899

FA4 4600 6.254 61.846

4-way 8-tap using M

CSA

FA1 9305 6.363 119.044

FA2 8865 6.561 116.674

FA3 9060 6.603 119.576

FA4 9344 6.363 119.473

8-way 8tap using M

CSA

FA1 18646 6.246 220.159

FA2 17564 6.544 226.343

FA3 18101 6.681 223.169



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FA4 18049 6.288 223.913

TABLE .2 COMPARISON OF DELAY, POWER AND LUT’S IN 2-WAY 8-TAP, 4-WAY 8TAP, 8-WAY

8TAP WITH MODIFIED RCA(M RCA)

TYPES OF FILTERS

Full

adder

structures

LUT’S

DELAY

(ns)

POWER

(watts)

2-way 8-tap using M

RCA

FA1 4692 6.213 62.916

FA2 4616 6.504 62.59

FA3 4570 6.588 63.899

FA4 4600 6.254 61.846

4-way 8-tap using M

RCA

FA1 9068 6.807 119.599

FA2 9115 6.401 116.649

FA3 9051 6.603 118.879

FA4 9228 6.756 117.977

8-way 8tap using M RCA

FA1 18060 6.813 231.399

FA2 18361 6.411 228.193

FA3 18038 6.653 229.95

FA4 18403 6.589 227.362

Figure.20. comparison modified RCA-CSA with different adder structures Figure.21 comparison modified RCA-CSA with different adder structures



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Figure.22. comparison modified RCA-CSA with different adder structures

Figure.24. comparison modified RCA-CSA with different adders Figure 23. Comparison modified RCA-CSA with different adders

Figure .25. comparison modified RCA-CSA with different adder structure



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Figure.26. comparison modified RCA-CSA with different adder Figure.27. comparison modified RCA-CSA with different adder

Figure.28. comparison modified RCA-CSA with different adder

Conclusion

MCM based general structures for FIR filter designing are implemented and adders(RCA & CSA) in these

corresponding implementations are modified with the including of multiplexer-based adder designs. This proposed

work has been able to achieve performance analysis of these MCM structures and is successful in its overall agenda

which was to create unique application oriented MCM structural designs. From the observations made by the

simulated results it is clear that for some cases the modified RCA based designs are outperforming the modified CSA

based designs, and are maintaining integrity in improving their designs in terms of POWER, LUT’S and DELAY for

VLSI based design implementation and similarly vice-versa. The novelty of this paper shows the overall performance

analysis of the multiple constant multiplication scheme. So to conclude, due to the proposed work the designs with

better power values are used in low-power applications and values which are better in area are used to fabricate area

efficient designs on compact devices and dsp processors and accordingly the structures that are having less delay are

utilized for faster calculating applications like in FFT algorithms etc., which is nothing but a way of adaptive filter

designing.

REFERENCES

[1] Pramod Kumar Meher, Yu Pan, “ MCM-Based Implementation of Block FIRFilters for High-Speed and Low-Power Applications,” IEEE/IFIP 19

thInternational Conference on VLSI and System-on-Chip, pp.118-121,2011.

[2] Chia-Yu Yao, Hsin-Horng Chen, Tsuan-Fan Lin, Chiang-Ju Chien, & Chun-Te Hsu. (n.d.). A new common-subexpression-sharing method for the synthesis of FIR filters. The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. doi:10.1109/apccas.2004.1412974 .

[3] A. G. Dempster and M. D. Macleod. "Use of minimum addcr multiplier blocks in FIR digital filters," IEEE Tram. Circuits Sysi. 11, vol. 42. pp. 569-577, Sept. 1995



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[4] Shubin, V. V. (2010). Analysis and comparison of ripple carry full adders by speed. 2010 11th International Conference andSeminar onMicro/Nanotechnologies and Electron Devices. doi:10.1109/edm.2010.5568768.

[5] Chih-Jen Fang, Chung-Hsun Huang, Jinn-Shyan Wang, & Ching-Wei Yeh. (n.d.). Fast and compact dynamic ripple carry adder design. Proceedings. IEEE Asia-Pacific Conference on ASIC,. doi:10.1109/apasic.2002.1031523.

[6] L. Montalvo and K.K. Parhi. 1996. Estimation of Average Energy Consumption of Ripple-Carry Adder Based on Average Length Carry Chains. In: proc. 11th Design of Integrated Circuits and Systems Conference (DCIS’96), Barcelona, Spain.

[7] Datta, R., Abraham, J. A., Montoye, R., Belluomini, W., Hung Ngo, McDowell, C., Nowka, K. (n.d.). A low latency and low power dynamic Carry Save Adder. 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512). doi:10.1109/iscas.2004.1329312.

[8] Sarkar, S., Sarkar, S., & Mehedi, J. (2018). Modified CSA-CIA for Reducing Propagation Delay. 2018 International Conference on Computer Communication and Informatics (ICCCI). doi:10.1109/iccci.2018.8441482.

[9] D.Mohanapriya, Dr.N.Saravanakumar, “A Comparative Analysis of Different 32-bit Adder Topologies with Multiplexer Based Full Adder”, DOI 10.4010/2016.1102 , ISSN 2321 3361 © 2016 IJESC

[10] K. Anirudh Kumar Maurya ; Y. Rama Lakshmanna ; K. BalaSindhuri ; N. Udaya Kumar, “Design and implementation of 32-bitadders using various full adders” 2017 innovations in power andadvanced computing technologies (I-PACT),DOI: 10.1109/IPACT.2017.8245176



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