indirect matrix converter...1 indirect matrix converter johann w. kolar thomas friedli eth zurich,...

1

Indirect Matrix ConverterJohann W. KolarThomas Friedli

ETH Zurich, Swiss Federal Institute of TechnologyPower Electronic Systems Laboratory

ETH-Zentrum / ETLCH-8092 Zurich, Switzerland

Phone: +41-44-632-2833Fax: +41-44-632-1212 www.pes.ee.ethz.ch

[email protected]

2

Schedule■ Indirect Matrix Converter (IMC)

Johann W. Kolar, Thomas Friedli- Basics- Comparison with Conventional (Direct) MC- IMC Modulation Schemes- Dimensioning- EMI Filter Design- Hardware Implementation- Experimental Results

Coffee Break

■ Indirect Matrix Converter vs. Back-To-Back ConverterJohann W. Kolar, Thomas Friedli

■ Future Research and Development, DiscussionJohann W. Kolar, Patrick Wheeler

3

Classification of AC-AC Converter Topologies

■ Sinusoidal input and output currents■ Unity power factor at the input■ No energy storage elements: size and weight reduction

MC Features:

4

Indirect Matrix Converter (IMC)

5

Conventional Matrix Converter

a

b

c

A

B

C

a

b

c

A

B

C

Basic Matrix Converter Topologies

Indirect Matrix Converter

2,max 1 13ˆ ˆ ˆ0.866

2U U U= ⋅ = ⋅

6

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛⋅⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛=

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛

c

b

a

C

B

A

uuu

sCcsCbsCasBcsBbsBasAcsAbsAa

uuu

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛⋅⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛=

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛

C

B

A

c

b

a

iii

sCcsBcsAcsCbsBbsAbsCasBasAa

iii

abcABC uSu ⋅=

Voltage Conversion Current Conversion

ABCi ⋅= Tabc Si

Conventional Matrix Converter (CMC)

Mathematical Description of the Basic Operating Behavior

, , :a b cu u u, , :A B Cu u u

Input voltages

Output voltages

, , :a b ci i i, , :A B Ci i i

Input currents

Output currents

7

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛⋅⎟⎟⎠

⎞⎜⎜⎝

⎛⋅⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛=

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛

c

b

a

C

B

A

uuu

scnsbnsanscpsbpsap

snCspCsnBspBsnAspA

uuu

Inv Rect ABC abcu S S u= ⋅ ⋅

Voltage ConversionSplit into Rectifier andInverter Stage

Rect pDC abc

n

uu S u

u⎛ ⎞

= = ⋅⎜ ⎟⎝ ⎠

■ Introduction of a fictitious rectifier and inverter stage■ Fictitious DC link voltage and DC link current■ Modulation as for DC link converters

Indirect Matrix Converter can be considered as a physical implementation of amathematical concept

Conventional Indirect Matrix Converter (IMC)

8

Functional Equivalence of the IMC and the CMC

a

b

c

A

B

C

■ Operation of the IMC is restricted to upn > 0

■ Remaining switching states identical to those of CMC

No. A B C sAa sAb sAc sBa sBb sBc sCa sCb sCc uAB uBC uCA ia ib ic

1 a a a 1 0 0 1 0 0 1 0 0 0 0 0 0 0 02 b b b 0 1 0 0 1 0 0 1 0 0 0 0 0 0 03 c c c 0 0 1 0 0 1 0 0 1 0 0 0 0 0 04 a c c 1 0 0 0 0 1 0 0 1 -uca 0 uca iA 0 -iA5 b c c 0 1 0 0 0 1 0 0 1 ubc 0 -ubc 0 iA -iA6 b a a 0 1 0 1 0 0 1 0 0 -uab 0 uab -iA iA 07 c a a 0 0 1 1 0 0 1 0 0 uca 0 -uca -iA 0 iA8 c b b 0 0 1 0 1 0 0 1 0 -ubc 0 ubc 0 -iA iA9 a b b 1 0 0 0 1 0 0 1 0 uab 0 -uab iA -iA 010 c a c 0 0 1 1 0 0 0 0 1 uca -uca 0 iB 0 -iB11 c b c 0 0 1 0 1 0 0 0 1 -ubc ubc 0 0 iB -iB12 a b a 1 0 0 0 1 0 1 0 0 uab -uab 0 -iB iB 013 a c a 1 0 0 0 0 1 1 0 0 -uca uca 0 -iB 0 iB14 b c b 0 1 0 0 0 1 0 1 0 ubc -ubc 0 0 -iB iB15 b a b 0 1 0 1 0 0 0 1 0 -uab uab 0 iB -iB 016 c c a 0 0 1 0 0 1 1 0 0 0 uca -uca iC 0 -iC17 c c b 0 0 1 0 0 1 0 1 0 0 -ubc ubc 0 iC -iC18 a a b 1 0 0 1 0 0 0 1 0 0 uab -uab -iC iC 019 a a c 1 0 0 1 0 0 0 0 1 0 -uca uca -iC 0 iC20 b b c 0 1 0 0 1 0 0 0 1 0 ubc -ubc 0 -iC iC21 b b a 0 1 0 0 1 0 1 0 0 0 -uab uab iC -iC 022 a b c 1 0 0 0 1 0 0 0 1 uab ubc uca iA iB iC23 a c b 1 0 0 0 0 1 0 1 0 -uca -ubc -uab iA iC iB24 b a c 0 1 0 1 0 0 0 0 1 -uab -uca -ubc iB iA iC25 b c a 0 1 0 0 0 1 1 0 0 ubc uca uab iC iA iB26 c a b 0 0 1 1 0 0 0 1 0 uca uab ubc iB iC iA27 c b a 0 0 1 0 0 1 1 0 0 -ubc -uab -uca iC iB iA

upn

…70 b b c 0 1 0 0 0 1 1 1 0 0 ubc -ubc ubc 0 -iC iC

71 b b a 1 0 0 0 1 0 0 0 1 0 -uab uab uab iC -iC 072 b b a 0 1 0 1 0 0 1 1 0 0 -uab uab -uab iC -iC 0

9

Multi-Step Commutation for CMC / IMC

Constraints:No mains phases short-circuitedNo interruption of iExample: i > 0, uab < 0, aA → bA

10

1st step: off

Example: i > 0, uab < 0, aA → bA


Constraints:No mains phases short-circuitedNo interruption of i

11

1st step: off2nd step: on




12

1st step: off2nd step: on3rd step: off




13

1st step: off2nd step: on3rd step: off4th step: on


Sequence depends oncurrent sign!



14

Zero DC Link CurrentCommutation for IMC

PWMpattern

1/3 mainsperiod

DC link voltage & current

15

PWMpattern

1/3 mainsperiod


u = uac

i = iA

(100)(ac)


16

PWMpattern

1/3 mainsperiod


(110)(ac)

u = uac

i = -iC


17

PWMpattern

1/3 mainsperiod


(111)(ac)

u = uac

i = 0


18

PWMpattern

1/3 mainsperiod


(111)(ab)

u = uab

i = 0


19

PWMpattern

1/3 mainsperiod


(110)(ab)

u = uab

i = -iC


20

PWMpattern

1/3 mainsperiod


(100)(ab)

u = uab

i = iA


21

PWMpattern

1/3 mainsperiod


Summary

Simple and robust modulation schemeas it is independent of voltages andcurrents (sign)

Negligible rectifier switching losses due to zero current commutationof the rectifier stage


22

Space Vector Modulation

601 /...πϕ =

Free-wheeling limited to Inverter Stage

idiidiiddi accabbacaba ==+= ,,)(

1=+ acab dd

1cosΦ1 =

ccbbaa uiuiui ~;~;~

a

b

a

bab

a

c

a

cac u

uii

duu

ii

d −=−=−=−= ;

Intervals considered

Local Average Value of Input Currents

Ohmic Fundamental Mains Behavior

Relative Turn-on Times

602 /...πϕ =

Time Intervals

22 /Td/Td PababPacac == ττ

Derivation

[2]

23

Identical Phase/Duty Cycle of Active Inverter Switching States (100), (110) in τacand τab

)100(),100(

),100(),100(

),100( δτ

τδ

ττ

δ ====ab

abab

ac

acac

)110(),110(

),110(),110(

),110( δτ

τδ

ττ

δ ====ab

abab

ac

acac

uu 32

)100( =

332

)110(

πjueu =

)( ),110(3

),110(3

),100(),100(2

32

*2 ab

jabac

jacababacacT eueuuuu

Pττττ

ππ

+++=

Generated Output Voltage Space Vector

.)()(

)()(

(

)110(3

32

)100(32

)110(3

21

213

2)100(

21

213

2

3)110(

3)110()100()100(

2

32

*2

δδ

δττ

δττ

δτδτδτδτ

π

π

ππ

jababacacababacac

j

P

abab

P

acac

P

abab

P

acac

jbcab

jacacbcabacacT

edudududu

eT

uT

uT

uT

u

eueuuuuP

+++=

+++=

+++=

Local Average Value of the DC Link Voltage

acacabab duduu +=

24

)110(3

32

)100(32*

2 δδπj

euuu +=

Output Voltage Space Vector

Therefore, Calculation of the Relative On-Times of the Active Switching States of the Output Stage can be Directly Based on ū

*2

21

*2

23

)110(

6*2

21

*2

23

)100(

sin||

)cos(||

ϕδ

ϕδ π

uu

uu

=

+=*

*21(100), 2 623

1*

*21(100), 2 623

1*

*21(110), 223

1*

*21(110), 223

1

ˆcos( )ˆ

ˆcos( )ˆ

ˆsinˆ

ˆsinˆ

ac P c

ab P b

ac P c

ab P b

UT u

U

UT u

U

UT u

U

UT u

U

π

π

τ ϕ

τ ϕ

τ ϕ

τ ϕ

= − +

= − +

= −

= −

→ Absolute On-Times

Local Average Value of the DC Link Voltage

)cos(1ˆ

112

3t

Uuω

= 1minˆ23 Uu =

25

Output Voltage System

)cos(ˆ)cos(ˆ

)cos(ˆ

032

2*2

032

2*2

02*2

ϕω

ϕω

ϕω

π

π

++=

+−=

+=

∗

∗

∗

tUu

tUu

tUu

C

B

A

Voltage Transfer Ratio

23

ˆˆ

1

*2 ≤=

UUM

Output Voltage Formation

Inverter Output Voltage Space Vectors Average Output Voltage

11max,2ˆ866.0ˆ

23ˆ UUU ⋅=⋅=

Variation of ū requires a Variationof the Inverter Modulation Index )cos(ˆ

ˆ

34||

11

*2

21

*2

2 tUU

uu

m ω==

26

ϕ2=ω2t Au Bu Cu0 ... π/6 up up, un up, un

π/6 ... π/2 up, un up, un un

π/2 ... 5π/6 up, un up up, un

5π/6 ... 7π/6 un up, un up, un

7π/6 ... 3π/2 un, up up, un up

3π/2 ... 11π/6 un, up un up, un

11π/6 ... 0 up un, up up, un

Clamping of each output phaseover a π/3-wide interval tominimize switching losses

Switch conducting the largestcurrent is clamped

Clamping

Clamping over an Output Period

27

Input Current FormationLoad Phase Currents

)cos(ˆ)cos(ˆ

)cos(ˆ

232

22

232

22

222

Φ++=

Φ+−=

Φ+=

π

π

ω

ω

ω

tIi

tIi

tIi

C

B

A

)110()100(),110(),100(1 )( δδτδτδτ CAacacCacacAac iiiiiac

−=−=

)110()100(),110(),100(1 )( δδτδτδτ CAababCababAab iiiiiab

−=−=

)cos(cosˆˆˆcosˆ

121

*2

222243 t

UUIImiii abac ωΦ=Φ===

Verify Equal Local Average Value ī of the DC Link Current in τac and τab

tii

m1

11 cos

1||ω

==

Variation of Input Stage ModulationIndex due to Varying ī

Resulting Input Current Space Vector

11

121

*2

211ˆ

cos1)cos(cosˆ

ˆˆ|| It

tUUImii =Φ==

ωω

28

Resulting Input Phase Currents

)cos(ˆ

)cos(ˆ)cos(ˆ

32

11

32

11

11

π

π

ω

ω

ω

+=

−=

=

tIi

tIi

tIi

c

b

a

Space Vector Modulation SummaryPhase of resulting input vector is adjustableOutput voltage vector u2* is adjustable PWM pattern is specific for each combination of input and output stage sectors

Rectifier (input) stage Inverter (output) stage

29

=⋅ t1ω

Conventional vs. Low Output Voltage ModulationConventional Modulation Low Output Voltage Modulation

11I,max,2 U86.0U23U ⋅≈= 11II,max,2 U5.0U

21U ⋅==

Rectifier space vectorrepresentation

(HV) (LV)

[5]

30

Conventional vs. Low Output Voltage ModulationHV LV

One input phase (a) is clamped toone DC link bus (p)Other input phases (b, c) are switchedto the remaining DC link bus (n)

No input phase is clamped to the DC link busOne input phase (b) is switchedbetween the positive (p) and thenegative (n) busCurrent blocks of both polaritiesappear in one input phase (b)

31

HV LV

Parameters:f1 = 50 Hzf2 = 100 HzfP = 20 kHzL = 1 mHC = 9 μF

Output VoltageGeneration

Conventional vs. Low Output Voltage Modulation

Input CurrentGeneration

32

HV

LV HVLV

Reduction of switching lossesof approximately 58%


Switching Losses Output Common Mode Voltage

Output common mode voltage is reduced to approximately 75%

33


LV

HV

Switching Losses Output Current Ripple

LVHV

Current StressesInput voltage ripple doubles

Output current ripple slightly reduced

For given Û2 (M12) the componentcurrent stress increases (conductionlosses)

LV

HV

34

=⋅ t1ω

Conventional Modulation (HV) Low Output Voltage Modulation (LV)

3-Level Modulation Scheme

3 Output Voltage Level Modulation (3LV)Weighted combination of HV and LV modulationLowers output current rippleReduction of the output common voltage

35

3-Level Modulation Schemeuacuab

ubc

u

0

0 +π/6-π/6 +π/3ϕ1= -π/3

uacuab

ubcu

0uacuab

ubcu

0

(a)

(b)

(c)

Conventional / High Output Voltage Modulation (HV)

Low Output Voltage Modulation (LV)

3 Output Voltage Level Modulation (3LV)

2 13ˆ ˆ0

2U U= ⋅…

2 11ˆ ˆ02

U U= ⋅…

2 11 3ˆ ˆ2 2

U U= ⋅…

36

Advanced Modulation Schemes

37

a

b

c

A

B

C

Sparse Matrix Converter (SMC)

As the operation is restricted to upn > 0, blocking of Sna within the turn-on interval ofSap is not required and both transistors are combined into a single transistor Sa

Derivation of the SMC Bridge Leg Configuration

Standard IMC Topology with 18 Switches

38

Sparse Matrix Converter(SMC)Bidirectional

Ultra Sparse MatrixConverter (USMC)Unidirectional

Sparse Matrix Converter Topologies

),( 661ππ +−∈Φ

),( 662ππ +−∈Φ

39

Four-Quadrant SwitchIXYS FIO 50-12BD

Sparse Matrix Converter TopologiesVery Sparse Matrix Converter(VSMC)Bidirectional

a

b

c

A

B

C

Three-Level Output SparseMatrix ConverterBidirectional

40

Realization Effort of Matrix ConvertersNumber of Transistors, Diodes and Isolated Driver Potentials

Converter Type Transistors Diodes Isolated Driver

Potentials CMC 18 18 6 IMC 18 18 8 SMC 15 18 7 VSMC 12 30 10 USMC 9 18 7

41

Indirect Matrix Converter Topology Overview

Ultra Sparse Matrix Converter (USMC)

Very Sparse Matrix Converter (VSMC)

Sparse Matrix Converter (SMC)

Indirect Matrix Converter (IMC)

RB-IGBT Indirect Matrix Converter

42

Dimensioning Procedure

43

Operating Point 1Nominal load torque: mM = mM,N,Speed near zero: nM ≈ 0Output phase displacement: Φ2 ≈ 0°

Operating Point 2Nominal load torque: mM = mM,N, Nominal speed: nM ≈ nM,0

Output phase displacement: Φ2 < 10°

Example of a steady state torque-speed characteristic of a PMSM

DimensioningBasic Considerations for Drive Application

44

DimensioningLoss Distribution

Input StageConduction lossesDue to zero DC link currentcommutation, switching losses are negligible

Output StageConduction lossesSwitching losses

Positions of ū2 and i2 determinewhich semiconductors are subject to power losses

45

■ Conduction and switching loss measurement on high performance test setup

■ Determination of a set of parameters by a given interpolation approach(polynomial parameters)

Ki ,i=1…5

■ 2 “Universal” analytic expressions for semiconductor dimensioning at Operating point 1 (local maxima): pDev,max = f (fp ,Û1 ,Î2 ,Ki )Operating point 2 (global average): PDev = f (fp ,Û1 ,Î2 ,Ki )

■ Limitation of the output current and overall converter efficiencyÎ2,max,OP1 = f (pDev,max ,Rth ,Tj-TH ), Î2,max,OP2 = f (PDev ,Rth ,Tj-TH )

η,OP1 = f (pDev,max ,Î2,max,OP1), η,OP2 = f (PDev ,Î2,max,OP2)

DimensioningProcedure for Loss Calculation

[2, 3, 4, 5]

46

ac ac bc bc bc acacacbcbcac

Zero DC link current commutation

Switching Loss MeasurementsFour Commutation CasesΔu > 0 and Δu < 0

iLoad > 0 and iLoad < 0

Measurement setup for an IMC, using RB-IGBTs in the input stage

47

0 2 4 6 8 10 120

0.2

0.4

0.6

0.8

1

1.2

1.4

Current [A]

V -100VV -200VV -300V

Example of fitted curves, Eoff,Δu<0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.50

5

10

15

i Sap

[A]

t [ s]

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5-100

0

100

200

t [ s]

u Sap [V

]

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5-500

0

500

1000

1500

t [ s]

p Sap [W

]

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5-0.5

0

0.5

1

t [ s]

Eof

f,Sap

[mJ]

Switching Loss MeasurementsMeasurement Data Processing

Use of switching loss polynomial

Coefficients are derived by least squareapproximation of the measured dataCoefficients are used for analyticalloss calculation

( ) 2 2 2 2 21 2 2 2 3 4 2 5 2,Sw u i K u i K u i K u K u i K u i= ⋅ ⋅ + ⋅ ⋅ + ⋅ + ⋅ ⋅ + ⋅ ⋅

48

( ) 22

25Son2

24Son

23Son

222Son21SonSon iuKiuKuKiuKiuKi,uw ⋅⋅+⋅⋅+⋅+⋅⋅+⋅⋅=

IGBT- Switching Loss Parameter Tj K1 K2 K3 K4 K5

Soff 129 -947 10-3 471 10-3 -84.1 10-3 2.52 10-3 Son 41.6 1.75 308 10-3 60.7 10-3 -923 10-6 25°C Doff 66.6 -2.54 332 10-3 95.4 10-3 2.90 10-3 Soff 179 -1.31 650 10-3 -116 10-3 3.48 10-3 Son 70.0 2.94 518 10-3 102 10-3 -1.55 10-3 120°CDoff 97.9 -3.73 488 10-3 140 10-3 4.27 10-3

Units nWs(VA)-1 nWs(VA2)-1 nWs(V2)-1 nWs(V2A)-1 nWs(V2A2)-1

Switching Loss MeasurementsExample of Measurement Data Output

Used for analyticalcalculation

49

IGBT- On-State Parameter Tj UF r

S 940 52.4 25°C D 1250 8.04 S 768 78.7 120°CD 732 38.0

Units mV mVA-1

( ) ( ) InvS

i

BInvFS

i

BCSpB riUip

rmsSpBSpB

,2

)010()110(,)010()110(,2

,

⋅⋅++⋅⋅+= δδδδ

( ) ( ) ( ) ( )[ ]BacOnSBabOffSBabOnSBacOffSP

SwSpB

iuwiuwiuwiuwf

p

,,,, ,,,,

,

+++⋅=

=

CSpBSwSpBSpB ppp ,, +=

∫P

PT

T dt12

, )( DevDevFDevDevFDevDevCDev iriUiirUiup ⋅+⋅=⋅⋅+=⋅=2

,, rmsDevDevFCDev iriUp ⋅+⋅=

abac ),110(),110()110( δδδ +=

Conduction Losses – Model, Parameters

Transistor Currents in Half Pulse Period of Sector II

abac ),010(),010()010( δδδ +=

Conduction Losses (in general)

Local Conduction Losses in Sector II (exemplary of SpB)

Local Switching Losses in Sector II (exemplary of SpB)

Local Total Losses in Sector II (exemplary of SpB)

u corresponds to switchedvoltage of output stage devices

Analytical Loss Calculation

[2, 3, 4, 5]

50

Operating Point 1 (Local Loss Maximum)

Equation

Transistor Transistor

Diode Diode

( )2,2max 332163 ÎrUÎMp DevDevFDev,C, ⋅+⋅⋅=

Equation

0≈→ MM

Total Inverter Stage (PInv,C):)(6 ,.,., CInvDCInvSCInv PPP +⋅=

Operating Point 2 (Global Loss Average)

01 ≈⇒ MOP

0max, =C,S,Invp

34

34

≈⎟⎠

⎞⎜⎝

⎛ −→ MM

12 2 =⇒ MOP

122 =→ MM

122 −=−→ MM

( )2,2max 33241 ÎrUÎp DevDevFDev,C, ⋅+⋅⋅=

⎟⎟⎠

⎞Φ+⎜⎜⎝

⎛+

Φ+=

=

222

22

,2

,

ˆ24

cos31638

cos324ˆ IMrMUI

P

DevDevF

CDev

ππ

π

Conduction Losses (Example for Inverter)

51

Filter Design Procedure

Choice of standards

Compare

QPmeasurementLISNSimulation or

calculationRequired

attenuation

Design filtertopology andcomponents

Designedfilter

Identification of thelargest emission condition

Evaluation (emissionlimits, size, stresses, etc)

Max?yes

no

Limits for emission

Pass?yes

no

Currentspectrum

a

b

c

A

B

C

Frequency [Hz]10 100 1k 10k 100k

RMS

curr

ent [

A]

1

8765432

0

FFT

calc

ulat

ion

Elec

tric

circ

uit

sim

ulat

ion

Input current spectrum Input current VSMC

EMI Input Filter Design

[6]

52

Modeled Spectral Measurement (Chain 01)

Calc

ulat

ion

in fr

eque

ncy

dom

ain

Calculations in frequency and time domains

( ) ( ) ( )( ) ⎥

⎦

⎤⎢⎣

⎡ωω

⋅ω=ωj

jjj

dm

measdmmeas I

UIU

LLISN50 μH

idmRLISN50 Ω

CLISN250 n H

u meas

Converter’sinput current

Frequency [Hz]

Impe

danc

e [Ω

]

0

10

20

30

40

50

10k 100k 1M 10M

Vmeas(s)Idm(s)

Frequency [Hz]10 100 1k 10k 100k

RMS

curr

ent [

A]

1

8765432

0

LISNoutput

AttenuatorMixer

RBW filterGainDetectorVideo filter

Oscillator

Measurementresult

MB

uDuQPuF umeas

Measurement values

Input current spectrum

Spectral measurement modeled chain

LISN simplified high frequency model

Frequency [MHz]

DM

con

duct

ed e

mis

sion

[dB

uV]

0.1 10

20

4060

80100

120140

160180

Measurement results - ( uF )

LISN output voltage spectrum - ( umeas )

Class A limitClass B limit


53

Calc

ulat

ion

in fr

eque

ncy

dom

ain

Calculations in time domain

LISN output voltage spectrum

Filt

er a

ttenu

atio

n [d

B] -2

-4

0

-8-6

-10-12-14

-18-16

-20

2

Frequency [kHz]

MB

+ 10

MB −

4

MB

+ 4

MB −

10

MB −

2

MB

+ 2

MB −

1

MB

+ 1

MB

Modeled filter

CISPR 16 specifiedfilter envelope

f

Aver

agin

g of

th

e Q

P ou

tput

vo

ltage

RBW filter Effect of the RBW filtering

Averaged values Effect of the QP detector Quasi-Peak detector

Frequency [Hz]10k 100k 1M

RMS

volta

ge [V

]

100

10-1

10-2

10-3

10-4

10-5

10-6

10-7

102

101

Ufilt(jω)

Umeas( jω)

RQP1DQP

RQP2CQPuD uQP

Volta

ge [V

]

6040200

-20-40-60-80

10080

-100

uQP(t)

Time [ms]0 20 40 60 80 100 120 140 160 180

uD(t)

Frequency [MHz]

DM

con

duct

ed e

mis

sion

[dB

uV]

0.1 10

20

40

60

80100

120

140

160180


Frequency [MHz]

DM

con

duct

ed e

mis

sion

[dB

uV]

0.1 10

20

40

60

80

100

120

140

160

180


Modeled Spectral Measurement (Chain 02)


54

Frequency [Hz]100 1k 1M

Gai

n [d

B]

0-20-40-60-80

-100-120-140

4020

10k 100k

Imains(jω)Idm(jω)

C1C2

L1

R1

L3

R2

L2

conv

erte

r

mai

ns

VSMC input current Designed three-phase filter Input filtered current

Measurement without filter Experimental result(DM conducted emission)

Final measurement

Frequency [MHz]

Con

duct

ed e

mis

sion

[dBμ

V]

0.1 1

60

40

20

0

-20

-40

100

80 Class A limit

Class B limit

Frequency [MHz]

DM

con

duct

ed e

mis

sion

[dB

uV]

0.1 10

20

40

60

80100

120140

160

180


dBµVdBµV

TDF

RBW 9 kHz

MT 200 ms

PREAMP OFF

VIEW1 QP

150 kHz 10 MHz

PRN

1 MHz 10 MHz

EN55022Q

70

80

75

50

55

45

40

35

30

25

20

60

65

Three-phase Filter (Topology and Function) and Final Result


55

R31

CM,outu

aDMu ,

bDMu ,

cDMu ,

DMu ,

DMu ,

DMu ,R

R

R

Common modemeasurement

Differential modemeasurements

Noise source( LISN / AMN )

out,a

out,b

out,c

CMu

aL

bL

cLcTr

bTr

aTr

R = 50 Ω

Basic Noise Separator Schematic

Dimensions: 12.0 x 9.5 x 5.7 cm (4.75 x 3.75 x 2.25 in.)

CM inductorTransformer

Three-phase CM / DM Noise Separator


Function

Enables separate measurement of DMand CM noise in order to properly evaluatethe performance of the designed filters

[7]

56

Hardware Prototypes

Experimental Results

57

IXYS IGBT moduleFIO 50-12BD1200 V, 50 A

IXYS IGBTFII 50-12E1200 V, 50 A

Bidirectional power flow

Very Sparse Matrix ConverterTopology and Power Semiconductors

58

EMC Input Filter20%

Power PCB/Control 20%

CommercialHeat Sink

Cooling60%

Power density 2.8 kW/dm3

46 W/in3

Efficiency 94.5%

Input RMS voltage 230 VOutput power 6.8 kVARectifier switching frequency 12.5 kHzInverter switching frequency 25 kHz

Magneto resistive output currentsensors from Sensitec

Very Sparse Matrix ConverterHardware Construction

59

EM

I Filt

er

IXYS RB-IGBTIXRH40N1201200 V, 40 A

IXYS bridge-legFII50-12E1200 V, 50 A

Bidirectional power flow

RB-IGBT Indirect Matrix ConverterTopology and Power Semiconductors

[8]

60

Input filter

Heatsink

Fans

Output connectors

Control boards

2.9 kW/dm3=~

Input RMS voltage 230 VOutput power 6.8 kVARectifier switching frequency 12.5 kHzInverter switching frequency 25 kHz

2.9 kW/dm3

48 W/in3

Efficiency: 95.5%

RB-IGBT Indirect Matrix ConverterHardware Construction

61

Operating point: U1 = 230 V, Pout = 1.5 kW, fout = 120 Hz

Measured efficiency: η ≈ 95 %

DC linkvoltage100 V/div

DC linkvoltage100 V/div

Inputcurrent5 A/div

Outputcurrent5 A/div

Measurement Results


62

52 WIGBT / Diode

switching losses

53 WIGBT / Diodeconduction

losses

55 WRB-IGBT

conduction losses

43 WRB-IGBTswitching

lossesAux. power losses

30 W

27 W

Input filter losses

Inverter stagelosses105 W

Rectifier stage losses98 W

Calculated losses distribution at the maximum output power of 6.8 kVA, U1 = 230 V, M = Mmax, and Φ2 = 0°; shown for Tj = 25°C

Overall Losses


63

A

B

C

a

b

c

IXYS bridge-legFII 50-12E1200 V, 50 A

IXYS IGBT moduleFIO 50-12BD1200 V, 50 A

IXYS diodeDSEP 60-12AR1200 V, 60 A

Unidirectional power flow

Ultra Sparse Matrix ConverterTopology and Power Semiconductors

64

Ultra Sparse Matrix ConverterSpecial Features – Clamp Circuit

Auxiliary power supply connected to DC link

Clamping circuit with resistor combination to dissipate the energy of a loadmachine in braking mode

2 6 6

2 6 6

( , )( , )

π π

π π

Φ ∈ − +

Φ ∉ − +

Output displacement angle:

iDC < 0 → Clamp activation

iDC > 0

iDC

65

Input RMS voltage 230 VOutput power 5.5 kVARectifier switching frequency 25 (37.5) kHzInverter switching frequency 50 (75) kHz

Si USMC

Si / SiC USMCSiC free-wheeling diodesin inverter stage

Gate drives

Input filterCeramic input capacitors

Auxiliary powersupply

RB-IGBT Indirect Matrix ConverterHardware Construction

66

Measurement Results Showing Clamp Operation

Ultra Sparse Matrix Converter

Motor speed500 rpm/div

Voltage acrossthe clamp switch200 V/div

Zoomed voltage acrossthe clamp switch400 V/div

67

1.5 kVA

Overview of Hardware Prototypes

Si RB-IGBT IMC Si IGBT USMCSi IGBT VSMC

Si IGBT USMC withSiC output stage diodes

Si MOSFET SiC JFETCascode SMC

6.8 kVA 5.5 kVA

5.5 kVA

6.8 kVA

68

Comparison of Back-to-BackVoltage DC-Link Converter and

Indirect Matrix Converter

69

■ Comparison of the Realization EffortAssumptions, design and losses

■ Losses and Efficiency dependent on Operating PointTheoretical limits

■ Power DensityPhysical layout, dimensions and power density

■ EMI Filtering EffortDesign procedure, components, structure and volume

Criteria for Comparison

70

SpecificationsInput (3~AC) 400 V, +10%, -15%, 50 Hz

Output (3~AC) S2 = 6.8 kVA at Tamb = 45°C

Switching frequency SMC: Input fp = 20 kHz / Output fp = 40 kHzBBC: Input fp = 40 kHz / Output fp = 40 kHz

Dynamic Modulation Margin ΔMmin = 5%

Load PM Synchronous Motor (PMSM)

Comparison of Realization Effort

Back-To-Back ConverterVery Sparse Matrix Converter

71

Assumption for comparison:

Ideally designed motors for each of the topologies

32, min 1,min2 (1 ) 280NU M U V= −Δ ⋅ =

22,

2,14

3N

NN

PI A

U= =

⋅

min 1,max(1 ) 2 655dcU M U V= + Δ ⋅ ⋅ ≈

12, min 1,max2

(1 ) 440N dcU M U U V= −Δ ⋅ = =

2, 8.9NI A=

1

2

1

2

2

: Input RMS voltage: Output RMS voltage: DC-link voltage

: Input RMS current: Output RMS current: Output power

dc

UUUIIP


VSMC

BBC

72

Choice of DC-link Capacitor for the BBC

Capacitor is selected such that the voltage does not fall below a defined minimum value during the transient from full regeneration to full motor operation

( ) ( )

( ) ( )( )2 22

2,min 2 22 2 min( )

in dc dc dc dcDC link

dc dc dc dc dc dc

L P E U E UC

E U u E U E−

⎡ ⎤⋅ − − +⎣ ⎦=

⋅ + − +

,min 31DC linkC Fμ− ≅

Inductors are chosen such that the current ripple at the switching frequency is lower than 20% of the input current amplitude (minimum EMI filter volume)

1,min

1,

/ 32 6in

P ripple

ULf i

=⋅ ⋅ ⋅

,min 1inL mH≅

1

1,

: Peak input voltage: DC-link voltage

: Boost inductor: Input RMS voltage

: Input current ripple, peak-to-peak

dc

dc

in

ripple

EULUi


Choice of Boost Inductors for the BBC

[1]

73

Thermal Simulation and Main Components

IXYS FIO 50-12BDIXYS FIO 50-12E

IXYS FII 50-12E

Not used8 μF, foil, 400 VACDC-Link Capacitors

Not used1 mH (toroidal)Boost Inductors

IXYS FIO 50-12ESemiconductorsOutput

IXYS FIO 50-12BDIXYS FII 50-12E SemiconductorsInput

Very Sparse Matrix

BBCDescription

3

3

3

4

3

6

Tamb = 45 °C

Tj,max = 150 °C

Rth,diodes = 1.3 °C/W

Rth,IGBTs = 0.6 °C/W


BBC requires largerheat sink due tolower efficiency

74

Losses and Thermal Limits – Comparison at Nominal Conditions

0

10

20

30

40

50

60

Rectifier Inverter Input OutputBBC VSMC

(SC)

(SS)

(DS)

(DC)

(SC)

Pow

er L

osse

s (W

)

Diode Switching (DS)Diode Conduction (DC)IGBT Switching (SS)IGBT Conduction (SC)

115

120

125

130

135

140

145

150

155

Rectifier Inverter Input OutputBBC

Junc

tion

Tem

pera

ture

(°C

)

VSMC

IGBT TjmaxDiode Tjmax

The

rmal

grea

se

123

Dio

deIG

BT

Dio

deIG

BT

Dio

deIG

BT

Hea

tsi

nk

122

The

rmal

grea

se

135

Dio

deIG

BT


Losses Distribution Junction Temperature

VSMC: No switching losses in input stage

BBC: Switching losses in both stages

Limiting device VSMC: Output IGBT

Limiting device BBC: Rectifier diode

75

Losses and Efficiency dependent on Operating Point

),(),(1

22

2ImS

ImPLoss−=η

mIUImS ⋅⋅= 2123

22 ),(

Efficiency Max. Output Current for f2 = 0(Standstill: Most Critical OP)

Max. Efficiency at Max. Modulation IndexVSMC: 94.5%BBC: 92.0%

Max. Output Current AmplitudeVSMC: 1.25 Î2,N (due to special modulation)

BBC: 0.46 Î2,N

76

Under rated load condition the critical fp is about 14 kHz→ VSMC is advantageous in efficiency within whole speed-torque plane beyond 14 kHz

NBBCLossVSMCLossLoss PPPP 2,, /)( −=Δ

Advantageous Applicationsfor VSMC (IMC)

Relative Loss Difference – Dependence on Load and Switching Frequency

Losses and Efficiency dependent on Operating Point

Relative Loss Difference

Applications requiring an output filterDrives operated at partial loadAircraft applications (400 – 800 Hz)Low inductance machines

77

Compare

Des

igne

d fil

ter

Pass?yes

no

QP measurementapproximation

Limits (standards)

LISN HF equivalentcircuit

50μH50Ω

250nF

Vh (f)idm (f)

Input currentspectrum

idm (f)

Requ

ired

atte

nuat

ion

QP measurements expected maximum resultsInput current spectrum without filter

QPmax ( f )

Design of the filtertopology andcomponents Size

Attenuation

Costs

Evaluation

100

2

4

6

8

10

RMS

curr

ent [

A]

Frequency [Hz] 106

VSMCiDM ( f )

-40-20

020406080

100

Con

duct

ed e

mis

sion

[dbμ

V]

105 106Frequency [Hz]

VSMC

Vh ( f )

QPmax ( f )

-40-20

020406080

100

Con

duct

ed e

mis

sion

[dbμ

V]

105 106Frequency [Hz]

BBC

Vh ( f )

100

2

4

6

8

10

Frequency [Hz]

RMS

curr

ent [

A]

106

iDM ( f )

Stresses

Modeling

QPmax ( f )

BBC

EMI Filtering Effort

78

Comparison

C1C2

L1

R2d

LCM,1

Con

vert

er

Mai

ns

C2d

CCM,1CCM,2

R1d

L1dLCM,2

Y2 250V4.7nF

Y2 250V4.7nFX2 250V

330nF

27Ω 1W

X2 250V150nF

3.4Ω 2W

X2 250V4700nF

VAC 500F W4093 x 4 turns

VAC 500F W3803 x 7 turns

Micrometals T130-2639 turns

Micrometals T130-2639 turns

Filter Structure for the BBC

VSMCBack-to-back

Total filter components volume

Total CM inductance (10 kHz)

Total CM capacitance

Total DM inductance (10 kHz)

Total DM capacitance (for all three-phases) 15.54 mF

1.20 mH

28.2 nF 28.2 nF

360 cm3325 cm 3

36 mH

36 mF

1.29 mH

36 mH

EMI Filtering Effort

Filter volume forthe VSMC is 10%larger

79

0 5ms 10ms 15ms 20ms

0 5ms 10ms 15ms 20ms 0 5ms 10ms 15ms 20ms

0 5ms 10ms 15ms 20ms(a)

(d)(c)

(b)

iA

uA

uA

iA

uA

uAua

ia

ia

ia

ua

VSMC

BBC

Nominal Operation (6.8 kW)

150 V/div15 A/div

150 V/div15 A/div

Characteristic Waveforms

Constant DC link voltage at higher level (boost capability)Lower output currents due to higher output voltage level

BBC Features:

80

Power density:≈ 2.8 kVA/liter≈ 46 W/in3

Volume: 2.4 liters

Power DensityBBCVSMC

Dimensions:L 26.2 cmW 8.0 cmH 11.5 cm

Power density:≈ 1.5 kVA/liter≈ 25 W/in3

Volume: 4.6 liters

Dimensions:L 22.7 cmW 16.0 cmH 13.4 cm

[9]

81

ConclusionsCMC and IMC / SMC proven to be competitive to BBC / Voltage DC Link System

Typically 1-2% higher dependent on operating point for samesemiconductor effort (especially, lower switching losses at high switching frequencies)

Typically 20% lower for forced air cooling

Comparable complexity of modulation and control, USMC clearly advantageous for unidirectional power flow

Lower output voltage range, therefore mainly suited to applications requiring a non-standard motor anyway

+ Efficiency:

+ Volume:

0 Modulation:

- Output Voltage:

82

Comparative evaluation of MC concepts and BBC forequal / optimally utilized semiconductor effort

EMI performance (common mode filtering)

Applicability for highly dynamic drives

Sensorless control down to zero frequency

Modulation for low pulse number / high power applications

Future Research

83

ReferencesCarlson, A.: „The back-to-back converter“, Master Thesis, Lund Institute of TechnologyLund, Sweden, (1998).

Kolar, J.W., Baumann, M., Schafmeister, F., and Ertl, H.: Novel Three-Phase AC-DC-AC Sparse Matrix Converter. Part I - Derivation, Basic Principle of Operation, Space Vector Modulation, Dimensioning.Proceedings of the 17th Annual IEEE Applied Power Electronics Conference and Exposition, Dallas (Texas), USA, March 10 - 14, Vol. 2, pp. 777 - 787 (2002).

Schafmeister, F., Baumann, M., and Kolar, J.W.: Analytically Closed Calculation of the Conduction and Switching Losses of Three-Phase AC-AC Sparse Matrix Converters. Proceedings of the 10th International Power Electronics and Motion Control Conference, Dubrovnik, Croatia, Sept. 9 - 11, CD-ROM, ISBN: 953-184-047-4 (2002).

Schafmeister, F., Herold, S., and Kolar, J.W.: Evaluation of 1200V-Si-IGBTs and 1300V-SiC-JFETs for Application in Three-Phase Very Sparse Matrix AC-AC Converter Systems. Proceedings of the 18th Annual IEEE Applied Power Electronics Conference and Exposition, Miami Beach (Florida), USA, February 9 - 13, Vol. 1, pp. 241 - 255 (2003).

Kolar, J.W., and Schafmeister, F.: Novel Modulation Schemes Minimizing the Switching Losses of Sparse Matrix Converters. Proceedings of the 29th Annual Conference of the IEEE Industry Electronics Society, Roanoke (VA), USA, Nov. 2 - 6, pp. 2085 - 2090 (2003).

[1]

[2]

[3]

[4]

[5]

84

ReferencesHeldwein, M.L. , Nussbaumer, T. , and Kolar, J.W.: Differential Mode EMC Input Filter Design for Three-Phase AC-DC-AC Sparse Matrix PWM Converters. Proceedings of the 35th IEEE Power Electronics Specialists Conference, Aachen, Germany, June 20 - 25, CD-ROM, ISBN: 07803-8400-8 (2004).

Heldwein, M.L. , Nussbaumer, T. , Beck, F., and Kolar, J.W.: Novel Three-Phase CM/DM Conducted Emissions Separator. Proceedings of the 20th Annual IEEE Applied Power Electronics Conference and Exposition, Austin (Texas), USA, March 6 - 10, Vol. 2, pp. 797 - 802 (2005).

Friedli, T., Heldwein, M.L., Giezendanner, F., and Kolar, J. W.: A High Efficiency Indirect Matrix Converter Utilizing RB-IGBTs. Proceedings of the 37th Power Electronics Specialists Conference, Jeju, Korea, June 18 -22, CD ROM, ISBN: 1-4244-9717-7, (2006).

Round, S., Schafmeister, F., Heldwein, M.L., Pereira, E., Serpa, L., and Kolar, J.W.: Comparison of Performance and Realization Effort of a Very Sparse Matrix Converter to a Voltage DC Link PWM Inverter with Active Front End. IEEJ Transactions of the Institute of Electrical Engineers of Japan, Volume 126-D, Number 5, May 2006, pp. 578 - 588.

[6]

[7]

[8]

[9]

85

Thank you very much for your attention !

indirect matrix converter...1 indirect matrix converter johann w. kolar thomas friedli eth zurich,...

Documents