industrial automation - technion · y3 fixed automation drum programmers pneumatic or hydraulic...
TRANSCRIPT
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Y3
Fixed Automation
Drum Programmers
Pneumatic or Hydraulic Cylinders
Xn
- Pumps
Heaters
Data Processing
MicroprocomputersProgrammable Controllers (PLC)
Output Signals
Relays
Microprocessors
Electric Motors
X1
X3
......
......
......
...
- Conveyor Belts
X4
Y1
Y4
- Robot Arms
Solenoid Valves
Moving-Part Logic (MPL)
Numerical Displays
Semi-Flexible Automation
Electronic Gates
X2
INDUSTRIAL AUTOMATION
X5
Ym
TYPICAL OUTPUT DEVICES
Programmable Counters
Timers
......
......
......
...
Y2
Lamps
Fixed Automation
S E Q U E N C E C O N T R O L
Pneumatic or Hydraulic Motors
L O G I C C I R C U I T
- Lifting Devices
Sensor Inputs
Audioble Signals (Bells, Buzzers, Sirens)
Pneumatic Valves
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�������INTRODUCTION
Analog/Digital Differences
Switches and Relays Pneumatic Switching Valves Cylinder Control and Sensing Other Switching Elements
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S?
SW DPDT
Fig. 0-2 Information Types
+ -
Value
Time
(open)
Time
Value
+
Element
Fig. 0-4 Binary (Switching) Elements
Flow Switches
2-Input OR Gate
Threshold Sensors
c. Binary (Logic, "Digital")
+ -
+ -
A+
Temperature Switches
S?
SW SPDT
a1
Ultrasonic Sensors
a. Logic Levels
"Unspecified"
Annular Back-Pressure Sensors
A+
Fig. 0-1 Subject Definition
+
2-Input NOR Gate
Pressure Switches
Value
Time
Out
d. Pneumatic Valves
b. Self Correction
INVERTER
K?
RELAY DPDT
a2
On-Off (Binary) Elements and Information
Signal
2-Input AND Gate
"High"
Fig. 0-3 Logic-Levels
Value Value
Various Methodes to Obtain Low-Cost Systems
Control Section
+ -
Time
IMPLEMENTATION
START
+ -
(open)
b. Electro-Mechanical Relays
Inductive Proximity Sensors
BINARY SENSORS :
a1,a2 = 00
Logic
a. Analog
Relay SPDT
g. Various Elements
Photoelectric Sensors
Level Switches (Height)
b. Digital
Value
Time
2-Input NAND Gate
Automation of Mechanical Industrial Production Systems
Magnetic Proximity Sensors
Inductive Proximity Sensors
a. Electrical Switches
f. Pneumatic Limit Valves
Time
Value
Interruptabel-Jet Sensors
"Low"
Back-Pressure Sensors
K?
RELAY SPST
LOGIC
In
A-
INDUSTRIAL AUTOMATION
e. Electrical Limit Switches
Time
3-Input NAND Gate
A-
0-1
c. Electronic Gates
Reed Switches
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CHAPTER 1
BOOLEAN ALGEBRA
Binary Basic Basic Boolean Operations Truth Table De-Morgan Functions Algebric Minimization Karnaugh Map Minimization
���������������� ����������������� ���������
"ON" / "OFF"
X(Y+Z) = XY+XZ
IMPLICATION
1
F1 = XY+X'1+Y.1 =
If Z=1 then :
b. Basic Operators
Y
f(A,B,C,D) = (A+B+C+D)(A+B+C+D')(A+B'+C'+D)(A'+B+C+D).
X nand Y = (X.Y)'
1 1 1
Contacts : Open / Closed
1.1 = 1
A+B = (A'.B')'
NAND (NOT AND) :
1 1
.(A'+B+C+D')(A'+B'+C+D)(A'+B'+C+D')
1. Universal Sum-of-Products :
f(A,B,C,D) = A'BC'+AC+B'C+CD
1. Universal Sum-of-Products :
1+1 = 1 {*}
0 1 1 1
(X+Y).(X+Z) = X+YZ
A' = (A+A)' = (A NOR A)
f'(A,B,C,D) = A'B'C'D' + A'B'C'D + A'BCD' + AB'C'D' +
= (A NAND A) NAND (B NAND B)
C
0.1 = 0 1' = 0
f(A,B,C,D) = A'B'CD'+A'B'CD+A'BC'D'+A'BC'D+A'BCD+
D
0
(A+B)' = A'.B'
= (A NOR A) NOR (B NOR B)
0 1 0
X+1 = 1
f. More Useful Operators
1
0' = 1
1
X.Y'
(A.B+A'.C)' = (A'+B').(A+C')
0
4. Minimal Products of Sum :
1
X.1 = X
George Boole
If Z=0 then :
1 1 1 1
INHIBITION
"0 / "1"
c. Basic Relations
1 1
AND , NOT
F2 = XY+X'Z
1 1 0 0
3. Minimal Sum-of-Products :
Logic , Boolean , Binary , Digital
Net : Connected / Not-connected
1 0 0 01 0 0 1
i. Functions Basic Representations
Binary sensors (Temperature, Pressure, etc)
NOR (NOT OR) :
e. Minimization - Math Operations
F1
F1 = XY+X'Z+YZ
0 1 0 0
0 0 1
0
X+Y'
3. Minimal Sum-of-Products :
F2 = XY+X'.1 =
1 0 1 0
X+X = X
XY+X'Z+YZ = XY+X'Z
0 0
0 0 1 1
0
0+0 = 0 AND , OR , NOT
(AB(C'+DE'))' = A'+B'+C(D'+E)
1 1 1 0
0 1 1
BOOLEAN ALGEBRA
1 1
1
Representations : (A.B)' = A'+B'
Logic Theory Implementation in Switching
F1 = XY+X'.0+Y.0 = XY F2 = XY+X'.0 = XY
A.B = (A'+B')'
1.0 = 0
d. Minimization - Truth Table
Implementations :
X+X.Y = X
1 1
4. Minimal Products of Sum :
X nor Y = (X+Y)'
NOR
A' = (A.A)' = (A NAND A)
AND OR NOT
0 1 1 0
10 0
+ AB'C'D + ABC'D' + ABC'D
A+B = (A'.B')' = ((A.A)'.(B.B)')' =
1+0 = 1
Z0 1 0 1
0 0 0
= XY+X'+Y = X'+Y
A
0
0
X+0 = X
XY+X'Z+YZ = XY+X'Z
NAND
"HIGH" / "LOW"
X+X' = 1
F2
X xor Y = X'Y+XY'
0 0
f(A,B,C,D) = (A'+C)(B+C)(A+B'+C'+D)
X.0 = 0
1 0 1
F
OR , NOT
X.X' = 0
F1 = XY+X'Z+YZ
Switch or Relay ON/OFF Position :
XY+X'Z+YZ = XY+X'Z
= X'+XY = X'+Y
X.X = X
1
0
1
1-1
X
X+X'.Y = X+Y
XOR (Exlussive OR)
0 0 0 00 0 0 1
B
1 1 0 1
2. Universal Products of Sum :
1 0 0
+ AB'CD'+AB'CD+ABCD'+ABCD
1 1 0
g. DeMorgan Theorem
2. Universal Products of Sum :
F2 = XY+X'Z
False and True replaced by 0 and 1
0.0 = 0
a. Basic Definitions
1
Binary Items and Variables
0 0 1 0
A.B = (A'+B')' = ((A+A)'+(B+B)')' =
Fig. 1-1 : Boolean Algebra Concepts
0+1 = 1
0 0
h. Universal Systems
1 0 1 1
���������������� ����������������� ���������
B
* Any two adjacent elements are represented
AB'C
1 1 1
HAS LICENSE
SIMPLIFIED RESULT :
0 1 1 1
1 1 0 0
A
B
C
D
CRETERIA
e. Truth Table Minimzation
A COMBINATIONAL SYSTEM DETECETS IF THE NUMBER IS DIVIDABLE
NON-ISRAELI MAIL 50 OR ABOVE
Fig. 1-3 : Algebric Minimization (2)
ISRAELI 1 1 1 1
1 1 1 0
0 1 0 0
1 0 1
0 0 0 1
* Visual method for boolean functions
c. Truth-Table
UNDER 50
1
= A+B'C'+B.C'+BC = A + B'C' + B(C'+C) =
A'B'C'
00 01 11 10
00
01
11
10
AB
CD0
ISRAELI
1
0 1 0
0
a 2-elements cell, represented by a product of
0
ISRAELI
1 0 1 0
=X0'(X2'X1'+X2'X1+X2X1'+X2X1)+X2'X1X0=
T
C
A
B
=X0'+X2'X1
0 1 1 0
minimization
= A+B'C'D'+B'C'D+BC'D'+BC'D+BCD'+BCD' =
T
B'
A'BC
=X0'+X2'X1X0=
MALE
= A + B'C' + B
1
A
1
B
Into a 4-elements cell, represented by a
B
AN OCTAL NUMBER IS DEFINED BY THE BINARY COMBINATION X2,X1,X0
50 OR ABOVE
A B C D
0 0 1 0
Fig. 1-2 : Algebric Minimization (1)
WHERE N(X2,X1,X0)=4.X2+2.X1+1.X0
FIND THE MINIMAL REQUIRED CONDITIONS
d. Minimization Steps
* Merging two adjacent elements produces
f. Minimal Requirements
A
1-2
=X0'(X2'+X2)+X2'X1X0=
= A+B'C'(D'+D)+BC'(D'+D)+BC(D'+D)'
1
X1
B
c. 3-Variables Map Representations
and/or
product of n-2 variables, and so on
= A+A'(B'C'D'+B'C'D+BC'D'+BC'D+BCD'+BCD)' =
UNDER 50
00 01 11 10
0
1
A
BC
CLIENT MUST SATISFY AT LEAST ONE OF THE FOLLOWING CONDITIONS :
X1
and/or
1
T = X2'X1'X0'+X2'X1.X0'+X2'X1.X0 +
AN INSURANCE COMPANY SELECTS CLIENTS ACCORDING TO THE FOLLOWING
b. Boolean Variables Assignment
and/or
* n variables split map into 2^n basic cells,
0 0 1
1 0 0 0
T = A+A'B'C'D'+A'B'C'D+A'BC'D'+A'BC'D+A'BCD'+A'BCD
INSURANCE COMPANY REQUIREMENTS
0
0 0 0 0
VARIABLE
and/or
0
A
1
1
C
by two "Adjacent" minterms
X2 X1 X0 T
BY EITHER 2 OR 3
1
* Each element is represented by a n-variable
b. Block Diagram0 1 1
1 1 0
1
A'BC'
NON-ISRAELI UNDER 50 WITHOUT DRIVING LICENSE
A
* Each variable occupies half map
=X0'(X2'(X1'+X1)+X2(X1'+X1))+X2'X1X0=
X1
1 0 0 1 1
d. Truth Table
0 0 1 1
(n-1) variables
NON-ISRAELI
1 1 0 1
1
1
1
a. Map Concepts and Basic Properties
0
0
+ X2.X1'X0'+X2.X1.X0'=
ABC
GENDER
MALE
COMBINATIONAL CIRCUIT
LICENSE
* Two adjacent 2-element cells may be merged
0
= A+C'D+BC+C'D'= A+C'(D'+D)+BC= A+C'+CB= A+B+C'
AGE
1 0 1 1
a. System Definition
1
named map Elements
B
FEMAIL
Fig. 1-4 : Karnaugh Maps Concept
1
boolean product, named "Minterm"
0 0 0
and/or
1
b. 2-Variables Map Representations
ABC'
1
1
T = A+A'C'D+A'BC+A'C'D' = A+A'(C'D+BC+C'D')
0 1 0 1
NON-ISRAELI UNDER 50 WITH DRIVING LICENSE
Karnaugh Maps
A'B'C
1 0 0
1
A'
D DOESN'T HAVE LICENSE
AB'C'
a. System Definition
NATIONALITY
CRITERIA : NATIONALITY, GENDER, AGE AND HAVING DRIVING-LICENSE.
A
1
d. 4-Variables Map Representations
c. Direct Minimzation
= A + C' + B
1
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Hebrew
E
b. { B , C , D}
HebrewEnglish
7. Selecting all ESSENTIAL candidates, don't cover the left languages Arabic andRussian. So, we must look for the minimal additional candidates that will completedthe.This selection is simpler.
2. Since all ESSENTAIL candidates (if there are any) must be a part of anyselection option, we first identify them and select them.
4. Actually, some (or all) NON_ESSENTIAL will have to be selected in case thatthe ESSENTIAL candidates do support all required languages.
B
a. { A , B , D}
8. In this case, either A or C complete the required support, so the minimal selectedgroup contains 3 candidate (2 ESSENTAIL and 1 ON_ESSENTIAT).
1-3
Of course, the company target is to hire the minimal number of employees,and get the required support.
An international company has to hire employees that will be available, as agroup, to support the following 6 languages :
There are many available combibations, but we can make the selection easier :
Romanian
5 candidates look for that job. Next table specifies the languageknowledge of each candidate :
D
9. There is no other option to the support Arabic and Russian by a single candidate,so there two minimal available selections :
Russian
Candidate
Arabic
3. NON_ESSENTIAL candidates doesn't mean that they will not be selected.NON_ESSNTIAL. Since any of them may be replcaed by others, no one candecide - on first glance - which of them must be selected,or not.
5. We can see easily that French is suppoter by candidate D only, andRomanian is supported by candidate B only. This maked D and B ESSNTIAL.Each of all other languages is supported by al least 2 candidates, so all thosecandidates are NON_ESSENTIAL.TIAL.
Candidate
11. Thsi means that first minimal selction (a) is preferable, which leaves a singleminimal solution.
10. Principally, both selections are minimal. On the other hand candidate A hashigher priority than C since he support 4 labguages and may be ore helpful, and abackup to the other languages that had been covered by the ESSENTIAL candidates.
1. Check if there are ESSENTIAL candidates, that is to say candidate thatsupport at least a single language, that none of the others does. Thesecandidates are called ESSENTIAL, since are non-replacable by any of theother candidates.
Fig 11-5 : ESSENTIAL and NON_ESSENTIAL concept
Russian
Hebrew , English , Russian , Arabic , Rumanian , French
GROUPS SELECTION - ESSENTIAL AND NON-ESSENTIAL CANDIDATES
Candidate
FrenchEnglish
Candidate
Arabic
C
6. Selection of candidates B and D (ESSENTIAL) cover more than the 2mentionedlanguages; they also support Hebrew and English, so we don't have to worryabout support of thse 4 langages.
Russian
A
Hebrew
Candidate
Arabic
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1
1
1
1
1
1
1
1
1
1
1
11
II
Fig
. 1-8
: Exa
mp
le 3
1
1
Non
-Ess
entia
l cel
ls :
2
F =
AC
+ B
'C +
A'B
C' +
CD
1
F2 =
BC
+ B
'C'D
+ A
'C'D
II
Min
imal
sol
utio
ns :
2
1
F =
AD
+ C
'D +
A'C
D'
1
1
IV
1
11
1
1
1
V
11
1
1
1
11
11
1
1
1
1
I
1
Min
imal
Sol
utio
n 4
11
II
I
1
Fig
. 1-7
: E
xam
ple
2
1
A
B
C
D1
F3 =
A'C
' + A
C +
BC
'D +
AB
'D'
1
F2 =
BC
D' +
AB
D +
A'B
C'
A
B
C
D
1
1
1
A
B
C
D
1
1
Ess
entia
l cel
ls :
2
A
B
C
D
11
1
A
B
C
D
A
B
C
D
1
III
1
1
11
1
1
1
I
Ess
entia
l cel
ls :
3
1
1
1
1
1
Fig
. 1-1
1 : E
xam
ple
6
11
Min
imal
sol
utio
ns :
1
Non
-Ess
entia
l cel
ls :
6
IV
II
1
F4 =
A'C
' + A
C +
BC
'D +
B'C
'D'
1
1
II
11
A
B
C
D
Non
-Ess
entia
l cel
ls :
2
1
1
1
1
1
1
1
II
F =
A'C
'D +
AC
D +
A'B
C +
AB
C'
1
A
B
C
D
1
A
B
C
D
Min
imal
Sol
utio
n 1
1
1
Map
s D
efin
ition
s
1
1E
ssen
tial c
ells
: 0
1
1
1
1
1
1
1
II
1
1
Min
imal
Sol
utio
n 2
1
1
A
B
C
D
11
1F2
= A
'C' +
AC
+ A
BD
+ B
'C'D
'
1
1
I
1M
inim
al s
olut
ions
: 4
A
B
C
D
Func
tion
"Are
a"
1
1
1
1F1
= A
'C' +
AC
+ A
BD
+ A
B'D
'
1
Non
-Ess
entia
l cel
ls :
4
1
IV
1
1
1
1
IV
Ess
entia
l cel
ls :
3
1
A
B
C
D
11
1
1
1
1
III
Min
imal
sol
utio
ns :
1
I
1
1
11
III
A
B
C
D
Fig
. 1-9
: E
xam
ple
4
1
1
1
1
A
B
C
D
11
III
1
1
1
1A
B
C
D
A
B
C
D
1
1
F1 =
BC
+ B
'C'D
+ A
'BD
1N
on-E
ssen
tial c
ells
: 1
VA
B
C
D
1
1
1
1
1
Ess
entia
l cel
ls :
2
A
B
C
D
11
1
All
(Max
imal
) Cel
ls
1
1
F1 =
AB
C +
BC
'D +
A'B
D'
11
11
1
1
1
1
1
2
1
1
1
1
Fig
. 1-1
0 : E
xam
ple
5
1-4
Min
imal
sol
utio
ns :
11
1
Non
-Ess
entia
l cel
ls :
0
1
1
A
B
C
D
1
Fig
. 1-6
: E
xam
ple
1
VI
A
B
C
D
1
Min
imal
sol
utio
ns :
2
II
1
Ess
entia
l cel
ls :
4
1
1
1
A
B
C
D
A
B
C
D
1
III
���������������� ����������������� ���������
-
1
1
Sel
ecte
d D
on't
Car
es :
Par
tial
-
1 11
III - -
-
0
1
Min
imal
sol
utio
ns :
1
-
-
1
1 1
1
11
1
Non
-Ess
entia
l cel
ls :
8
0
1
1
A
B
C
D
Non
-Ess
entia
l cel
ls :
1 (+
2)
0
1-
F2 =
BD
+ A
C +
A'B
'+ C
'D'
III
-
-
1
1
1
-M
inim
al s
olut
ions
: 1
1
1
1
Ess
entia
l cel
ls :
0
Fig.
1-1
7 : E
xam
ple
10
1
-
1
1-
1
Ess
entia
l cel
ls :
0
1
A
B
C
D
II
-
1
1
1
-
1
Non
-Ess
entia
l cel
ls :
3 (+
5)
VI
1
1II
0
Non
-Ess
entia
l cel
ls :
12
-
1
11 -
1
1
Non
-Ess
entia
l cel
ls :
1
1
1
II
1
1
1
Ess
entia
l cel
ls :
2
-
1
-
-
Ess
entia
l cel
ls :
2
-
0
Sel
ecte
d D
on't
Car
es :
Non
e
11
1
Non
-Ess
entia
l cel
ls :
0
-
A
B
C
D
III
1
1
A
B
C
DII
1
01
-
1
1
-
1
Fig.
1-1
4 : E
xam
ple
8
-
1
1
1
1
1A
B
C
D
I
-1
11
0A
B
C
D
-
1
A
B
C
D
I
-
1
1
-1
IV
Min
imal
sol
utio
ns :
2
Fig.
1-1
3 : E
xam
ple
7.1
I
1 1
1
-
F' =
AB
'D +
A'B
D' +
BC
'DF
= A
D' +
A'B
' + B
CD
1
0
A
B
C
D
A
B
C
D
-1
1A
B
C
D
F1 =
A'C
' + B
'D'+
AB
+ C
D
IV
1
1M
inim
al S
olut
ion
2
-
-
-
1
1
All
(Max
imal
) Cel
lsII
A
B
C
D
Ess
entia
l cel
ls :
2
III
--
11
1
A
B
C
DF
= A
C' +
C'D
+ A
'CD
'
0
1
1
F =
(A +
B' +
C' +
D).(
A' +
B +
C +
D')
-
1
0
0
A
B
C
D
1
A
B
C
D
II
1
1
-
1
1
1
0
0
1
1
A
B
C
D
I
-
-
-
1
1
Sel
ecte
d D
on't
Car
es :
All
-
Func
tion
"Are
a"
V
F5 =
1
F2 =
AC
D +
AB
+ A
'D'
1
1
1
Map
s D
efin
ition
s
A
B
C
D
F' =
A'B
CD
' + A
B'C
'D
F4 =
A'D
+ B
'C +
AB
+ C
'D'
-
1
1
11
1
1
II
11
11
-
A
B
C
D
01
1
Min
imal
Sol
utio
n 1
Min
imal
sol
utio
ns :
6
Ess
entia
l cel
ls :
0
IV
-
1
1
1
1
I
1
Sel
ecte
d D
on't
Car
es :
Par
tial
11
A
B
C
D
A
B
C
D
11
0
-
-
1-51
1
1
1
1
A
B
C
D
A
B
C
D Min
imal
sol
utio
ns :
1
0
11
III
-
-1
1
F =
(A'+
B+D
').(A
+B'+
D).(
B'+
C+D
')
Ess
entia
l cel
ls :
1
II
Min
imal
sol
utio
ns :
1
Not
e : F
1 an
d F2
are
equ
ival
ent b
ut n
ot id
entic
al
-
0
1
A
B
C
D
1
-
-
1
1
Min
imal
Sol
utio
n 4
-
-
1
10
1
Fig.
1-1
8 : E
xam
ple
11
-
0
1
A
B
C
DIII
11
0
A
B
C
D
F3 =
AD
'+ B
C'+
CD
+ A
'B'
Fig.
1-1
5 : E
xam
ple
8.1
-
1 0
1
1
1
F6 =
11
1
-
1
1
-
-
1
Min
imal
sol
utio
ns :
1
III
1
1
I
-
1
A
B
C
D
-
1 1
I
V
-
1
1
Sel
ecte
d D
on't
Car
es :
Non
e
1
1 1
11
1
-
-
1
F1 =
AC
D +
AB
+ A
'C'
Fig.
1-1
6: E
xam
ple
9
I
-
1
III
-
-
-
1 1
F =
AD
+ A
'D'
-
1
0
1
0
Non
-Ess
entia
l cel
ls :
5
-
-
1
0
Fig.
1-1
2 : E
xam
ple
7
-
1 11
11
���������������� ����������������� ���������
00 01 11 10
0
1
X
Y,Z
1 1 1
A B C D
0 1 - 1
-
0 0 0
E
0 0 1Design a combinational circuit that gets a BCD input, and converts it to7-Segment display.
0 1 1 1
0
1 1 1 1
b. 7-Sigments Arrangement
Y
a. Truth-Table
1 1 - -
-
1
*
=D3+D2.D1'+D2'D1+D2.D0'
1 0 0 0 0 1 1
G
0 1 1
0 1 0 1
0
Z
0 1 1
D3 D2 D1 D0
b. Karnaugh-Maps
Fig. 1-21 : BCD to 7-Segments
C
D2
1
A=D3+D2.D1'+D2'D1+D1.D0'=
X
1 1 0
d. Truth-Table (Partial)
-
1
1 1 1 0-
1
1 0 1
Z
Binary combinations 1010-1111 (above decimal 9) may not appear asinputs, and are refered as don't-care.
*
X
D
1 1 0
Y
0 0 1
D0
1 0 0 0 1
F
Z
1 0 1
0
00 01 11 10
00
01
11
10
D1,D0
D3,D2
1 1 0
0 1 - 1
1
-
Fig. 1-20 : Motor Operation Control
1
1 0 0
00 01 11 10
0
1
X
Y,Z
1 0 0 1
B
0 0 1 0
-
A = X + Y + Z
1 1 - -
BCD to 7-SEGMENTS CONVERTER
1
0
C = XYZ
Fig. 1-19 : Majority Function
0 0 1 0
B
1 0 - 1
0 0 0 0
a. System Definition
B
Y
1
D3
-
X
X
1 1 1
(Exer 1-7)
B
C
1
X Y Z M
Y
E=D2'+D1'D0'+D1.D2
1 1 - 1
1 0 - -
M = XY+XZ+YZ
1 0 1 1
SWITCH
X Y Z A
0 1 1 1
A
0 0 1 0 1
1
D1
1 0 - -
f. Karnaugh Map of "A"
E F G
11 0 1 0
Z
1 0 0
1 0 - -
D
1 1 0
-
C
Z
SWITCH
0 0 0 1
Z
Y
X
1 1 0 0
1
X
0
Y
1 1 0
-
Y
0
0 1 1 1
0 0 1 0
Z
c. Contact Circit Realization
SWITCH
1
00 01 11 10
0
1
X
Y,Z
G
c. Block Diagram
C
1
1
0 1 1 1
1-6
00 01 11 10
0
1
X
Y,Z
Y
A
A
0 1 - 1
d. Electrical Diagram
0
C
BCD is short form of Binary-Coded-Decimal. It Represents 10 decimaldigits (0-9) in 4-bit binary code (0000-1001).
1 0 0
0
0 1 1 0
*
e. Karnaugh Map of "E"
1 1 1 1
X
1 1 1
B
-
X
0 0 0
0 1 0 0
F
a. Truth-Table
1 1 - -
B = XY + XZ + YZ
-
X
0 1 0
0
Y
Ab. Karnaugh-Map
-
E
0 0 0 0
0 1 - 1
1 0 0
10 1 0
0 0 0
00 01 11 10
00
01
11
10
D1,D0
D3,D2
1 1 0 1
00 01 11 10
00
01
11
10
D1,D0
D3,D2
1
���������������� ����������������� ���������
RELAY DPST
SW SPST
C
M3 = A'BC
C
B
SW DPST
M6=ABC'
M1
M4
T = AB + AC + BC = AB + (A + B)C
B
M4 = AB'C'
C
M6=ABC'
Fig. 1-22 : Various Switches and Relays Types
+-
M1 = A'B'C
RELAY SPDT
COMMON
SW PUSHBUTTON
M
M7=ABC
9 Long Lines, Carrying High Current
C
d. Switches Remote Operation
L=A'B'C'
RELAY SPST
M4=AB'C'
e. Relays Remote Operation
B L = A'B'C'
B
Fig. 1-23 : "MAJORITY" Function Circuit
A
A
M7 = ABC
M3
c. Contacts Circuit
1-7
M5 = AB'C
M4=AB'C'
RELAY 4PST
SW DPDT
A
SW SPDT
M2=A'BC'
M6
+-
M7=ABC
B
b. Switches-Operated Circuit
B
A
B
C'
B'
a. Block-Diagram
M
B
M7=ABC
C
A
M2
C
Long lines, high power dissipation
M7
+-
M1=A'B'C
A
C
M3=A'BCB
C'
B
M6 = ABC'
C'
B
Fig 1-24 : 3-TO-8 DECODER CIRCUIT
M6=ABC'
RELAY 4PDT
M5=AB'C
B'
M4=AB'C'
A
M1=A'B'C
LAMP
M
A
M5
M1=A'B'C
M3=A'BC
C'
C
d. Relays-Operated Circuit
RELAY DPDT
A' C
A
C
M2=A'BC'
M2=A'BC'
C
COMMON
3 Long Lines, Carrying Low Current
M3=A'BC
M5=AB'C
C
c. Contacts Circuit
L=A'B'C'
+ -
A
b. Switches-Operated Circuit
C
B
A
a. Majority Boolean Function
M2 = A'BC'
M5=AB'C
L=A'B'C'
���������������� ����������������� ���������
&
Old USASymbols
X1'
b. Use of Gates
X1
CR1=Y1.X2+Y2.X2'+Y1.X1'+Y2.X1
T=Y2.Y3+Y1.Y3+Y1.Y2.Y3'+(Y2.Y3') = Y2 + Y1.Y3
Y2
CR1
T
Y2
1-8
OR
Y1
GATE
X1'CR1
CR1
6 Contacts , 12 Springs
c. Saving Contact Springs
Fig. 1-25 : Saving Contacts and Contacts Springs
IMHIBITION
6 Contacts , 12 Springs
b. Sneak Path Y2.Y3'
Y
X2'
OutputVariables (y,y')
>1
y
T
InputVariables (x')
Y2
X2
Y3
Y1
&
EXCLUSIVEOR
x1
X1'
y'
X1'
X1
b. Saving Contacts
X1
ExitationFunction(Y)
X1
CR1=Y1(X1'+X2)+Y2(X1+X2')
X2
Y2
x2
>1
Y1
S
R
Q
Q'
FF
y'
Y2
Fig. 1-28 : Logic Gate Symbols
S
R
Y
Y'
OldEuropeanSymbols
CR1=Y1(X1'+X2)+Y2(X1+X2')
X1
2 Contacts4 SpringsCR1=Y1(X1'+X2)+Y2(X1+X2')
X1'
Y2
y
Y1
y
X1
Y1
1
y'
Y3
x3
CR1
Y2
a. Use of Relay
a. Original Function
NOT
&
X2'
4 Contacts , 10 Springs
8 Contacts , 16 Springs
X1'
Y2
NOR
a. Original Function
y T
e. Saving Contact Springs
Y2
Y1
x4
d. Changing circuit schema
FLIP-FLOP
Y1
S
R
Y
Y'
Y3
OutputFunction (T)
AND NAND
X1'
X2'
Fig. 1-27 : Devices Outputs (fan-out)
1 Contact3 Springs
X2
T=Y2.Y3+Y1.Y3+Y1.Y2.Y3'
=1
Fig.1-26 : Sneak Path Creation
New SymbolsRecommendedby ISO
X2
Y1
Y3
RELAY
X1
X1
���������������� ����������������� ���������
0D
Fig. 3-30 : Multiple Output System
T1
A
0
0
a. General Case
0
B
C'
0
A
B
C
D
-
-
D
1-9
Xn
1
Fig. 1-31 : Minimize by Selecting Non-Prime Cells, in Multiple-Ourtut System
1
AC'
C. Gates Implementation
BCD
-
-
1
0
0
MultipleOutputSystem
C0
B+A'D
0
T=BC'+A'C'D=
C'(B+A'D)
=C'(B+A'D)
0
..... C
B
0
A
B
C
D
-
InputVariables
0
T2
-
B
(B+A')C'D
0
--
A
1
.....
1
-
0
0
InputVariables
-
D
A
X2
A'
0
d. Gates Implementation of (c) - 4 Gates
0
T2=A'B+BCD
T1
C
1
A'D
0
T1=AC'+BCD
0
1
C'C
a. Prime Cells Selection
0
D
-
A'
1
OutputVariables
0
-
-
b. Function T2
1
T1=AC'+BCD
A
A
b. Specific Case
B+A'
0
-
a. Function T1
D
0
=(B+A')C'D
C
MultipleOutputSystem
X1T2T3
-
C
C
0
-
D
Fig. 1-29 : Minimize by Selecting Non-Prime Cells
A'
1
D
B
-
0
B
A
B
C
D
1
c. Non-Prime Cells Selection
A
1
B
C'
A'B
-
OutputVariables
1
(Instead of A'C+BD)
0
X3
A
B
C
D
B
B
b. Gates Implementation of (a) - 5 Gates
0
1
T=BC'D+A'C'D=
Tm
-
10
0
1T2=A'B+BCD
���������������� ����������������� ���������
CHAPTER 2
RELAYS CASCADE SYSTEMS
Ladder Diagram Relays, Cylinders, Valves Symbols Sequential Sequences Relays Cascade Implementation Huffman Method Flow Diagram Primitive and Merged Flow Tables State Assignment Output and Excitation Functions
���������������� ����������������� ���������
a2
CR1
"OR"
START
b. Normally Closed
RedLamp
a. Position "-"
CR1
A+
a. Valve Without Return Spring
(open)
SetCircuit
Fig. 2-4 : Cylinder Actuation Valves
SwitchingCircuit-4
|
b. Basic Contacts Circuit
CR1
b. Example - Wiring Diagram
CR1
SwitchingCircuit-3
|
220V
(Closed) (open)
a1
A+
||
a1
CR1START
A+
Load-2
b. Valve With Return Spring
Load-4
+ -
a1
SwitchingCircuit1-n
c. General Circuit
Voltage
+ -
RedLamp
"AND"
2-1
a. Basic Circuit
a2
Load-n
CR1
STOP
GreenLamp
a. Normally OpenGreenLamp
b. Example - Home Electric Ladder Network
A-
Load-3
Fig. 2-2 : Set-Reset Relay Flip-Flopa2
"YES"
A+
STOP
Fig. 2-5 : Positions of Cylinder Limit Switches
|
START
|
a1
Fig. 2-6 : Graphic Symbols of Limit Switches
Fig. 2-3 : Flip-Flop Implementation Example
"YES"
A-
(open) (Closed)
a1,a2 = 01
+ -
a2
1
2
3
45
6
7
8
RELAY CR1
SwitchingCircuit-1
ResetCircuit
"YES"
STOP
c. Position "+"
+ -
a2
"XOR"
b. Position "Moving"
a. Example - Schematic Circuit
"YES"
CR1
SwitchingCircuit-2
a1,a2 = 00
CR1
Load-1
A+
a. General Schematics
A-
START
a1
CR1
+ -
CR1
(open)
a1,a2 = 10
STOP
A-
Fig. 2-1 : Ladder Diagram
���������������� ����������������� ���������
5
+ -
8
B
4. Cylinder "C" shifts the driller to next hole location.
+
A. Cylinders Position Chart
CylindersStates
b1
B+ ,
C
C. Cylinders Position Chart, Contacts &Valves Position
-
a2
C
-B
4
LimitSwitches
+
+
-
2
8
c2
-
-
5
2. Cylinder "B" lowers the driller thus performing drilling action3. Cylinder "B" lists the driller thus disconnecting it from the plate
-
-
C
a. Process Mechanical Representation
CylindersStates
-
8
c1
+
A
START
VALVE
A
6
5. Cylinder "B" lowers the driller thus performing drilling action
b2
A
CylindersStates
+
-
-
4
+
A
-
1
+
START ,
-
A+ ,
A
b. Sequence Description
+
c2
2-2
43
3
+
+
6
A
B+ , A-
3
Fig. 2-7 : Process Sequence Representations
LimitSwitches
c1
+
6
+
Cylinder "B" lowers and lifts a driller..
7
a1
B
Process starts by pressing START pushbotton
a1
1
8
Fig. 2-8 : Sequence Chart Diagram
b1
2
B- ,
-
1
B. Cylinders Position Chart & Contacts
B
-
b2
B
-
6
1 +
6. Cylinder "B" lists the driller thus disconnecting it from the plate
+
-
+
+
5. Cylinder "C" returns the driller to its initial position,and cylinder "A" releases the wooden plate.
7
7
3
C+ ,
2
B
Fig. 2-2 : "Intuitive" Design Problems
Cylinder "A" fastens/reases the wooden plate.
1. Cylinder "A" fastens the wooden plate
-
2
C
4
START
B- ,
5c. Sequence Short Representation
CylindersStates
+d. Cylinders Sequence Process Chart
START
C-
a2
A Sequence of Drilling Two Holes in a Wodden Plate
C
5
7
C
���������������� ����������������� ���������
START
B+ is also actuatedbefore cycle starts
cr1
TMR
cr1
Fig. 2-9 : "Intuitive" Design Problems
cr1
d. Step 3 : Correct and Actuate B+
tmr
b2
B+
2-3
b1
cr1
b1
b1
B+
Long Start causes Actuation ofA+ and A- simultaneously
PROBLEM
TMR
A-
PROBLEM
PROBLEM
a1
cr1
2
b2
Add reset (b2') to CR1
a2
e. Steps 4-5 : Correct and Actuate TMR and B-
START
a2
A+b1
TMR
B-
cr1
cr1 cr3
b2
(STEPS:
B+
B+ and B- are actuated simultaneously.
A+
START
START,A+,A-,B+,10 Sec delay,B-
CR1
cr1
f. Correct problems of (e)
START
cr1
START
b2
b1
START
b2
cr2
CR1
A+
a1
CR2
A+
tmr
3
B-
tmr
A-
cr1
a2
A-
4
a2
A+
cr1
B- g. Isolate Limit Swithes from Solenoids Current
cr1
CR1
CR1
1
c. Step 2 : Actuate A-
A-
B+
A+
a1CR3
A-
b. Step 1 : Actuate A+
a. Process Sequence (No Return Springs)
b1
cr1
5)
a2
cr1
a1
CR1 is actuated infinitily
���������������� ����������������� ���������
CR2
B-
* Same "Letter" may appear no more
cr
b1
Condition(s)
a single cycle
2
Group 1Termination
Group(s)
* Except for specific cases, groups
A+
B+
a. Sequence List Representation
, A- ,C-
Condition(s)
5
cr3
Condition(s)
than once in a group (to avoid
cylinder
conflicted commands to a cylinder)
A-
B-A- ,
START
START
C-
Fig. 2-12 : Typical Groups Partitioning
B+
1 9
cr
CR1
CR4
I
cr
Condition(s)
c1
cr
cr2
Fig. 2-10 : Cascade Method Target & Rules
I
3
CR3
, A+ ,
Fig. 2-13 : Typical Initial Cascade Circuit,
I
Partitioning doesn't depend on having
Group 2Termination
cr4'
Group(s)
cr2'
c2C-
B-
6
cr1
* Maximal size groups (to obtain
Group(s)
* Distinguish between situations
, C+ ,
Condition(s)
B+
cr4
a1
Group(s)
cr3
b. Sequence Chart Representation
cr
cr2
cr
START
I
, A+ ,
where a cylinder performs more than
cr3'
C-
C+
Condition(s)
RELAYS CASCADE SYSTEMS
A-
B+
I
C+
7
I
, C+ ,
A+
Fig. 2-11 : Typical Process Definition
cr3'
START
A+
2-4
Group(s)
* Avoid conflicting actuation of a
B-
, A- ,
A- ,
8
Group 4 (Last)Termination
of 3-Cylinder / 4-Groups Process
minimum number of group relays)
b2
cr4'
a2
Group(s)
I
or not having valves return springs cr1
4A+
Group 3Termination
V
���������������� ����������������� ���������
b1
cr3'
cr4'
STA
RT
a2
CR
4
CR
3
c. T
otal
Initi
al C
ircu
it
I
cr4'
STA
RT
I
cr2
cr4
cr2'
cr4
STA
RT
cr2'
CR
3C
R3
2-5
cr2
CR
1
cr1
cr3
cr2
cr3
cr2
b1
V
Fig.
2-1
5 : R
elay
Cas
cade
Des
ign
Pro
cess
1 (W
ith R
etur
n S
prin
gs)
, A+
,
cr3
I
cr4'
cr4'
, C+
,
cr
B+ a2
cr1
B-
cr3
cr3'
CR
2
I
c. T
otal
Initi
al C
ircu
it
cr3'
cr1
I
cr3'
A+
cr3
retu
rn s
prin
gs.
cr2
B-
CR
2
cr4'
cr3'
cr2
A+
A+
STA
RT
B-
I
a1
A+
C-
cr
cr3
C-
C-
IA
-
cr2
d C
ompl
ete
Cir
cuit
d. C
ompl
ete
Cir
cuit
, A- ,
A+
cr2
2. V
alve
s ar
e ac
tuat
ed e
lect
rica
lly (s
olen
oids
).
B+
cr3'
B+
dur
atio
n
cr
c2
c1
IC
-
B-
cr
cr2
cr1
STA
RT
CR
1
, A- ,
I
cr
cr2'
B+
cr1
1. C
ylin
ders
are
act
uate
d by
5/2
val
ves
with
out
, C+
,
V
, C+
,
cr4
cr2
A-
B+
a1B
-
retu
rn s
prin
gs.
C-
B+
b. G
roup
s P
artit
ions
CR
1
a1
I
cr3'
cr1
CR
4
b2
cr4
cr3
2. V
alve
s ar
e ac
tuat
ed e
lect
rica
lly (s
olen
oids
).
A-
cr4'
I
a1
cr4'
, A+
,
cr3
c1cr
3
cr1
STA
RT
A-
A-
cr1
cr cr
, A+
, a2
C+
a. P
roce
ss S
eque
nce
Info
rmat
ion
A+
cr2
CR
2
, C+
,A
-
cr2
a2
STA
RT
STA
RT cr3
C+
, A+
,
Fig.
2-1
4 : R
elay
Cas
cade
Des
ign
Pro
cess
1 (N
o R
etur
n S
prin
gs)
CR
4
b2
I
CR
4
a. P
roce
ss S
eque
nce
Info
rmat
ion
, A- ,
B-
cr
C+
cr4
CR
3
B+
, A- ,
cr2
cr3
cr3
CR
1
B+
cr4
I
C-
I
C+
cr2'
cr1
B+
c2
b. G
roup
s P
artit
ions
1. C
ylin
ders
are
act
uate
d by
5/2
val
ves
with
cr3'
cr1
A+
cr4
A+
cr4'
cr
CR
2
���������������� ����������������� ���������
1. C
ylin
ders
are
act
uate
d by
5/2
val
ves
with
ret
urn
spri
ngs.
D- ,
II
cr2
cr2
A+
,
II
C+
cr2'
cr3
cr3'
c1
Fig.
2-1
6 : R
elay
Cas
cade
Des
ign
Pro
cess
2(W
ithou
t Ret
urn
Spr
ings
)
a. P
roce
ss S
eque
nce
Info
rmat
ion
a2
cr1
cr1
cr4'
cr3
c2
STA
RT
D+
cr3
cr2
B+
,
a2
STA
RT
,
D-
b1
C+
Not
es :
CR
4 be
en c
ance
led
(use
less
).
cr2'
I
cr4
cr2
Rse
t CR
3 be
en c
orre
cted
STA
RT
cr2'
cr1
1. C
ylin
ders
are
act
uate
d by
5/2
val
ves
with
out r
etur
n sp
ring
s.
cr
a1
CR
1
cr1
Con
tact
a1
been
add
ed to
Set
CR
1
CR
2
cr4'
D+
,
cr1
C+
D- ,
cr3
cr4
B-
cr3'
D- ,
cr
CR
1
c. T
otal
Initi
al C
ircu
it
cr
a1
Fig.
2-1
7 : R
elay
Cas
cade
Des
ign
Pro
cess
2(W
ith R
etur
n S
prin
gs)
B- ,
A-
cr2'
cr1
cr2
cr1
d. C
ompl
ete
Cir
cuit
C- ,
CR
2
A+
,
I
STA
RT
,
(IV)
CR
2
CR
3
C+
,
cr1
cr3
cr1
cr2
I
cr3
CR
1
cr3
cr3'
CR
1
D+
,A
- ,
b2
C+
,
cr
A+
cr
cr3'
cr3
A- ,
I
c1a2
d2 b2
cr1
STA
RT
D+
A- ,
D+
cr2
(IV)
B+
D+
cr3
I
cr3'
cr2
A+
STA
RT
,I
C- ,
A+
,
cr2
B- ,
STA
RT
,
B+
cr
A+
cr3
cr2
B+
,D
+ ,
cr4'
C-
B- ,
cr2
cr
a1
I
2. V
alve
s ar
e ac
tuat
ed e
lect
rica
lly (s
olen
oids
).
CR
3
cr cr
a. P
roce
ss S
eque
nce
Info
rmat
ion
B+
,
cr2
cr
a2
D+
cr3'
d2
A+
cr1
C+
A- ,
CR
4
2. V
alve
s ar
e ac
tuat
ed e
lect
rica
lly (s
olen
oids
).
c. T
otal
Initi
al C
ircu
it
B- ,
cr1
A- ,
A+
,
cr4
B+
A+
,
cr2'
STA
RT
d1
B+
b. G
roup
s P
artit
ion
CR
3
cr4'
B+
d. C
ompl
ete
Cir
cuit
B-
cr1
cr3'
A- ,
A- ,
cr3
c2
cr3'
cr3
A-
CR
4
CR
2
B+
,C+
,
cr2
a1
D-
cr1A
- ,
I
CR
3
C+C
- ,
C+
,
A+
,A
+ ,
C-
A+
C- ,
cr2
cr
d1
b1cr
3
A+
,
cr
b. G
roup
s P
artit
ion
D- ,
2-6
D+
,
A+
���������������� ����������������� ���������
When input changes from "0" to "1", output change to "1" is delayed by T sec.
4 Sec
Note : Element behaves as a slow activated relay : it changes to active state only T sec afterbeen energized, but returns to rest state as soon as energizing terminates.
Timing chart of a 5-Sec delay timer (example)
5 Sec
As long as input is "0", output is also "0".
IN
Fig. 2-17 : "On-Delay" Timer Definition
"ON-DELAY" TIMER DEFINITION
2-7
OUT
IN
TIME
5 Sec
When input changes from "1" to "0", output changes to "0" immediately, and time count resets to 0.
"ON-DELAY" TIMER OUT
���������������� ����������������� ���������
CHAPTER 3 PLC (Programmable Logic Controller) PLC Definition PLC Hardware Control System PLC Programming Programming LIFO Stack Implementation Timers and Counters Modified Programming Commands Standard I/O
���������������� ����������������� ���������
LightsAudible Alarms (Bells,Buzzers,Sirens)
3-1. Programmable Controller (PLC) Representation
a. General
Conract Relay Output
ProgrammingUnit
OutputModules
12, 24, 48, 120, 230 Volt AC
Field signal may not be connected directly to PLC
3-1
Eliminate need to implement relays and its wiring
Central ProcessingUnit (CPU)
3-2. PLC Interfaces
Slow but OK for industrial timimg
Expensive
May be controlled and monitored by central computer
Reliable operation under industrial conditions
Contact Relay Coils
First applied at 60th-70th
Cost economical, requires small space
b. Discrete Output Devices Actuated by PLC
b. Block Diagram of PLC
Micro-computer for controlling industrial processes
Contains protection from oposite polarity connectios
Relay Contacts
PLC - Programmable Logic Controller
Limit Switches
c. Standard Discrete I/O Interface Modules
Pneumatic or Hydraulic Cylinders and Motors
3-3 Input/Output Modules
Photoelectric Switches
Push-Button Switches
Built in self diagnostics
Contains timer' counters and more
Contains protection from voltage transients and noise
Not economic for small control processes
Adapted to work in industrial conditions
5V DC (TTL Level)
Input/output are adapted to high voltage/current devices
Electrical common isolation
Memory
Implement binary and analog signals, PID
Fans
Motor Starters
PLC
Selector Switches
Perfect reliability
Sensor Switches (Level, Pressure, Temperature etc)
Proximity Switches
Heaters
InputModules
12, 24, 48, 120, 230 Volt DC
Valve Solenoids
a. Discrete Input Devices to PLC
Converts field signals to logic level, and vica versaAdapted to implement DC and AC signals
ControlledSystem
Solution to the design of complex systemsEasy to program and easy to change it
���������������� ����������������� ���������
002
Sol
enoi
d
000
PLC
9
Mot
or
PLC
6
006
Rel
ay
PR
OC
ES
S
6
b. S
ever
al P
ossi
ble
LAN
Top
olog
ies
001 .........
PLC
2
m
PLC
1
PLC
Lim
itS
witc
h 1
Con
trol
led
Sys
tem
PLC
Pro
gram
Cod
ing
n
001
PR
OC
ES
S
5
000
PR
OC
ES
S
7
I/O M
odul
es (F
ield
Mou
nted
with
Mul
tiple
xer)
CR
......
....
PR
OC
ES
S
n
PLC
3
Leve
l FS
5
Sw
itch
Bul
b
BU
S
PR
OC
ES
S
4
PR
OC
ES
S
1
Tem
p TS
3
STA
R
Lim
itS
witc
h 2
PLC
n00
7
PLC
6
PLC
8
PR
OC
ES
S
2
Leve
l FS
4
PR
OC
ES
S
9
Fig.
3-6
: PLC
Mac
ro N
etw
orks
004
Out
put
Mod
ules
Fig.
3-4
: G
ener
al I/
O C
onne
ctio
n D
iagr
am
Con
trol
led
Sys
tem
PR
OC
ES
S
8
3-2
HO
ST
PR
OC
ES
S
3
005
Sol
enoi
d
I/O M
odul
es (P
LC M
ount
ed)
003
a. P
LC T
ypic
al N
etw
ork
Inpu
tM
odul
es
PLC
7P
LC 4
RIN
G
PLC
......
....
Fig.
3-5
: D
iffer
ent I
/O C
onne
ctio
n Lo
catio
n
002
......
....
a. P
LC-M
ount
ed I/
O
PR
OC
ES
SO
R
................
STO
P
003
STA
RT
b. R
emot
e-M
ount
ed I/
O
004
���������������� ����������������� ���������
Xn
D- ,
Y7
X3
a1
B-
CPU
OUTPUTMODULE 2
Y1
PLC
START
Y1
+ -
Fig. 3-7 : PLC General Configuration
X5
INPUTMODULE 2
b. Input Table
Y6
X0
Y4
INPUTDEVICES
INPUTMODULE N
D+
SENSOR 2
C-
c1C+
X2Y4
LOAD 2
b2
Y7
X0
X7
Y2
A-
OutputModules
OUTPUTDEVICES
SENSOR 1
C-
B- ,
LOGICLEVEL
OUTPUTMODULE 1
(no return springs)
A+ ,
CYLINDER SYSTEM
Fig. 3-9 PLC I-O Variables Assignment
LOGICLEVEL
INPUTMODULE 1
d2
B-
A+
X5
B+ ,
X1
INPUTMODULES
Start
HIGH/LOWVALUES
HIGH/LOWVALUES
C+
X6
X3
X8
c2
A-
X2
HIGH/LOWVALUES
X7
C+
(LOGIC LEVEL)
X2
A- ,
C-
B+
c2
INPUTMODULE 1
Y8
LOGICLEVEL
d1
c. Output Table -
+ -
Y8
START
OUTPUTMODULE M
a1
X1
A-
X2
A+
D+
Y1
Y6
Y5
X0
Y1
D-
a2
LOAD 1
D+
CR1
X6
Ym
INPUTMODULE 2
B+
a. Process sequence
Fig. 3-8 : Typical PLC Control System Example
D-
OUTPUTMODULE 2
X1
B+
a2
PLC
PLC SYSTEM
a2
X8
LOGICLEVEL
INPUTMODULE 3
no return springs
Y3
LOGICLEVEL
A-
X4
HIGH/LOWVALUES
Y4
d2
START , C+ ,
a2
Y2
C+
3-3
CRk
e. PLC and I/O System
X1
LOAD m
b1
Start
Y2
Y1
c1
OUTPUTMODULES
OUTPUTMODULE 1
A+
CPU
D+
HIGH/LOWVALUES
Y2
A+ ,
Y3
LOGICLEVEL
Y3 X4
InputModules
d. Output Table -
d1
SENSOR n
with return springs
Y2b1
b2
, C- ,
A+
a1
Y5
HIGH/LOWVALUES
a1
���������������� ����������������� ���������
f. Simplified Ladder Diagram
LED
Y15
PLC
X19
CR1
Stop
c. Relay Ladder Diagram for ACS
System is turned-on by pressing STARTbutton, andremains activated after releasing the button
OR Y13
Typical air-condition system is operated by two push-botton switched :
STOP button that deactivate the system
b. Block Diagram
OutputModule
OUT Y13
Start
LED
CR1
Y15
START
X18
AND NOT X19
Y13
d. PLC Ladder Diagram
a. Air-Condition System (ACS) representation
System is tuened-off by pressing STOP button, and remainsde-activated after releasing the button
OutputModule
CR1
3-4
Stop
LED
Y13
CR1
T.S.
X17
ACS
ACS
Start
InputModule
Start
START button that operates the system
X19
T.S.
Y13
CR1
X18
X18
X17
INPUTMODULE
A red LED is illuminated as long as the system in on
InputModule
X17
On
OffSystem
X17
Y13
Fig. 3-10 PLC Control for Air-Condition System (ACS)
CR1
Y15
STOP
e. PLC "Internal" Ladder Diagram
CR1
OUT Y15
d. I/O Assignment Table
STORE X17
ACS
CR1
Y15
InputModule
(Temperature Switch)
(ACS supply must be isolated from sensors)
LED
Y13
X18
AND NOT X18
Air ConditionControl Panel
T.S.In addition, control circuit is also equipped with a temperature sensor,that protects the system from over-heat (by turns it off)
LED
X19
g. PLC Program
OUTPUTMODULE
Stop
T.S.
ACS
X19
(No isolation problem since allI/O are isolated by modules)
���������������� ����������������� ���������
7
Y13
OU
T
AN
D N
OT
AN
D
0
X3
Con
nect
ed to
3128
a. P
artia
l Lad
der
Dia
gram
of a
Con
trol
Sys
tem
f. P
LC P
rogr
am
Y13
cr1
Y12x5 X5
AN
D
x411
cr8
OU
T
B+
6
(sim
plifi
ed)
b2
X5
6
x3
Y12
Out
put M
odul
e
d. P
LC P
rogr
am
2cr
1
b2
cr3
cr6
OR
Y13
OR
cr1
STO
RE
X5
cr3
cr2
cr2
X4
2 8
Fig.
3-1
1 : S
impl
ifica
tion
of P
LC L
adde
r D
iagr
am
B+
AN
D
x3
cr6 c. P
LC L
adde
r D
iagr
amO
UT
cr1
d2
4
x3
AN
D5
a2
b. I
/O A
ssig
nmen
t
X4
C+
OR
cr6
x4
cr3
cr1
cr3
3-5
cr1
Y13
Y12
cr3
Y12
x3S
TOR
E
cr2
10 4
a2
cr8
cr3
5
C+
9
AN
D N
OT
Y13
9A
ND
Y12
cr3
3O
R
X5
AN
D N
OT
cr2
CR
8
0
OU
T
e. S
impl
ified
Lad
der
Dia
gram
OR
d2
OU
T
cr2
CR
8
x371 1
cr2
cr6
cr6
10
cr2
STO
RE
STO
RE
AN
D
x3
X4
Inpu
t Mod
ule
cr1
AN
D
���������������� ����������������� ���������
STORE NOT
CR10
CR10STORE NOT
(2nd in)
3
Load
CR5
X4
CR2
8STORE
a. Ladder Diagrama. Ladder Diagram
c. PLC Programming Option 2
(3rd out)
1st
WEAPONSTACK
5
CR11
8
2nd
Shoot
cr10
AND
1st
OR
Shoot
1
WEAPONSTACK
CR2
STORE
X2
AND
CR1
Empty
X2
1st
X2
X1
X2
X4
3-6
AND
OR
OR
Shoot
1
AND
Commands that refer to stack - such as "AND STORE" , "OR STORE" etc- perform operation on current "upper" stack element (the one that beenlast entered), and deletes that element from stack, while "Pushing up"previous eelements. Action is similar to unloading a weapon stack, orshooting.
STOREAND NOT
OUT
AND
X1
b. PLC Programming Option 1
STORE
CR10
(4th in)
b. PLC Programming of (a)
CR5
1
STORE
WEAPONSTACK
X2
4
cr11
2
AND NOT
X1
6
(1st in)
CR10
AND0
STORE
CR6
STORE NOT
1st
(4th out)
STORE
X1
AND
0
Command STORE first stores current value in a stack, while "pushingdown" previous stack elements, and then clears latest calculatedvalue. Action is similar to loading weapon stack.
X4STORE NOT
CR11
STORE
4th
(3rd in)
WEAPONSTACK
X4
CR10
Load
STORE NOT
OR
(1st out)
cr10
STORE NOT
X2
STORE
OR
AND
1st
cr11
Shoot
STORE NOT
AND
Load
5
4
7
3rd
0
Y5
CR11
AND NOT
STORE NOT
WEAPONSTACK
Y4
Fig. 3-13 : Use of LIFO Memory Stack
CR6
OUT
2nd
CR1
CR11
6
STORE NOT
5
2nd
X1
STORE NOT
Fig. 3-14 : Multiple Use of LIFO Stack
3-12 PLC LIFO Stack concepts
(2nd out)
WEAPONSTACK
a. Ladder Diagram
CR11
3
7
X4
1st
WEAPONSTACK
Y5
b. PLC Programming of (a) CR3
4
3-15 : LIFO Use Oprions
OR
Y4
X2
x3
Y4
Load
3
CR3
X3
STORE NOT
OUT
X3
1st
2OR
2
OUT
WEAPONSTACK
AND
WEAPONSTACK
���������������� ����������������� ���������
C+
cr1
cr3
cr3
x4
cr1
STA
RT
X5
CR
1
e. P
LC P
rogr
am
OU
T
X6
Y5
c2
x0
cr4
x4
cr1
cr2
CR
4
B-
OR
x5
C-
C+
Y3
Y5
A+
CR
1
OR
x5
B+
AN
D
B+
Ass
ignm
ent
CR
4a2
c2
Y6
3-7
cr2
cr2
B-
cr2
CR
2
cr1
OU
T
Y4
b. R
elay
s C
asca
de C
ircu
it
CR
3
CR
2
cr3
cr1
cr3'
Fig.
3-1
6 : P
LC C
asca
de S
yste
m D
esig
n
X0
OR
NO
T
x6
x3
OU
T
x2 Y5
cr2'
cr1
cr4'
cr2
AN
D
X2
STO
RE
STO
RE
STO
RE
X6
STO
RE
CR
2
STO
RE
A-
cr4'
c1
CR
1
X5'
OR
cr3
x1
x5
AN
D
CR
3
C+
cr2
x6
a1
Y4
x2
Y6
cr3
CR
3
x6
a. P
roce
ss s
eque
nce
Gro
ups
part
itini
ng
STA
RT
cr1
cr1
cr4
OU
T
STO
RE
AN
D N
OT
cr3
cr2
c1
AN
D N
OT
Y2
AN
D N
OT
x0
Y4
AN
D
CR
4
cr2
STA
RT
cr4
cr2
C+
cr3
cr2
AN
D N
OT
Y1
STO
RE
cr3
AN
D
b2
I
Y1
STO
RE
OU
T
OU
T
y2'
cr4
b1
cr1
x1cr3 Y3
B-
cr3
c1cr
2
cr4
cr1
C-
C-
x4
b1
AN
D
cr1
A+
cr3'
Y2
OR
Y6
y4'
cr4
OU
T
cr4'
b2
B+
A-
ORAN
D N
OT
C-
a1
cr3'
x3
cr4
Y3
d. P
LC C
asca
de C
ircu
it
OU
T
STO
RE
NO
T
cr4
IIIcr
2II
X1
Y2
OROU
T
X3'
Y1
AN
D
A+
c2
cr1
cr4
c. P
LC V
aria
bles
a2
cr4
A-
cr1
cr1
cr4
IV
cr3'
OU
T
���������������� ����������������� ���������
x1
y2
x2
X6
X6
cr3
c2
cr3'
C+
Y5
Y1
X3
C-
X4
a2
y4
STA
RT
a2
CR
3
c1
CR
4
Y4
CR
3
AN
D
c2
A-
Y1
Rel
ays
STA
RT
OU
T
cr3'
Y5
C+
CR
3y1
Y4
Y2
= C
R2
AN
D N
OT
AN
D
cr4
A+
Y1
x3
III
cr3
y4
Y4
cr2
STO
RE
Ass
ignm
ent
B-
AN
D
STO
RE
CR
1
AN
D
c2
b. R
elay
s C
asca
de C
ircu
itc.
PLC
Var
iabl
es
AN
D N
OT
3-8
y2
y4'
OU
T
cr2
Y4
OR
cr1
CR
2
Y2
X6
Y3
B-
X2
B-
Y5
y1
AN
D
Fig.
3-1
7 : P
LC S
impl
ified
Cas
cade
of F
ig. 3
-16
cr1
Y6
CR
3
I
OR
b1
x5
OR
cr1
cr3
cr3
x0
X5
y4'
Y6
b2
c1
cr1
OU
T
STO
RE
NO
T
d. O
ptim
ize
CR
STA
RT
X3'
OU
T
Y6
b1X
5
AN
D N
OT
Y1
OU
T
cr2
a1
Y2
A-
STO
RE
OU
T
X5
C-
cr4'
x4y1
OR
Y2
cr4
B+
Y2
CR
3
B+
cr4'
Y4
Y2
A+
X6
A+
CR
3
y2'
X1
cr2
IIA
ND
NO
TIV
AN
D
AN
D
cr3
X5'
C+
c1
cr4
cr3'
cr2'
cr3
CR
3
Y4
Y1
= C
R1
a1
AN
D N
OT
X0
A-
y2 X2
C-
OR
NO
T
STO
RE
cr1
Y3
Y3
x4
C-
X1
Y1
b2
OR
X0
B+
a. P
roce
ss s
eque
nce
Gro
ups
part
itini
ng
e. P
LC C
asca
de C
ircu
it
f. P
LC P
rogr
am
y1
C+
x6
Y4
cr3'
OU
T
OR
Y4
= C
R4
Y2
���������������� ����������������� ���������
Y1
X1
OUT
OUT
Variables States
OUT
CR2 Y7=1 , CR2=1
Y1
a. Proper Rung Order
I/O Update
AND NOT
OUT
1. Input variables (Xi) status cannot be changedby program commands, and remainsunchanged until next cycle
x4
4. Return to (1) and start new cycle
Y7=1 , CR5=1
X1
CR1
X1
cr4
3. Program commands refer to latest updateof the variables.
X1
CR5
3. Wait until end of scan time (*)
X1
at Beginning of Scan
X1
1. Read & store status of all external inputs (Xi)2. Output variables (Yi) and internal variables(CRi) status are controlled by PLC program.They are updated once during each cycle
Fig. 3-19: Importance of Proper Rung Order (Pulse Shaper)
CR4
x4
STORE
CR1
Next Scan
a. PLC Scan Cycle Order
y7
AND NOT
Scan Period
b. Variables Status During Scan Cycle
cr6
Y1
STORE
X4=1 , Y7=1
c. Effect of Scanning Action on Relay States
X1
CR4=1 , CR6=1
CR6=1 , Y8=1
CR1
Y1 Y1
Y8
CR1
CR6=0 , Y8=0
CR1
Fig. 3-18 : Effect of Scanning Action in PLC
b. Improper Rung Order
3-9
X4=1 , CR4=1
STORE
X1
X1cr1
Y7=0 , CR2=0
CR6 CR4=0 , CR6=0
cr1
CR1
2. Run program commands in its written order
This Scan
Y7
Y1
y7
���������������� ����������������� ���������
CR1
CR1=1
cr1
1
CR1
cr1
cr1
cr2
PROGRAMFLOW
MOTOR
cr2
SCHEMATICDRAWING
Y1
MOTOR
Y1
STORE
Y1
END-LOOPRESULT
MOTOR
START
Y1
MOTOR
Y1
Y1
Y=1
PLCPROGRAM
Y=1
cr2
OR
WRONG
Y1
CR1=1
cr2
Motor current flows through sensors)
cr2
Fig. 3-20 : Right/Wrong Cases
Y1OUT
START
STORE
cr2
RIGHT
RIGHT
CR1
OUT
OUT
a. NEVER SPLIT OUTPUT FUNCTION INTO 2 (OR MORE) OUTPUT SUB-FUNCTIONS
OR
Y1
CR2=0
Y=1
SPECIFICCASE
0
cr1
OUT
CR1
OUTSTORE
1+0=1
OUT
1
CR2=0
WRONG
Y=0
CR1
Y=0
STORE
b. LOAD MUST BE ISOLATED FROM SENSORS
STOP
3-10
STOP
STORE
cr1
cr1
STORE
Motor current flows through separate contact,thus isolated from input sensors
���������������� ����������������� ���������
X2
X2
X2
X3 X1
X3
CR1STORE
X1
X2
b. Programmable Simplified Circuit
OUT
a. Original Circuit
OUT
X4
AND
X2
CR1
CR1
X3
X3
X1
cr1
AND
OUT
X4
X4
STORE
AND
X2
X4
AND
OR
X2X4
cr1
cr1
STORE
X2
X1OR
CR1
d. PLC Program
STORE
X1
OR
Fig. 3-21 : PLC Program Simplification
X2
X3
3-11
OR
X2
X3
X2
X2
AND
STORE
X2
STOREcr1
AND
X4
X1
cr1
STORE
STORE
AND
X4
OUT
CR1
STORE
AND
c. Ladder Sub-Circuit
X3
CR1
e. Simplified Program
AND
AND
X2
CR1
cr1
X1
STORE
AND
AND
STORE
���������������� ����������������� ���������
TMR1
(120)OUTCOUNT
TIMERS AND COUNTERS
The following implement PLC timers and counters of two companies :
TMR1 (in)
b. Specific Case
tmr1 (out)Time
Note : Examples refer to specific PLCs. Actually there exist a lot ofdifferent timers and counters.
tmr1
General Electrinc (GE)
Texas Instruments (TI)
delay
tmr1
delay
X1=0 Timer is Reset
Fig. 3-23 : PLC "On-Delay" Timer Model (GE)
3-12
delay
TMR1
(120)OUTCOUNT
X1=1 Timer Enabled and counting time
c. General Case
Fig. 3-22 : PLC Timer And Counter Models
X1
a. "On-Delay" Definition
F1
���������������� ����������������� ���������
tmr1
x1
TMR2
a. Flash Block Diagram
(Light Valve)
Fig. 3-24 : Design Flash-Light system using "On-Delay" timers
(0.5 Sec)tmr2
Switch
(0.5 Sec)
3-13
FlashControl
x1
Y1
tmr1=Y1
tmr2
TMR2
Switch
TMR1
TMR1
tmr1
c. PLC Ladder Diagram
b. Flash Timing Diagram
d. Detailed Timing Diagram
Flash
Flash Light
Flash light is actuated while switch is on
���������������� ����������������� ���������
a. Ladder Diagram
CR2
200
Fig. 3-25 : 2-Input PLC Timer (TI - Texas Instruments)
AND NOT
STORE
CR2
TMR
STORE
STORE
empty
OUT
(5) CR2
(200)
X1
STORE
TMR1
STORE
5
X2
OUT
2
AND NOT
TMR2
STORE
(5)
5
5
2
X2=1 Timer Enabled X2=0 Timer is Reset F2=1 Timer Enabled F2=0 Timer is Reset
Out
15
b. Programming of (a)
3-14
y1
y1
empty
(n)
CR1
20
(5)
F1
X1
y1
X1
35
X1=1 Timer Run X1=0 Timer Stops
y1
y1
X1
5
25
OUT
TMR2
10
empty
CR2
d. Programming of (c)
5CR2
empty
F1=1 Timer Run F1=0 Timer Stops
X2
c. Timing Diagram (Delay=0.5 Sec)
X1
X1
y1
STORE
5
Y1
TMR2
(5)
Reset
F2
STORE
y1
CR1
TMR
c. Simplified Ladder Diagram
TMR1
-
TMR1
TMR1CR2
CR2
Counta. Specific Case
CR1
-
Y1
y1
-y1
TMR1
STORE
-
X1
OUT
30
CR2
STORE NOT
TMR
CR2OUT
Y1
X1
Fig. 3-26 : Design Flash-Light system using TI timers
CR2
1
b. General Case
empty
���������������� ����������������� ���������
CR1
Timer is actuated by either of the twoswitches. If timeout occurs beforeseconad swithced been turned, lock isdiabled
In order to make sure that a single manager will not be able to turn on both switches, theswitches been located far from each other, and lock is to be opened only if the twoswitches are turned on within 0.5 Sec.
(5)
(5)
After being opened, the lock is closed as soon as any of the switches is turned off.
x1
3-15
TMR
CR1
TMR
Switch A
(0.3 Sec)
d. Solution Step 2
CR1
x2
Y=1 when both switches are operated, andtimer output tmr1 is off
x2CR1
x2
x1
x1
x1
Lock
x2
x2
x2
f. Solution Step 3 - Complete Solution
Missing timer actuation
(0.3 Sec)
a. Security Lock Specifications
x1
Fig. 3-27 : Two-Hands Circuit Using PLC
Switch B
(5)
y1
Missing timing dependence
x2
Y1
X1
TMR
c. Solution Step 1
Timer output always is set to "1" after0.5 Sec. This disables lock even if ithad been opened correctly.
A security lock is to be opened only on confirmation of two managers, simultaneously.Each manager confirms by turning on a personal switch (A and B).
e. Solution Step 3
Y1
x1
(0.3 Sec)
Y=1 when both switches are operated
CR1
CR1
Y1
If one switch is turned on at least 0.5 Sec before second switch is turned on, the security lock isdisabled, and may later be open after releasing the pressed switch and repeat the process.
x2
x2
Y1
X2
x2
If Y1 been set to "1", it keeps beconnected by by-passing cr1 contact(acts as flip-flop).
b. PLC I/O table
Y1
���������������� ����������������� ���������
a. Specific Case
120
F3=1 Counter Enabled F3=0 Counter is Reset
CTRi
X1= O-->1 One countX2=1 Counter Enabled X2=0 Counter is Reset
Y2
CTR
F1
(Reset)
empty
X3=1 Counter Enabled X3=0 Counter is Reset
CTRi
F2= O-->1 One count
Y2
3-16
CTR
b. General Case
OUT
CTR3
X1
LOAD NOT
OUT
F2(n)
F1
CTR3
F1= O-->1 One count
X2
X2
CTRi
(Event)
X1
(Up/Down)
F1 determines UP or DOWN mode
(25)
a. Specific Case
(Reset)
b. General Case
25
X2= O-->1 One count
X3
c. Programming of (a)
(Event)
LOAD NOT
X1 determines UP or DOWN mode
Fig. 3-28 : PLC Two-Input UP Counter (TI)
STORE
F3
LOAD NOT
CTR1
Y1
c. Programming of (a)
Fig. 3-29 : 3-Input UP/DOWN Counter (GE)
(n)
OUTCTR3
X2
(Up/Down)
X1
CR1
F2(120)
X3
STORE
LOAD
X1
F2=1 Counter Enabled F2=0 Counter is Reset
CR1X2 CR1
���������������� ����������������� ���������
(6)
CR1
d. Solution Step 1
OUT
(6)
1
(10 Sec)
STOREx2 (d2)
1
OUT
Y2
CR1
x1
x2 (d2)
Y2
cr6
x1 (d1)
Y2
X1
STORE NOT
x2 (d2)
COUNTER
3-17
cr2
cr1
(NOT USED)
Y2
Connected to
x1
e. Solution Step 2
OUT
COUNTER
CR2
x1 (d1)
x2 (d2)
Infinite cycles
STORE NOT
AND
Input Modules
x0
D
x1 (d1)
X2
g. PLC Programm
100
d2
Y1
+ -
(100)
STORE
Y1
x0 (Start)
D-
START
cr1
Circuit performs 6+1/2 Cycles,and stops
f. Solution Step 3 - Complete Circuit(NOT USED)
Y1
x0 (Start)
cr1
Y2
START,(D+,D-) repeat 6 times,D+,10 Sec DELAY,D-
Y1
AND NOT
D+
TIMER
x2
CR1
x1 (d1)
Output Modules
cr1
START,(D+,D-) repeat 6 times,D+,10 Sec DELAY,D-
X0
cr2
cr1
x1 (d1)
CR2
d1
CTR1
x2
D-
cr1
1
D+
OR
a. Required Sequence
Y1
STORE
cr1
TMR1
b. Cylinder Type
6
d2
c. PLC I/O Table
OUT
Fig. 3-30 : Step-By-Step Design of Sequence
d1
STORE NOT
���������������� ����������������� ���������
CR1OUT
OUT
Y1
X3
X5
1st
Elevator runs automatically (without human control), from 1st floor to 5th floor, and vica versa,
X5
Notes : CR2 control elevator direction
OUT
OR
UP
OR
b. PLC System Configuration
OUTPUTMODULE
3-18
TMR1
(100)OUT
COUNT
RESET
Each floor is equipped WITH a unique contact, that is closed when the elevator reaches that floor.
TMR1
Y2
CR2
X3
X4
while stopping for 10 seconds in each floor.
X1
CR2
5th
CR0
These contacts are implemented as input sensroes for PLC control system.
X2
CR2
INPUTMODULE
a. System Description
X4CR0
(NOT USED)
X1
c. PLC Ladder Diagram
Y2
CR2
2nd
AND
OR
CR2
INPUTMODULE
X1
CR0
AND NOT
OR NOT
CR0
OR
X1
X3
CR1
CR0
Fig. 3-31 : "Saturday" Elevator
MOTOR
OUTPUTMODULE
Y1 - Up direction
INPUTMODULE
STORE
AND
OR NOT
Y1
Y1
STORE
MOTOR
CR2
CR1
CR2
3rd
STORE
CR0
CR0
CR2
OUT
INPUTMODULE
STORE
100X5
X5
Y2
4th
OUT
X2
X5
CR1
INPUTMODULE
OR
X1
d. PLC Program
PLC
X4
CR0
X2
Y2 - Down direction
CR1
An elevator exists in a 5-floor building.
DOWN
CR0
CR1
AND NOT
���������������� ����������������� ���������
CR1
X3
AddingRelay
cr1Y1
Impossible
a.
Non SerialParallel
X1
X5
X5
d.
CR2 = X3.X5 + X1.X4.X5
CR2
CR1
NO cost
Impossible
X4
X4
Almostunlimmited
Possible
Relays System
Impossible
X3
X1
Parallel
f.
CR1 = X1.X2 + X3.X4.X2
cr1
X3
X3
Limitted
Support
Property
X4
X2
X1
Number ofContacts
b.
PLC System
X2CR1 X1
Unlimitted
CR1 = X1.X2 + X3.X4.X2
CR1
Required
X2
e.
X5
X1
Serial
X5
i.
(CR1 = X1.X3+X2.X4++X1.X5.X4+X2.X5.X3)
Sneak Path X3
X1
Expenssive
Y1
NO cost
X1
h.
CR1
Possible
c.
X1
X3
CR1
Timers /Counters
Limmted
Signal Flow
CR2
Almost not required
X2
Expenssive
X4
Fig. 3-32 :Differences Between Relay and PLC Ladder Diagram
Possible
g.
X4
CR2 = X3.X5
X1
X2
3-19
X5
Reliability
Races
���������������� ����������������� ���������
(mul
tiplie
d by
-1)
Dig
ital/A
nalo
g co
nver
sion
The
LAN
can
be
orga
nize
d ac
cord
ing
to a
ny o
ne o
f a s
ever
al p
ossi
ble
LAN
Topo
logi
es (a
rran
gem
ents
), su
ch a
s "C
omm
on B
us",
"S
tar"
or
"Rin
g".
Mic
ro-A
utom
atio
n :
Fig.
3-3
9 : L
ogic
Ope
ratio
ns
Fig.
3-3
4 : M
aste
r C
ontr
ol R
elay
(MC
R) C
omm
and
Fig.
3-3
7 : T
ypic
al "
AD
D"
Inst
ruct
ion
Blo
ck
SQ
UA
RE
RO
OT
AD
D
(or
corr
ecpo
ndin
g bi
ts o
f tw
o sp
ecifi
ed r
egis
ters
)
NO
R
Dat
a Tr
ansf
er In
stru
ctio
ns :
Fig.
3-3
6 : A
rith
met
ic In
stru
ctio
n
a. L
adde
r D
iagr
am
...
a. L
adde
r D
iagr
am
OR
Mat
hem
atic
al O
pera
tions
MIC
RO
-AU
TOM
ATI
ON
ver
sus
MA
CR
O-A
UTO
MA
TIO
N
CO
MP
AR
E
STO
RE
X6
Mov
es a
ll bi
ts o
f a r
egis
ter
to r
ight
or
left
3-40
Dat
a C
onve
rsio
n In
stru
ctio
ns
STO
RE
+
...
Reg
iste
r X
NO
T
If X
6=0,
then
the
next
(3) o
utpu
ts a
re fr
ozen
, and
the
PLC
cont
inue
s its
sca
n at
the
rung
follo
win
g th
e th
ird
outp
ut
2. C
entr
aliz
ed D
ata
Acq
uisi
tion
Reg
iste
r Z
MU
LTIP
LIC
ATI
ON
SU
BTR
AC
T
<
X6
Inve
rt
=c.
Com
man
d D
efin
ition
THIS
CO
UR
SE
RE
FER
S T
OM
ICR
O-A
UTO
MA
TIC
ON
LY
Logi
cal S
hift
s :
Enh
ance
d la
dder
dia
gram
inst
ruct
ions
are
han
dele
d ve
rydi
ffer
ently
in d
iffer
ent P
LC m
odel
s. T
herf
ore,
onl
y a
few
typi
cal e
xam
ples
are
sho
wn
here
.
Mat
rix
Ope
ratio
ns
Fig.
3-3
8 : T
ypic
al "
CO
MP
AR
E"
Inst
ruct
ion
Blo
ck
Mor
e
XO
R
1. D
istr
ibut
ed C
ontr
ol
=X
6
DIV
ISIO
N
Thes
e ch
ange
the
cont
enta
of a
spe
cifie
d re
gist
er.
3-20
Ove
rflo
wO
utpu
t
Fig.
3-4
2 : P
LC M
icro
/Mac
ro S
yste
ms
Def
initi
on
GO
TO
3
(inve
rts
all b
its)
b. P
rogr
amm
ing
Line
s
JMP
Reg
iste
r Y
EN
HA
NC
ED
LA
DD
ER
DIA
GR
AM
INS
TRU
CTI
ON
S
...
b. P
rogr
amm
ing
Line
s
Com
plem
ent
Fig.
3-3
3 : S
uppo
rt O
ther
Dat
a Ty
pes
Reg
iste
r Y
Aut
omat
ion
of a
larg
e pl
ant,
cons
istin
g of
man
yin
divi
dual
aut
omat
ion
isla
nds.
Use
s a
larg
eco
mpu
ter
or a
larg
e P
LC, t
hat c
oord
inat
es th
eop
erat
ion
of th
e in
divi
dual
aut
omat
ion
isla
nds.
Eac
h au
tom
atio
n is
land
is u
usua
lly c
ontr
olle
d by
its
own
cont
rol s
yste
m, s
uch
as a
sm
all o
rm
ediu
m-s
cale
PLC
("D
istr
ibut
ed C
ontr
ol")
.
c. C
omm
and
Def
initi
on
Byt
e/W
ord
form
at (b
inar
y gr
oups
)Ty
pica
l Con
vers
ions
:
Fig.
3-4
1 : D
ata
Com
man
ds
BC
D to
Bin
ary
MC
R
NA
ND
If X
6=0,
then
the
next
(3) o
utpu
ts a
re k
ept a
t log
ic "
0" (s
hut o
ff)
LATC
H (U
NLA
TCH
)
JMP
(3)
Mac
ro-A
utom
atio
n :
X6
AN
D
Bin
ary
to B
CD
Mac
ro-a
utom
atio
n m
akes
use
of a
LA
N (L
ocal
-Are
a-N
etw
ork)
, whi
ch li
nks
the
vari
ous
stat
ions
or
auto
mat
ion
isla
nds
with
the
cent
ral s
uper
visi
ngco
mpu
ter
or P
LC. T
he u
se o
f a L
AN
pro
vide
s :
...
Ther
e ar
e m
any
such
inst
ruct
ions
, use
d to
mov
e da
ta w
ithin
the
PLC
Reg
iste
r X
AD
D
Con
trol
(Ena
ble)
3
Dig
ital t
o/fr
om B
inar
y
Aut
omat
ion
of a
sin
gle
mac
hine
, or
asm
all g
roup
of m
achi
nes,
als
o ca
lled
an "
Aut
omat
ion
Isla
nd".
Fig.
3-3
5: J
ump
(JM
P) C
omm
and
Abs
olut
e V
alue
MC
R(3
)
Con
trol
(Ena
ble)
CO
MP
AR
E
>
���������������� ����������������� ���������
0
Des
tinat
ion
regi
ster
2
00
1
AN
ALO
G O
UTP
UT
Dat
a Ta
ble
0
0
12 b
its R
egis
ter
hold
ing
anal
og v
alue
Sin
ce A
/D c
onve
rter
s ar
e ex
pens
ive,
they
are
oft
en s
hare
d by
sev
eral
4 to
8 c
hann
els.
One
cha
nnel
is r
ead
and
stor
ed o
n ev
ery
scan
.
loca
tion
0 - 1
0 v
olt D
C
1
(Low
ala
rm li
mit)
Slo
t
03
f. T
ypic
al "
PID
Con
trol
ler"
Inst
ruct
ion
Blo
ck
3-21
00
Num
ber
of c
hann
els
4
Ana
log
inst
ruct
ion
used
1
1 Dat
a Ta
ble
2. C
ontr
olle
r O
utpu
t
1
1
Slo
t
05
Trac
k
Fig.
43
: Sup
port
Ana
log
Dat
a
1
0
3.
K
(P
-con
trol
)
0
(Tra
cks
inco
min
gva
riab
les,
eve
n if
"Con
trol
" is
off
)
(Act
ive
loop
con
trol
)Ana
log
Tran
sduc
er
loca
tion
D/A
Vol
tage
Sig
nal
1
0
0
c.. T
ypic
al "
anal
og In
" bl
ock
Inst
ruct
ion
+/-
5 v
olt D
C
01
0
PID
CO
NTR
OLL
ER
Rac
k
o
Wor
d lo
catio
n
Con
nect
ed to
Reg
iste
r
5.
T
(D-c
ontr
ol)
(Oct
al c
ode
200
= 12
8)
11
11
12 b
its
Ana
log
Out
put m
odul
e
1
(Slo
ts 0
to 7
per
rac
k)
1
0
e. T
ypic
al "
Ana
log
Out
" In
stru
ctio
n B
lock
(Hig
h al
arm
lim
it)
0
0
(Giv
en b
y an
alog
inpu
t mod
ule)
Vol
tage
Sig
nal
1
or
0
(Sen
t to
anal
og o
utpu
t mod
ule)
In s
ome
PLC
's, t
he P
ID C
ontr
olle
r is
impl
emen
ted
by a
spe
cial
out
put m
odul
e, i.
e. b
y ha
rdw
are.
Inot
hers
, it i
s pr
ogra
mm
ed u
sing
a s
peci
al In
srtu
ctio
nB
lock
, suc
h as
sho
wn
here
.
A/D
+/-
10
vol
t DC
(Slo
ts 0
to 7
per
rac
k)
6.
Set
Poi
nt
0 - 5
vol
t DC
0
Ana
log
inpu
t mod
ule
0A
nalo
gin
stru
ctio
nus
ed0
(Rac
k w
ith 8
slo
ts)
a. S
tand
ard
Ana
log
Out
put I
nter
face
Mod
ules
0
0
1
or
0
(Sin
ce th
ere
are
8 ch
anne
ls, t
he 8
slo
ts w
ould
be
assi
gned
the
Des
tinat
ion
Reg
iste
r 20
0 t
o 2
07 )
01
Reg
iste
r S
tora
ge
0
0
(Rac
k w
ith 4
slo
ts)
Con
trol
b. S
tori
ng a
n A
nalo
g In
put1
0
Reg
iste
r ho
ldin
g an
alog
val
ue
0
4 - 2
0 m
A
1
Ret
urn
Line
d. T
ranf
erri
ng a
Wor
d to
Ana
log
Out
put M
odul
e
PID
Con
trol
ler
(Ena
bles
Out
puts
)
0
Ret
urn
Line
8
1
4.
R
(I-c
ontr
ol)
Not
Use
d
AN
ALO
G IN
1. C
ontr
olle
d V
aria
ble
Ana
log
Tran
sduc
er
Sou
rce
regi
ster
3
00
Num
ber
of c
hann
els
8
(Oct
al c
ode
300
= 19
2)
1
Reg
iste
r S
tora
ge
Wor
d lo
catio
n
8
1
10 -
50 m
A
Rac
k
40
1
���������������� ����������������� ���������
CHAPTER 4
INDUSTRIAL SWITCHING ELEMENTS
Electronic Gates Gates Implementation Input/Output Module Electric Relays Pneumatic Valve “Gates” Moving Parts Logic (MPL) Design Considerations Switching Elements Properties
���������������� ����������������� ���������
SN54LS76
9
54 : Military Family
g. Chip Configuration
SN74LS27
8
9
2
7
VCC
6
Many More Families
2
(not SSI)
8
SN74LS049
6
12
1
10
SN74LS76
Function
High / Low Power Dissipation
4
4
8
1
74 : Commercial Family
10
And Many More
1112
1
4
VCC
4
j. Technologies Characteristics
6
4
1
16
15
14
23
J
CLK
K
Q
Q
PR
CL
c. Tripple 3-Input NAND Gate
4
SN54LS32
1
13
VCC
3
10
d. Dual 4-Input NAND Gate
10
SN54LS04
VCC
5
High / Low Speed
k. Grid-Array Package
7
14
2
5
GND
15
3
High / Low Power Supply Voltage
SN74LS20
89
11
3
914
6
(Serial Number)
12
12
13
Vendor
1
13
16
VCC
11
12
SN54LS00
7
i. Families
12
SN54LS20
VCC
SN54LS27
3
13
6
4-1
b. Quad 2-Input OR Gate
SN 54 LS 00
11
4
7
GND
2
GND
9
14
5
14
2
7
14
9
2
11
4 8
SN54LS00
5
12
13
5
7
e. Hex INVERTER
9
6
12
11
10
78
J
CLK
K
Q
Q
PR
CL
7
GND
3
5
13
High / Low Power Drive (Fan-Out)
1
14
13
SN74LS32
Family
6
2
5
10
8
3
1
10
10
6
Fig. 4-1 : Typical Simple Gates Packages (SSI - Small Scale Integrated)
11
a. Quad 2-Input NAND Gate
Difference : Temperature Range
h. Chip Name "Code"
8
GND
11
3
SN74LS00
f. Dual J-K FLIP-FLOP
Technology
14
GND
���������������� ����������������� ���������
AB
(CD)'
Fig.4- 3 : Equivalent Circuits for Function AB+A'C
(d)
1
23
G
A
4
56
0 0 1 0
Required Signal (OUT)
1 1 1 0
9
108
B
C
b. Eliminate Bounce by a Simple Flip-Flop
B
(c)
9
108
C
B
4
56
A'C
C
A
A'C
B
C
T = ABCDEFGH
b. 7 Gates , 2 Packages , 3xT delay
0 0 1 0
CD
A
A'
A'
AB+A'C
E
AB+A'C
2
C
A
4
56
00 01 11 10
0
1
C
A,B
H
B
((AB}'.(CD)'.(EF)')' =
9
108
a. AND-OR-NOT system
1 1 1 0
A
(Increase Speed)
D
PRESS BOUNCE
AB+A'C+BC
B
4 Gates , 1 Package
a. 7 Gates , 2 Packages , 7xT delay
AB+A'C
(AB)'
B=1
AB
EF
H
D
(e)
C
(a)
AB
(AB)'
1
B
4 Gates , 3 Packages
4
56
A'C
A
C
RELEASE BOUNCE
Transition From 011 to 111
00 01 11 10
0
1
C
A,B
BC
AB+CD+EF
E
B
AB
(b)
D
(EF)'
C
9
108
12
1311
Fig. 4-5 : Hazard Elimination
T
ANTI-BOUNCE CIRCUIT
A
B
b. NAND system
D
E
AB+A'C
A
AB
(Gate 1 Slower Than Gate 2)
C
(Save Packages)
1
23
T
F
12
1311
4-2
C=1
F
A
F
B
b. NAND system
E
= AB+CD+EF
A
Fig. 4-2 : Equivalent Circuits for Function AB+CD+EF
B
OUT
G
OUT
1
23
(A'C)'
F
a. AND-OR-NOT system
A'
Fig. 4-6 : Switch Bounce Elimination
Fig. 4-4 : Equivalent Circuits for Function ABCDEFGH
1
23
A
A' CDa. Contact Bounce (A,B) and
���������������� ����������������� ���������
Amplifier
3
OUTPUT
Load
a. AC Input Module (IAC)
Fig. 4-8 : AC Input and OutputModules for Electronic Gates
3
4
2
Fig. 4-10 : Relay Construction
Zero
Vol
tage
Cir
cuit
VCC
VCC
112-120 VAC
1
OUTPUT
OUTPUT
Fig. 4-9 : DC Input and OutputModules for Electronic Gates
VCC
5
2
3
2-60 VDC
TransientProtectionCircuit
4
Make BeforeBreak
1
2
- +
Fig. 4-11 : Typical Relay Package
4
NormallyOpen
GND
GND
b. AC Output Module (IAC)
GND
12-120 VAC
Break BeforeMake
1Load
Fig. 4-12 : Typical Relay Contacts
4-3
2
5
INPUT
3
DC Output Module (IDC)
OUTPUT
DC Input Module (IDC)
Fig. 4-7 : Typical Opto-IsolatedInput Module
4
GND
12-120 VAC
NormallyClosed
���������������� ����������������� ���������
A
T=A'
4-4
A
A
a. YES Gate b. NOT Gate
T=A+B'
Hot
T=A
f. IMPLICATION Gate
A
T=A.B'
T=A
B
+
+-
B
(T=A+B)
A
+
T=A'
Fig. 4-13: Pneumatic Valve Gates
Hot
T=A+B'
Cold
e. INHIBITION Gate
B
i. AND/OR Gate
+
h. YES/NOT Gate j. INHIBITION/IMPLICATION Gate
C
Cold
T=A.B'
m. COLD Pressure Less Than HOT -HOT Flows Into COLD
+
T=A+B
B
A
T=A.B
l. Almost equal HOT/COLDpressure - No Flow
+
A
B
A T=A.C+A'B
A
+
AB
T=A.B
A
B
d. OR Gate
+
k. Non-Valve "OR" Element
+-
T=A+B
g. SELECTOR Gate
B
+-
c. AND Gate
���������������� ����������������� ���������
A
X1
A
A
X3
B
>1
Fig. 4-18 : Pneumatic OR Gates
D
T=X3(X1'+X2)+X4(X1+X2')
E
B
C
&
T
T=X1+X2
B
b. Position 2
X2
S = A . B
X4
S = A . B
A
X2
P2
P1S = A + B
Fig. 4-19 : Pneumatic AND Gate
Fig. 4-16 : Pneumatic Universal Gate (MPL)
Fig. 4-17 : Pneumatic Universal Gate (MPL)
B
(Dreloea, E.Germany)
A
A
C
T=X5(X1'+X2)+X4.X1.X2'
4-5
X1
S = A + B
BFig. 4-15 : Shuttle Valve
X5
(Samsomatic, W. Germany)
B
E
Fig. 4-14 : Operation of 5/2 Spool Valve
P1
a. Position 1
(OR Gate)
X4
D
X1
P2
X2
S = A + B
A
���������������� ����������������� ���������
Fig. 4-20 : Pneumatic Gates (TELEMECHANIQUE, France)
4-6
���������������� ����������������� ���������
Fig. 4-21 : Fluid Flip-Flop (Wall Attachment Principle)
Fig. 4-22 : Fluid OR-NOR Gate Q1 = C1 + C3 , Q1 = (C1 + C3)’
Fig. 4-23 : Fluid NOR Gate (Impact Modulator, AIR Logic, USA) T = (C1 + C2 + C3 + C4)’
4-7
���������������� ����������������� ���������
Fig. 4-24 : Pneumatic Binary Amplifier (Single Stage, AIR LOGIC, USA)
Fig. 4-25 : Pneumatic Binary Amplifier (Two Stage, CLIPPARD, USA)
4-8
���������������� ����������������� ���������
Fig. 4-26 : Comparison Between Switching Methods
4-9
���������������� ����������������� ���������
Fig. 4-27 : Comparison Between Switching Elements
4-10
���������������� ����������������� ���������
��������������CHAPTER 5 HUFFMAN METODE� Feedback Memory Concept Typical Block Diagram Primitive Flow Diagram Primitive Flow Table Merge diagram Merged Flow Table States Assignment Exitation and Output Functions Ladder Circuit Realization PLC Program Random Inputs Systems
���������������� ����������������� ���������
c. Adding External State Input (y) May Eliminate Problem
DirectionDetectorSystem
Forward Green Bulb
0 0 0 1 0 0 0 1 ......
* enables to implement large Karnaugh maps and Pseudo Karnaugh maps.
Note : Assume that piston changes direction only after reaching cylinder edge.
Zm
a2
Backwords Red Bulb
0 ... 1 ...
L1
Combination System
Example - A system detects cylinder pistonmovement direction : forward (toward A+position), or backwords (toward A- position).
CR1
(Inpossible in a combinational system)
Limit switch a1
L1
External Outputs
Y
L1
1 ... 0 ...
MemoryExitation
Huffman method is very effective in reducing the number of group relay flip-flops.
0 ... 1 ...
b. Same Input Generates Different Outputs
External Outputs
Y
f. Multiple Internal Generated State Signals
0 ... 1 ...
Huffman/PLC Combination
* eliminates the complexity of Huffman method,
L2
Fig. 5-1 : Huffman Method - Basic
0 ... 0 ...
Set
S
Design process by Huffman method may become very complex, from"State Assignmsnt" step, and on. Furthermore, it is based on Karnaughmaps, which eliminate the number of involved variables.
L2
Fig. 5-2 : Sequential System Concepts
X1
MemorySystem
Combination System
a2
Xn
0 1 0 0 0 1 0 0 ......
0 ... 0 ...
d. Internal Generated State Signal
L2
It is also effective for design of systems with random inputs.
a1
Internal State
Internal State
Combinational System
CRk
Limit switch a2
0 ... 0 ...
y
cr
a1
Flip-Flop
1 ... 0 ...
S
Combinational System
a. System Definition
Z1
The Huffman-PLC method :
L1
Reset
System reads limit switches a1 and a2 andoutputs signals to green or red bulbs. Duringforward movement (input=00), green bulb mustbe illuminated, and during backwords movement(same input) red bulb must be illuminated,
L2
a1
External Inputs
* implements flip-flop for each state
R
DirectionDetectorSystem
External Inputs
R
5-1
Memory
When system realization is based on PLC or on electronic gates, number of "relay"flip-flops doesn't actually effect system cost (or effect is minor)
a1 a2
L1
e. Sequential System General Diagram
10 00 01 00 10 00 01 00 .......
a2
Set-ResetControl
a10 ... 0 ...
L2
a2
���������������� ����������������� ���������
td2
RESTRICTION : DUE TO TRANSIENTHAZARDS, ASYNCHRONOUS SYSTEM CANNOTHANDLE CHANGE OF SEVERAL INPUTSIGNALS SIMULTANEAUSLY (EXCEPT FORSPECIFIC CASES).
Time (Sec)
Fig. 5-5 : "On-Delay" Timer
X
Step 7 : States assignment
Set
Reset
(Unstable State)
Step 4 : Merge options Diagram
a. Definition
Unstable State
cr
td3
IN
Reset
Fig. 5-3 : States Transition Process
Memory
Unstable State
d. Relay Flip-Flop Transition Response
When input changes from "0" to "1", output is delayed T sec
OUT
Step 1 : System requirements definition
5 Sec
In order to evoid it, simultaneous changes are replaced by sequential changes. This result isachieved due to memory (flip-flop) delay.
Step 3 : Primitive flow table
Step 11 : System Logic Circuit
MechanicalDelay
Z2
cr
Step 5 : Merge groups selection
5-2
Combinational System
X
Each transition from state to state is combined ofunstable state followed - after delay- by stablestate.
Step 2 : Primitive flow diagram
When input changes from "1" to "0", output is changedimmediately, and time count is reset
c. Circuit Example
Flip-Flop
Flip-Flop Delay
td1
5 Sec
e. Transition Timing
td4
ElectricalDelay
b. Example of Timing Diagram (5 Sec Delay)
4 Sec
b. Hazard Problem and Its Elimination
Step 8 : Output table
Fig. 5-4 : Huffman Design Steps
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Step 6 : Merged flow table
Step 10 : Outputs expressions
a. Essential Restriction Rule
Set
Z1
Change of an external input may couse a change ofstate variable, which is fed to system input. Result maycause simultaneous change of two input signals(external and internal).
Step 9 : Flip-flops exitation expressions
StableState
Set
Time (Sec)
���������������� ����������������� ���������
-
4
a1,a2
cr3
START
Start moving towards A+
0
STORE
0
X0
With Return Spring
R3' = cr4' + a2'
00
a1
a2
-
-
3
CR3
e. States Definitions
4
cr3 AND
OR
Cylinder moves towards A+None (A-)
a2
4
x1
1
7
a1
x1
-
STORE
A+
R3 = cr4.a2
x2
-
10
5
AND
AND
A+
a1,a2 / A+
6
S4 = cr3.a2
cr
a1
-10/1CR2
STORE
OutputCommand
A+
7
cr4
3
1
k. States Assignment6
01
8
cr2
cr3
Keep moving towards A+
01/0
-
01/0
CR4
Cylinder moves towards A-
-
4
1
a1,a2
x1
2
Y1
OR NOT
x1
8
State
3
X1
cr2
OUT
5
--
OR
cr3
a1
OUT
5
Moving towards position +
7
S2 = cr1.a2
START , A+ , A- , A+ , A-
00/0
cr2
cr2
6
- cr3
cr1
a1,a2
3
cr1
a1,a2
1
(refer to 5-5 for Initializationand Output Rules)
cr1
Cylinder at A+
S1 = cr4.a1
cr
cr1
START
8
-
-
-
p. Relays Ladder Diagram
a1
c. Cylinder Type
Position 1
2
R1 = cr2.a2
Solenoid A+
None (A-)
3
7
cr1
CR2
10/1
00/1
3
2
q. PLC Circuit & Program
-
cr1
cr2
OUT
1
1Keep moving towards A+
8
-
STORE
CR2
AND
Keep moving back
1
Limit contact a2
CR1
AND
HUFFMAN DESIGN METHOD
00
A+
OR
cr4
Cylinder at A+
f. PrimitiveFlow-diagram
AND
-
11
a1
8
01
A+ = cr1 + cr3
x2
(With Returned Springs)
5
R2 = cr3.a1
AND NOT
2
n. Relays Ladder Diagram
5-3
STORE
+
4
Start
cr4
cr1
OR NOT
cr4
4
x0
5
cr3
6
0
cr3
-
OR
00
0
1
Limit contact a1
x2
cr4
00 R4 = cr1.a1
x2
STORE NOT
01
00/1
01
1
OR
cr2
cr2
-
(refer to 5-5 forMerging rules)
a. Sequence
8
cr3
cr1
x2
A+
4
x1
00
Cylinder at A- (Start)
x2
Cylinder State
10
10
m. Exitation and Output Functions
cr1
cr47
cr4
11
x1
R1' = cr2' + a2'
cr4
START
A+
1
4
cr3
cr3
CR4
00/0
a2
START
-
STORE NOT
6
j. Merged Flow-table
0
x1
None (A-)
2
cr1
OR
Start moving towards A+
8
7
{1,2) , (3,4) , (5,6) , (7,8)
cr3
cr2
SYSTEM
0
a2
cr2
x1
A+Start moving back (towards A-)
11
11
-
cr2
2
3
2
A+ = START.cr1.a1 + cr1.a1' + cr3
cr1
STORE NOT
Cylinder at A-
7
i. Selected Groups
7
7
b. Sequence Chart
-
8
01
STORE
a2
STORE NOT
STORE
CR3
3
6
cr3
-
-
-
CR1
Cylinder moves towards A-
d. Basic Block Diagram
10
6
Y1
cr3
Fig. 5-6 : Sequence A+,A-,A+,A- , Huffman Method
AND
10
STORE
-
h. Merge Diagramcr1
cr1
OR NOT
a1
1
cr2
R4' = cr1' + a1'
CR3
x1
5
1
x0
cr3
Action
10
A
00
00
cr3
R2 '= cr3' + a1'
a1
AND NOT
-
5
3
00
S3 = cr2.a1
1
OUT
x2
1
3
7
11
cr2
2
-
o. PLC I/O Tables
5
Position 2
-
x1
x2
Start moving back (towards A-)
A+
cr3
cr1CR4
cr1
10
cr2
AND
-
1
1
X2
01
5
S1 = a1(cr2+cr3)' = a1.cr2'.cr3'
-
x1
CR1x1
CONTROL
1
0
5
Y1
6
0
g. PrimitiveFlow-table
l. Output Table
OUTPUTS
AND NOT
-
cr1
INPUTS
a2
OUTAND
Keep moving backNone (A-)
- OR NOT
���������������� ����������������� ���������
a1
-
Limit contact a2
1
-
0
cr3
11
0
x2
3
5
{1,2) , (3,4) , (5,6) , (7,8)
6
R3 = cr4.a2
l. Output Tables
0
cr3
p. PLC Ladder Diagram
A+ = START.cr1 + cr3
cr3
STORE NOT
5
1
-cr2
(See page 5-9 forMerging rules)
Cylinder at A+
a2
4
00/1
-
-
OR NOT
OUT
CR3
1
1
0
x1
a2
(refer to 5-5 for Initializationand Output Rules)
cr2
-
cr4
cr1
OUT
CR2
AND
Start moving back (towards A-)
0
10
STORE1
5
STORE
0
-
a1
f. PrimitiveFlow-diagram
OR NOT
A-
x2
CR3
8
3
No action required
Cylinder State
7
-
cr4
a1,a2
6
5-4
-
c. Cylinder Type
INPUTS
OR
-
R3' = cr4' + a2'
x1
8
10
-
-
cr2
01
START
g. PrimitiveFlow-table
S1 = a1(cr2+cr3)' = a1.cr2'.cr3'
AND
cr2
+
10
No action required
cr1
4
X0
1
0
-
1
-
S2 = cr1.a2
x0
Solenoid A-
cr
cr2
10
cr3
AND NOT
8
d. Basic Block Diagram
11
-
OR
-
cr3
cr2
2
S3 = cr2.a1
01a1,a2
-
cr1
a1
STORE
00
1
OUTPUTS
(Without Returned Springs)
3
1
1
6
2
a1
a1
i. Selected Groups
OR
o. PLC I/O Tables
1
a1,a2
X1
R2 = cr3.a1
cr3
cr1
Y2
Start moving towards A+
-
11
R1' = cr2' + a2'
cr4
00
a. Sequence
cr1
A
-
4
00
0
Y2
a2Action
-cr4
No action required
0
OUT
a1
cr2
S4 = cr3.a2
-
4
x2
CR1
cr4
START
10
cr2
A-
cr3
5
01
-
1
CR3
-
A-
cr
6
A+
10
8
A+ = cr1 + cr3
0
x2
x2
a2
Cylinder at A-
j. Merged Flow-table
X2
A-
0
START
6
CR2
7
1
7
7
4
8
x2
k. States Assignment
cr1
0
5
x2
State
6
Y1
0cr3
-
q. PLC Circuit & Program
0
1
A-
2
11
CR4
x1
x2
01
a1,a2
A+
AND
Cylinder moves towards A-
A+
01/0
n. Relays Ladder Diagram
OR NOT
3
8
OUT
cr3
cr4
-
A- = a2
CR1
a1,a2 / A+
5
0
0
x17
7 Y1
R2 '= cr3' + a1'
-
0
0
cr3
-
AND
Y1
b. Sequence Chart
Position 2
00
00/0
-
STORE NOT
Start
x2
cr4
cr2
-
CONTROL
00
1
1
AND
2
2
-
cr2
h. Merge Diagram
cr3
10
5
STORE
-
00
1
cr
STORE
OUT
A+
1
-
5
CR2
-
4
cr3
R4' = cr1' + a1'
AND
HUFFMAN DESIGN METHOD
Position 1
00
-
A-
2
1
Solenoid A+
CR4
Without Return Spring
No action required
2
Limit contact a1
0
R4 = cr1.a1
10/1
-
A+
Y1
11
-
cr1
R1 = cr2.a2
4
START
Start moving towards A+
a1,a2
OR
cr1
x1
a2
AND
Cylinder moves towards A+
1
3
-
x1
0
3
01
3
0
OR NOT
-
OUT
x2
cr1
0
0 -
START , A+ , A- , A+ , A-
10
-
00
8
00/0
01
1
x1
STORE NOT
OutputCommands
Cylinder moves towards A-
-
cr2
cr4
7 4
cr1
Start moving towards A+
cr3
AND
0
-
a2
cr1
STORE
-
0
01
7
5 7
cr3
1
A+
Position - (initial)
7
2
m. Exitation and Output Functions
STORE NOT
a2
1
SYSTEM
Fig. 5-7 : Sequence A+,A-,A+,A- , Huffman Method
3
3
-
8
x0
cr2
3
Start moving back (towards A-)
-
cr3
cr2
-
5
-
cr1
01/0
6
S1 = cr4.a1
cr1
cr3
-cr4
x1
-
Moving towards position +
CR1
10/1
00/1
00
-cr1
CR4
AND NOT
-
cr3
OR
-
e. States Definitions
A+
6
-
cr2
STORE
���������������� ����������������� ���������
0
3
a. Merge A
vailable Cases
State S
tate
1-
-
3
41
1
Usually, transient tim
e is very short with respect to steady states duration.
Row
j
2
a. Flip-Flop Transition Cases
b. Merge N
on-Available C
ases
1
0 --> 0
-
00
But transition betw
een steady states is done by pathing through anon-steady state : transients. If w
e don't take care of transition states, saydefine it as don't care, system
output may be w
rong during thosetransients.
-
Transient Outputs
CR
1=CR
2=CR
3=....CR
i=....=CR
n = 0
Rule 1 : If outputs of 2 steady states are sam
e, the output of thetransition betw
een them m
ust be equal to the steady-stateoutput.
2
Fig. 5-9: FF Exitation R
ules
Generally, if there is not enough inform
ation about the importance of
transient outputs, the following rules are used :
This is acheived by writing the initial function in its negative
conditions, and negate it (similar to im
plementing the "0"
Karnaught table).
4
This state is not part of the flow table, and and therefor is not
taking care of. As a result, if w
e refere only to the flow table, w
ecan't force the initial state C
R to becom
e "1".
System
Inialization
-
In some cases, w
e may ignore the need to define transitions output,
usually when output inertion is high. For exam
ple, standard 220valve is actuated by A
C current, m
eaning that during each cycle itscurrent is 0 tw
ice, but it illuminates as required. This a sim
ple casew
here due to high enersion, transient outputs do not affect theexpected output.
1
On system
reset (or power on), all state variables are "0", m
eaning :
2
0 --> 1
In most cases, only steady-state output is specified.
Row
i
3
Rule 2 : If outputs of 2 steady states are different from
eachother, the output of the transition betw
een them m
ay be definedas don't care.
Row
i
1-
1
Merged R
ows (i,j)
0
So, instead of w
riting the CR
states where the transition to that state m
ustbe carried on, w
e write the states w
here the transition is forbidden, as afunction of C
R or several C
Rs, and then negate it.
0
4
Row
j
Therefor, driving the system to its expected initial state, m
ust be doneby a function that doesn't depend on any operated C
Ri, but only on
non-operated CR
i' .6
1
Fig. 5-8: Merge Flow
Row
s Rules
0
5-5
-
Tran Current N
ext Set R
eset
Most (or all) set/reset functions are product of state-variable (or m
ore),but since all of them
are 0, all functions are inhibited.
1
2
0
5
1 --> 0
Negating this expression, using D
e-Morgan rules, bring to a
function that depends on CR
', and this may be carried on.
0
1
1 --> 1
���������������� ����������������� ���������
1
3
{1} , {3} , {2 , 4}
5
4
3
{1 , 2} , {3 , 4}
{2} , {1 , 3 , 4}
3
2
1
4
(j)
(b)
2
{1} , {2 , 3} , {4}
3
2
or
2
4
(l)
3
24
{1 , 2} , {3 , 4}
1
or
1
{1 , 4} , {2 , 3}
{1 , 2} , {3 , 4}
1
2
{1 , 2 ,3} , {4}
1(m)
4
{1 , 2} , {3 , 4 , 5 , 6}
{1 , 2} , {3} , {4}
3
4
(e)
(f)
or
{1 , 2 , 4} , {3}
1
4
{1 , 3} , {2} , {4}
4
(h)
or
(c)
3
{1 , 2} , {3 , 4}
2
6
(k)
{1 , 2 , 3 , 4}
4
(g)
3
or3
3
{1 , 2 , 3 , 4 , 5 , 6}
(i)
{1 , 2} , {3 , 4}
1
1 {1 , 4} , {2 , 3}
{2 , 3, 4} , {1}or
{1 , 2 , 3 , 4) , {5 , 6}
Fig. 5-10 : States Grouping Examples
3
4
2
{1 , 2 , 3) , {4 , 5 , 6}
2
2
3
1
2
(a)
1
(d)
4
4
1
5-6
or
{1 , 2} , {3} , {4}
{1} , {2 , 3} , {4}
or
5
2
6
{1 , 2 , 4) , {3 , 5 , 6}
���������������� ����������������� ���������
6
Huffman Method
0
-
-
0
{1 , 2} , {3 , 4 , 5 , 6}
00 10 11 01
00
01
11
10
L.H
Drain Valve
--
M
1
T
V
--
T
a. Process definitions
-
MIXINGSYSTEM
STARTM'
-
-
M
-
0
F'
4
START
cr1
F
-
1
--
0
0
--
Cascade Method
-
H
M
START
c. Groups Partition
-
cr1,T
-
1
4
-
M = H
-
h. Exitation Map (SR)
Process is same as defined ai Fig. 6-25/a .
S = L'.START
{1 , 2 , 3} , {4 , 5 , 6}
D
I
2
Fig. 5-12 : Automatic Mixing System
1
L (Low)
{1 , 2 , 3} , {4 , 5 , 6}6
j. System Functions
1
-
(0)
0
5
c. Merge Diagram
2
00 10 11 01
00
01
11
10
L.H
Mixer Motor
4. On timeout, motor is turned off, and DRAIN valve is opened.
(1)
Start
(L')
I
5
-
5
TMR
1
A mixing system requires filling a tank with liquid, mix it for aspecific time period and then drain the liquid out.
cr1,T
4
0-
-
0
0
cr2
, F ,
-
1
4
00 10 11 01
00
01
11
10
L.H
-0
1
01
CR
-
b. Process Sequence
-
D
5
cr1,T00 10 11 01
00
01
11
10
L.H
a. Process presentation and requirements definitions
-
cr3
-
0
cr2
f. Merged Flow Table
-
0
-
-
F'
TMR
I
3
0
TMR
LHT
cr2
2
-
D = L.cr1'
--
000 100 110 111 101
b. Primitive Flow Table
cr1,T
2. Liquid fills tank until HIGH level sensor is operated.
-
START
(H)
- 1
3
1
F = H'.cr1
-
0
CR1cr2
1
0-
TMR
(0)
Timer
-
-
-0
Tmr
I
,
1
0 1
CR3
4
-
Level Switch
D
0
-
0
-
, F ,
-
Fig. 5-11 : Automatic Mixing System
1
00 10 11 01
00
01
11
10
L.H
1. Sequence starts by pressing START buttom. This opens FILL valve.
3. At that time FILL valve is closed, mixing motor is turned on, and a timer is activated
0
0 0
-
F
cr2
D'
-
1
-
-
cr1
05
cr3
I
cr1,T
F D M Ymr
H
D
-
L
0
-
M
D
1
-cr1,T
START
-
H (High)
-
An automatic process is represented as follows :
M
6
0
M'
g. "Path" Map
0
0
3
(T)
4
1
-
1
-0
CR2
2
, D'
LHT
5. When tank is empty, LOW level sensor contacts open, and DRAIN valve is closed.
{1 , 2 , 3 , 4} , {5 , 6}
-
0
--
1
000 100 110 111 101
1
2
M
e. Selected Groups Partition
I
(0)
R = tmr
00 10 11 01
00
01
11
10
L.H
-
Level Switch
-
6
-
Fill Valve
0
-
1
--
I
0
10
- 0
0
-
cr3
-
cr3
0
L
L
F
-
3
d. Cascade Contacts Circuit
d. Minimized Groups Partition
cr1
3
,--
D
-
-
-
-
1
0
F
0-
-
1
6
-
TMR = H
-0
-
-
0
4
1
i. Output Tables
5-7
0-
-
-
���������������� ����������������� ���������
00/01
X1
Photocell 2
X1,X2/Z
-
X1,X2
10/02
2
e. Primitive Flow Table
-
b. System Block Diagram
1
0
2
i. Merged Flow Table
{1,5},{2,3,4}
2
4
-
2
Z
(0)
State 3 : High element in check area (11)
00 10 11 01
Z
-
{1,2,5},{3,4}
l. System Functions
5. X2 is covered by all sizes. X1 is covered by elements over
0
h. Selected Options
4. Photocells X1 and X2 are placed in specific locations.
1
0
3
S1 = X1
5
0
3. Reject is performed by opening a reject door - Z=1.
5
2 3
01/04
1
j. State Assignment
(0)
01/15
0
-
(Z = X1'.X2.cr1')3
4
5
0
5-8
0
(S1 = X1.X2')-
X1
the defined specific heigh limit.
Photocell 1
R1 = X1'.X2'
Height Limit
Z = X2.cr1'
-
3
-
X1,X2
a. System Definition
1
2
00 10 11 01
Reject Door
-
{1,5},{2,3,4}
f. Merge Diagram
c. States Definitions
5
1. Different size elements are transferred on a conveyor belt.
0
State 5 : Low element in inside check area (01). Pushed out
0
X2
1 -
1
5
X2
1
State 4 : High element starts leaving area (01)
0
1
X1,X2
00 10 11 01
cr1
-
g. Merge Options
Fig. 5-13 : Height Detector System Design
2
00 10 11 01X1,X2
4
4
cr1
1
(R1 = X1'.X2'.cr1)
4
11/03
HEIGHT DETECTORSYSTEM
d. Primitive Flow Diagram1
1
k. Output Table
-
1
State 1 : Check area empty (00)State 2 : High element enters area (10)
2. All elements that are below specific height limit must be rejected.
3
���������������� ����������������� ���������
Fig. 5-14 : Realiation of Fig. 5-13
STORE
1. Different size elements are transferred on a conveyor belt.INPUTS
R
a. Summary of Fig. 5-13
X1
X2
d. PLC I/O List
AND
X1
X2
Q'
cr1
STORE
4. Photocells X1 and X2 are placed in specific locations.
S
b. Relays Implementation
(R1 = X1'.X2'.cr1) OR
Photo-cell X1
CR1 = (X1 + cr1).(X1 + X2) =
X1
OUT
x2
CR1
x1
(cr1 = Q)
Z
X1
= X1.X1 + X1.X2 + cr1.X1 + cr1.X2 =
STORE NOT
Y1
c. Gates Implementation
Z
= X1+ cr1.X2
Cylinder Z
x1
2. All elements that are below specific height limit must be rejected.
X2
Photocell 2
X2
R1'
x2
CR1
Reject Door
(S1 = X1.X2')
HEIGHT DETECTORSYSTEM
cr1
CR1
X2
X2
Q
OR
Photo-cell X2
Y1
5. X2 is covered by all sizes. X1 is covered by elements over
5-9
Height Limit
X2
3. Reject is performed by opening a reject door - Z=1.
Z = X2.cr1'
cr1
AND
OUTPUTS
cr1
S1 = X1
X1
(Z = X1'.X2.cr1')
f. cr1 Function Simplification
cr1
e. PLC Program
R1 = X1'.X2'
S1
STORE
the defined specific heigh limit.
X1
X1
OUT
Z
Photocell 1
���������������� ����������������� ���������
R1 = B'
-
h. Selected GroupsW = A + B
5
3
RO
AD
-
4
0
State
* Only a single train crosses the junction path area, at a time.
Path Area
1
0-
1
2
4 Train leaving central area
5
cr1
L
3
5
(0-)
1
W
(R1' = B)S1 = AB
W
-
1
11
1
c. States Definitions
{3.,4,5) , (1,2)
-
CONTROL 00 01 11 10
Trains may go in two direction, but the following assumption are known :
A red light signal is placed in the junction of road and raillway. Its task is warning cars not to cross the junction.
3 Train over central area
(11)
One of the tracks is connected to common node (Ground), while the other track is splitted - within the junction path area - into 3 sections, that are physically joined, but electrically isolated from the graounded track, and from tracks outsidejunction path area.
1
3
5
00
1
Mid-section is also isolated from the other two, as seen in the drawing.
Signaling control system senses A and B signals, and turns red lights on or off, accordingly.
401/01
01
11
4
-
2
g. Merge Options
00 01 11 10
W
L
A
11
AB
2
1
W
B
When the junction path area is empty (no trains inside) all 3 sections are disconnected from common track, thusproviding "0" signal on each section.
Signal returns to "0" as soon as last waggon leaves the appropriate track section.
0
AB
AB
L
01
Position
L = A + cr1'.B
i. Merged Flow-table
* Train doesn't changes direction within the junction path area.
1
5-10
3
5
1
4
3
5 "Short" train on central area
LW
2 01/11
AB/LW
Another red light signal is placed far from the junction. Its task is warning other trains not to enter junction area.
01
{1,2,5) , (3,4)
-
1
k. Output Table
RAILWAY
B
A
{1,2,5) , (3,4)
1
00e. Primitive Flow-table
L
5
00 01 11 10
0
1
AB
1 Junction area empty2
W
2 Train enters area
11
53
11
4
1
00/00
b. Basic Block Diagram
Junction
00 01 11 10AB
W
1
11
j. States Assignment
Junction Path Area
cr1
SYSTEM
10
1
Fig. 5-15 : Traffic-Light Control System Design
3 11/11
1
3
2
When the train crosses a track section, it connects it electrically to the common track, thus changing its signal into "1".
Train must operate red light as soon as it enters "junction path area", far from the junction, and turn it off as soon aslast waggon leaves the junction, near junction.
5 10/11
f. Merge DiagramLW
a. System description
3
4
01
L
0
(11)
-
11
L
-
l. System Functions
d. Flow-diagram (primitive)
00
���������������� ����������������� ���������
B
cr1
S
OUT
b. System Functions
cr1
e. PLC I/O Tables
x1
R1 = B'
CONTROL
x2
B
h. CR1 Function Simplification
AND
c. Realys SYstem Realization
CR1
L
L = A + cr1'.B
d. Gates Implementation
OR
cr1
x2
SYSTEM
OUTPUTS
X1A
cr1
CR1
cr1
B
x1
x2
A
B
OR
(R1' = B)
AND
W
x1
cr1
Q'
W x1
x2
CR1
g. PLC Program
B
L
Y1
B
W = A + B
x2
A
OR
x2
S1 = AB
a. Basic Block Diagram
INPUTS
CR1 = (A.B + cr1)B =
x2
R
=A.B.B + cr1.B =
CR1
A
A
=A.B + cr1.B = B(a + cr1)
OUT
STORE
cr1
Y1
L
x1
B
Warning W
STORE NOT
Y1
f. PLC Circuit
AND
x1
STORE
Q
Y2
x2
5-11
X2
Y2
A
Light L
W
B
Fig. 5-16 : Realization of Fig. 5-15
Y2
A
OUT
���������������� ����������������� ���������
C
{3,4,5} {2.6} {1}
NO
600/10
1
NO
100/00
{1,5} {2.6} {3,4}
State
NO
cr3
NO
3
1
NO
0
(0)
1
311/01
00 10 11 01
2
S3 = F.C
(0)
3 Error exists and is being confirmed
l. Exitation & Output Functions
3
4
YES
YES
j. Output Table of S
5
Fail Signal
ErrorStatus
00
-
YES
0
4 Error exists and been confirmed
00
0
01
-
YES
6
cr1
-
-
-
0
h. Selected Options
1
4
0
2
10
410/01
11
ON
4-
3
00
3. If FAIL signal still exists, confirmation turns on flash light L =1. ALARM SIREN
occurs
1
(*) Non-minimal cell selction enables functionminimaztion
5
R3 = cr1.F'.C' + cr1.F'.C = cr1.F' (*)
L
-
1
FC/AL
k. Output Table of L
It must activate siren S, until operator confirmation
f. Merge Diagram
05
01
NO
3
-
ON
1 Idle StateOFF
S L
5
FC
0
-
AL
A
-
OFF
KeyStatus
0
2
FC
FC
01
0
4. After confirmation, flash is turned off a soon as fail terminates.
5
d. Primitive Flow Diagram
3
a. System Definition
(0)
c. States Definitions
L = cr3
YES
{1,5} {2.6} {3,4}
States Assignment
2 Error exists. Not yet confirmed
2
1
5 Confirmed key depressed while no error
00 10 11 01
(0)
S2 = cr1.F.C'
R2 = F'.C + F.C = C
10
i. Merged Flow Table &
-1
(Error exists and operator releases key)
ALARMSYSTEM
0
Confirmationbutton
R1 = cr2.F.C' + F.C = F(C + Ccr2)
-
S1 = F'.C'.cr2' + F'.C = F'(C + cr2')
Fig. 5-17: Alarm System Design
Position
00
S = cr2
4
g. Merge Options
OFF
3
YES
1
0
NO
OFF
cr2
00 10 11 01
YES
AlarmStatus
cr1
1. System FAIL status is exspressed by an external signal F=1.
10
0
210/10
cr3
5
6 Error terminated but not yet confirmed
FC
NO
6
5
NO
501/00
6
0
1
3
-
cr3
1
FC1
1
6
-
0
11
1
cr1
NO
b. System Block Diagram
00 10 11 01
0
(Error exists and operator presses key)
0
2. Operator confirms by pressing C buttom. This de-activates siren.
WarningStatus
NO
5-12
(0)
cr2
cr2
2
ALARM FLASH
2
(0)
3
5
F
e. Primitive Flow Table
(Error exists and operator releases key)
���������������� ����������������� ���������
C
Fig. 5-18: Realization of Fig. 5-17 by Relays System
c. Circuit Realization
cr3
L = cr3
cr1
cr
L
C
C
S2 = cr1.F.C'
cr1
R3' = cr1'+F
F
R2 = F'.C + F.C = C
F
cr2
SET
cr3
CR3
S3 = F.C
cr2
R3 = cr1.F'.C' + cr1.F'.C = cr1.F'
a. Exitation & Output Functions
cr2
F
CR
A = cr2
C
CR1
cr1
S1 = F'C'.cr2' + F'.C = F'(C + cr2')
b. Typical Relay Flip-Flop
CR2
5-13
cr2
R1 = cr2.F.C' + F.C = F(C + cr2)
C
A
F
F
(RESET)'
R1' = F'+(C'.cr2')
R2' = C'
���������������� ����������������� ���������
STORE NOT
R1' = F'+(C'.cr2')
STORE
S3 = F.C
OUT
INPUTS
x1
b. PLC I/O Tables
cr1
x1
AND NOT
5-14
S1 = F'C'.cr2' + F'.C = F'(C + cr2')
R3' = cr1'+ F
OR
x2
x1
STORE
A = cr2
y1
OUT
CR3
e. PLC Program
x2
R1 = cr2.F.C' + F.C = F(C + cr 2)
R2' = C'
x2
AND
x1
Y2
Flash L
Alarm A
R3 = cr1.F'.C' + cr1.F'.C = cr1.F'
OUT
OR
Fig. 5-19: Realization of Fig. 5-17 by PLC
CX1
L = cr3
x1
OR
CR1
cr1
AND
AND
AND
x2
OR
y1
x2 y1
Y1
x1
cr1
OUTPUTS
Y1
d. PLC Circuit
F
cr1
CR2
x1 cr1
y2
a. Exitation & Output Functions
x2
AND NOT
STORE
x1
X2
STORE
S2 = cr1.F.C'
y1x2
AND NOT
Y2
c. CR Equivalence
OR NOT
CR1
y2
x1
OR NOT
y1
x2
STORE NOT
AND NOT
x2
Y2
Y1
x1
R2 = F'.C + F.C = C
Y1
x2
Y2
y1
���������������� ����������������� ���������
R2
S1
R1
= cr
2.F.
C' +
F.C
= F
(C +
cr2
)
L
3C
R2
R3
b. C
ircu
it R
ealiz
atio
n
5-15
R3
= cr
1.F'
.C' +
cr1
.F'.C
= c
r1.F
'
F' C'F
1
Fig.
5-2
0: R
ealiz
atio
n of
Fig
. 5-1
7 by
Ele
ctro
nic
Gat
es S
yste
m
R2
= F'
.C +
F.C
= C
S R
CR
CR
'
L =
cr3
S1
= F'
C'.c
r2' +
F'.C
= F
'(C +
cr2
')
2
A
CR
2'S R
CR
CR
'
A =
cr2
S2
= cr
1.F
.C'
S3
= F.
C
S3
S R
CR
CR
'
CR
3
R1
C
CR
1
S2
a. E
xita
tion
& O
utpu
t Fun
ctio
ns
���������������� ����������������� ���������
(0)
4
A
1
cr2
B
-
600/1
6
"UP" direction
6
Fig. 5-21 : Motor Direction Detection System Design
7
(0)
401/0
00 01 11 10
AB
1
c. Contro,l System Block Diagram
811/1
-
-
210/0
cr4cr3
B
D = cr1.B + cr2.A' + cr3.B' + cr4.A
2
2
state (CRi=0).1
g. Merged Flow-table &State Assignment
5
S1 = cr2.A'B + cr2'.cr3'.A'B'
S4 = cr1.A.B + cr3.A'B
7
j. Corrected System Initialization
-
-
5 2
5
(1)
1
1
4
-
4
SYSTEM
6
501/1
710/1
5
cr11
3
A
4
6
(S1 = cr2.A'B + cr4.A'B')
3
CONTROL
O
5-16
-
cr2
2
O
90
(1)
3
00 01 11 10
AB
O
(1)
1
a. Disk Partitions ans Sensors Arrangement
5
1
D
8
1
d. Primitive Flow-diagram
h. Output Table
1
4
S2 = cr1.AB' + cr3.A.'B'
R1 = cr2.A.B' + cr4.A.B
R2 = cr 1.A'B + cr3.AB
8
3
8
A
311/0
R3 = cr2.A'.B' + cr4.A'B
0
8
At that state, Flip-flop 1 must be set, with no confilict later,
(B leads A)
6
O
O
100/0
"DOWN" direction
(0)
(1)
(0)
D
O
f. Merge Diagram
7
i. Exitation and Output Functions
7
6
7
5
R4 = cr 1.A'.B' + cr3.AB'
0
1
00 01 11 10
AB
cr3 3
ChangeDirection
that is to say, while CR2 and CR3 are not set.1
(A leads B)
1
2
S3 = cr2.A.B + cr4.A.B'
8
1
O
-
cr1
2
7
Initially, while A=B=0, and all Flip-flops are in reset
e. Primitive Flow-table
cr4
4
D
8
360
3
b. Encoder Code Waveforms for Both Directions
O
B
���������������� ����������������� ���������
B
B
S3 = A(cr2.B + cr4.B')
cr1
cr3
B
A
B
A
A
cr1
cr3
R2' = B' + (cr1' + A).(cr3' + A')
CR4
S2 = B'(cr1.A + cr3.A')
R1' = A' + (cr2' + B).(cr4' + B')
A
R3' = A + (cr2' + B).(cr4' + B')
R4' = B + (cr1' + A).(cr3' + A')
cr1
A
cr1
A
A
B D
cr2
D = cr1.B + cr2.A' + cr3.B' + cr4.A
cr2
cr3
A
B
b. Relays Circuit
CR2
cr4
A
B
B
a. Exitation and Output Functions
R4 = B'(cr1.A' + cr3.A)
Fig. 5-22: Realization of Fig. 5-21 by Relay System
cr4A
cr1
5-17
A
cr3
R3 = A'(cr2.B' + cr4.B)
cr4
cr2
cr2
CR3
S4 = B(cr1.A +cr3.A')
R1 = A(cr2.B' + cr4.B)
A
cr4
CR1
cr3
cr2
S1 = A'(cr2.B + cr2'.cr3'.B')
R2 = B(cr1.A' + cr3.A)
B
B
B
A
cr2 B
B
A
B
cr3
���������������� ����������������� ���������
STORE
X1
x2
R3' = A + (cr2' + B).(cr4' + B')
AND NOT
CR2
cr4
INPUTS
x2
x2
x2
x1
x2
cr3
x2
AND
x2
x2
d. PLC Program
Fig. 5-23: Realization of Fig. 5-21 by PLC
x2
OR NOT
AND
OR
5-18
X2 STORE NOT
x1
cr4
STORE
cr4
cr1
STORE
cr3
R4 = B'(cr1.A' + cr3.A)
STORE
OR NOT
cr2
x1
R4' = B + (cr1' + A).(cr3' + A')
OR
STORE NOT
STORE
x1
STORE
AND
CR4
STORE
x1
S4 = B(cr1.A +cr3.A')
cr4
AND
x1
x2
x1
Y1
OUT
OUT
Y1
ANDOR NOT
x1
x2
AND
CR4cr3
STORE
AND NOT
x2
cr1
cr3
a. Exitation and Output Functions
cr2
STORE NOT
OUT
STORE
cr1
x2
x2
cr3
cr3
OR
cr2
D = cr1.B + cr2.A' + cr3.B' + cr4.A
S1 = A'(cr2B + cr2'.cr3'.B')
cr1
OR
AND NOT
cr1
AND NOT
x2
OUT
x2
x2
AND
STORE NOT
STORE
x1
cr1
OR NOT
STORE
AND NOT
x1
OR
AND
STORE
OR
cr1
OR NOT
c. PLC Circuit
x2
x1
AND NOT
STORE
R2 = B(cr1.A' + cr3.A)
cr4
CR1
x1
x2
CR1
x1
AND
x1
x1
Direction D
CR3
x2
STORE
STOREcr3
x2
AND
x1
cr3
cr3
cr1
STORE NOT
cr3
x1
OR
AND
AND
A
cr2
R1 = A(cr2.B' + cr4.B)
x1
CR3
AND NOT
AND NOT
AND NOT
x2
x1
STORE
cr4
x1
cr3
AND NOT
x2cr2
STORE
R2' = B' + (cr1' + A).(cr3' + A')
cr2
cr2
OUTPUTS
OR NOT
OR
x2
x1
x1
AND
OR
x1
cr4
OR NOT
S2 = B'(cr1.A + cr3.A.')
x2
OR
STORE
AND
x1
cr3
STORE NOT
STORE NOT
x1
STOREcr4
x2
x2
OR NOT
B
OR
Y1
STORE
STORE NOT cr1
b. PLC I/O Tables
STORE
R3 = A'(cr2.B' + cr4.B)
cr2
cr2
x2
S3 = A(cr2.B + cr4.B')
x1
x1
OUT
cr2
AND
CR2
STORE
x1
R1' = A' + (cr2' + B).(cr4' + B')
STORE
cr2
STORE
STORE NOT
���������������� ����������������� ���������
5
8
5
Switch
cr1
Switch
i. System Functions
0
S2 = cr1.X1.X2
-
3
X1,X2
a. System Definition
17
2
5
6
& States Assignment
410/0
8
both inputs become 0 (X1X2=00).
-
S5 = cr4'.X1'.X2
511/1
-
Fig. 5-24 : Combination Lock System Design
Proper Sequence
-
8
R4 = X1'.X2'
f. Selected Merge Partitions2
7
3
-
T = cr4
X2
Open (T=1)
e. Merge Diagram
g. Merged Flow Table
1
cr4
10 5
-
5-19
cr2
Improper Sequence
1
2. The door is opened and closed, by entering the following sequence :
9
R2 = cr3.X1.X2' + cr5.X1'.X2
c. Primitive Flow Diagram
-
X1,X2
10
1
4
cr1
1
-
4
1
3
Combination Lock
10
S4 = cr3.X2
2
0
cr3
6-
-
1
1010/0
1
3
-
cr3
100/0
d. Primitive Flow Table
4 1
S1 = X1'.X2'
8
1
R5 = X1'.X2'
-
9
1. A security door is controlled by two input switches : X1 and X2 .
7
3
h. Output Table
911/0
610/1
5
00 01 11 10
S3 = cr2.X1.X2'
08
4
X1,X2 / T
7
X1,X2
-
0
0
T
0
801/0
210/0
X1
cr2
8
0
-
8
-
1
Close (T=0)
cr5
R3 = cr4.X1.X2 +X1'.X2'
-
5
X1,X2 = 00 , 10 , 11 , 10 , 11 ..... 00
-
16
R1 = cr2.X1.X2 + cr5.X1'.X2
1
cr5cr4
9
0
6
-
1
0
4
OpenDoor
10
-
5
0
0
b. System Block Diagram
9
00 01 11 10 T
00 01 11 10
-
8
-
1
9
2
701/1
311/0
0
0
{1,2},{3},{4},{5,6,7},{8,9,10}
1
0
-
Actually, door is opened when latest 5 inputs satisfy the sequence 00 , 10 , 11 , 10 , 11 , and closed as soon as
1
1
���������������� ����������������� ���������
CHAPTER 6
PNEUMATIC CONTROL SYSTEMS
Pneumatic Cascade Efficient Valve Implementation Emergency-Stop Modes
���������������� ����������������� ���������
+ -
CYLINDER "B"a1
A+
Start , A+,A-,A+,A-
c2b1
I
B-
+ -
+ -
A+
4
II
Fig. 6-3 : Cascade Design for Sequence Start , A+,B+,B-,A-,C+,C-
CYLINDER "A"
I
b1
B+
a2
CYLINDER "A"
CYLINDER "A"
.....
+ -
START
Start , A+ , B+ , B- , A- , C+ , C-
I
+
IV
+ -
a1
B-
START (A+) Conflicts With A- Actuation (by b1)
a1
b. Cascade Circuit
A+
Fig. 6-1 : Intuitive Design forSequence Start , A+,B+,A-,B-
I
II
+ -
Fig. 6-4 : Cascade System for Sequence Start , A+,A-,A+,A- (Cascade)
+ -
+ -
IV
c1
(IV)
a2
B-
A-
CYLINDER "A"
III
b1
+ -
a1
+ -
6-1
+
I
CYLINDER "B"
START
b2
+-
A-
3
B+ C+
+ -
CYLINDER "B"
Fig. 6-2 : Sequence Start , A+,B+,B-,A-
a2
II
+ -
2
A-
a2
b2
A++ -
II
+ +
B+
b2
1
More Conflicting States
+ -
CYLINDER "C"
+ -
+ -
+ -
Fig. 6-5: Multiple Limit Valves Replacement2
A-
C-
III
+ -
a. Cascade Groups Partitioning
1
+ -
���������������� ����������������� ���������
2
* Valves do not have return springs
II
1
1
+ -
+ -
4 GROUPS
I
a. 2-Groups Manifold Lines Configuration
Limited to control cylinders with actuation valves that satisfy the following restrictions :
c. 4-Groups Manifold Lines Configuration
II
Fig. 6-6 : Pneumatic Cascade Basic Concept
I
II
b. 3-Groups Manifold Lines Configuration
Pure pneumatic control systemSimplicity and realiability
2
* Valves are operated pneumatically (no solenoids)
Fig. 6-7 : Pneumatic Cascade Group Configurations
+ -
III
(START is also included within a group)
IV
3 GROUPS3
+-
I
6-2
* Last Group may be merged with first group, provided that groups do not conflict
+ -
III
2
4
+ -
3
1
Group Partitioning differences between pneumatic and relays cascade are :
* There is always an active group, even when not operating
2 GROUPS
���������������� ����������������� ���������
b2+ -
B+B++ -
B-
START
+ -
C+, ,
B+
2. Two sets of two limit valves.
c. Single-Cycle Cylinder Requirement
II
B-
C-
SEQUENCE GROUPS
B++ -
C+
a1
4. A START valve is also required.
B-,
+ -
I
A-
B-
b1
+ -
+ -
B-,
CYLINDER "A"
C+
A+,
C-
c1
a2
b. Sequence Groups Partioning
3. A two-input OR gate for each valve control.
CYLINDER "C"
III
C-
c2
A-
ORIGINAL SEQUENCE
,
e. System Cylinders Requirements
b2
Fig. 6-8 : Pneumatic Cascade Design Process Steps
a. Process Sequence Definition
+ -
1. cylinder actuated by valves without return springs.
B+A+,
CYLINDER "A"
2. Cylinders "A" and "C" perform single cycle (each), and require a single set of limit valves.
A-
6-3
A+
A+
START,
1. System consists of 3 cylinders, each equipped with limit-valves
,
CYLINDER "B"
CYLINDER "B"
b1
2. A set of two limit valves.
A-
B++ -
a2
1. cylinder actuated by valves without return springs.
3. Cylinder "B" performs two cycles, and requires two sets of limit-valves, and OR valves.
IV
START,
a1
+ -
B-
d. Two-Cycle Cylinder Requirement
���������������� ����������������� ���������
A-
b2
+ -
C+
B-
+ -
f. System Components
III
B-
+ -
1
B-
a1 c1
START
IV
IV
6-4
B+
START,
CYLINDER "A"
+ -
+ -
IV
4
CYLINDER "B"
a1CYLINDER "B"
c2
B+
C-+-
a2
+ -+ -
C+
C+
(Cont'd)
1
c1
I
II
2
II
B+
START
A-
a2
C-
A-
,
CYLINDER "C"
C-
b1
2
II
CYLINDER "C"
+ -
+-
A+
A+
c2
B++ -
+ - ,
I
g. Complete System
4
+ -
+ -
3
Fig. 6-8 : Pneumatic Cascade Design Process Steps
+ -
B-,
III
CYLINDER "A"
+ -
b2
III
+ -
A+,
I
b1
3
+ -
���������������� ����������������� ���������
B-
II
c1
+ -
1
d2
6-5
D+
1
b1
B-
+ -
A- D-
b1
D-
2
START
C+
I
START ,
A-
A+
A+
I
A+,
I
III
+ -
+ -
D-
CYLINDER "D"
CYLINDER "A"
START
C+
C-
d1
START,
,
A-
C-
+ -
+ -
II
a2
B-
+ -B+
D+
I
CYLINDER "B"c1
B+,
II
+ -
, B- ,C+
START,
a1
D+
+ -
CYLINDER "A"
3
, B- ,
c2
+ -
b2
,
(from semester exam July 2002)
c2
A+,
C+
B+
a2
+ -
C+
III+ -
A- ,
,
+ -A+
II
2
C+
A- ,
B+,
Fig. 6-10 : Pneumatic Cascade Example 2
B+
B-
CYLINDER "B" CYLINDER "C"
A-
A+
Fig. 6-9 : Pneumatic Cascade Example 1
a1
+ -
C-
C-B+
I
CYLINDER "C"
+ -
C-
,
b2
START ,
+ -
+ -
(from semester exam September 2002)
C-
���������������� ����������������� ���������
A
0
1
6/2
Val
ve G
ate
+-
OR
1A+B
AN
D
2
3/2
Val
ve G
ate
2
Ass
ocia
te P
rofe
ssor
+
6
A+B
'
b. T
able
s Li
st
2
T1
Fig.
6-1
1 : F
unct
ion
Tabl
es B
ackg
roun
d
2
3
T =
AC
+BC
'
B
B
A
2
com
bina
tions
. It w
as fo
und
that
a s
urpr
isin
gly
larg
e va
riet
y of
fair
ly c
ompl
ex
T =
A
A
T1
R
P
Note : Use of shuttle valves is uaually less expensive.
+
Var
ious
type
s of
dir
ectio
nal-c
ontr
ol v
alve
s ha
ve b
een
syst
emat
ical
ly a
naliz
ed
2
Eff
icie
nt U
se o
f Dir
ectio
nal-C
ontr
ol
Boo
lean
Func
tion
P
2
3
Dep
t of M
echa
nica
l Eng
inee
ring
,
2
T =
A+B
2
A
+-
+
AB
T
IMP
LIC
ATI
ON
9
3
fulle
st e
xten
t, w
hich
can
res
ult i
n co
nsid
erab
le r
educ
tion
in th
e nu
mbe
r of
val
ves.
7T
= A
+B
0
in fi
ve ta
bles
whi
ch in
clud
e 18
6 (i.
e. a
ll th
e si
gnifi
cant
) inp
ut-s
igna
l com
bina
tions
.
a. 3
/2 V
alve
, S
ingl
e O
utpu
t Fun
ctio
n
Fig.
7-1
9 : E
xam
ples
of
Com
plex
Fun
ctio
ns
Hai
fa, I
srae
l b. T
wo
Sep
arat
e O
utpu
t Fun
ctio
n,
2 In
put V
aria
bles
AN
D
Val
ves
in F
luid
-Log
ic C
ircu
its
Tech
nion
- Is
rael
Inst
itute
of T
echn
olog
y,
6IN
HIB
ITIO
N
3
AC
'+B
C
3
b. 3
/2 V
alve
Con
nect
ions
yie
ldin
g S
ingl
eO
utpu
t Fun
ctio
n
C
A
B
B
1
A
3A
ND
c. T
wo
Sep
arat
e O
utpu
t Fun
ctio
n,
3
Inpu
t Var
iabl
esN
OT
T
3
D.W
. Pes
sen
1
Fig.
6-1
3 : 3
/2 V
alve
Con
nect
ions
yi
eldi
ng S
ingl
e O
utpu
t Fun
ctio
nan
d V
alve
s P
ins
Ass
ignm
ent
INH
IBIT
ION
T =
A'
8
a. F
unct
ion
Sea
rch
Ord
er
Sev
eral
exa
mpl
es a
re p
rese
nted
, illu
stra
ting
how
the
tabl
es c
an b
e us
ed to
2A
.B'
T2
a. V
alve
s P
ins
Ass
ignm
ent
4
A
1
0
OR
3
YE
S
to d
eter
min
e th
e lo
gic
outp
ut fu
nctio
ns o
btai
ned
for
diff
eren
t in
put-
sign
al
0
T =
AB
'
C
1
4
+ Line
No.
4
P
It th
us b
ecom
es p
ossi
ble
to e
xplo
it th
e lo
gic
capa
city
of t
hese
val
ves
to th
eir
A
B
A
0
5
R
5/3
Val
ve G
ate
A Fig.
6-1
2 : F
unct
ion
Tabl
es A
rang
emen
t
Func
tion
Nam
e
Mem
AS
ME
P1
B
OR
1
5
P 5/2
Val
ve G
ate
d. T
wo
Sep
arat
e O
utpu
t Fun
ctio
n,
4/5
Inpu
t Var
iabl
es
+-
T =
AB
B
S
3/2
Val
ve F
lip-F
lop
3
B
0
A
7
3
SE
LEC
TOR
5
B
T2
4
T =
AB
+-
+-
4
...
B
A
1
impl
emen
t giv
en fl
uid-
logi
c fu
nctio
ns w
ith a
min
imum
num
ber
of v
alve
s.
e. T
wo
Sep
arat
e Fl
ip-F
lop
Out
put
Func
tion
IMP
LIC
ATI
ON
YE
SB
A
B
AC
+BC
'
T =
A+B
'
S
NO
T
5/2
Val
ve F
lip-F
lop
4
SE
LEC
TOR
T
logi
c fu
nctio
ns c
an b
e ob
tain
ed w
ith a
sin
gle
valv
e.Th
e re
sults
are
sum
mar
ised
P
6-6P2
���������������� ����������������� ���������
6-7
Fig. 6-14
���������������� ����������������� ���������
No. FUNCTION NAME BOOLEAN
FUNCTION 1 BOOLEAN FUNCTION 2
Valve 5/2 P 2 3 4
Valve 6/2 P 2 3 4 5
Valve 5/3 P1 P2 2 3 4
59 60 61 66 70 73 75 79 81 84 85 86 87 90 91 94 95 96 97 99 100 101 103 104 105 107 109 110 112 113 114 115 117 118 119 120 121 122 127 128 129 131 132 133 134 135
YES/SELECTOR ………………..…….……. NOT/SELECTOR ………………..…….……. AND/OR …………………………..…….…… AND/AND …………………………………… AND/INHIBITION ………………………….. AND/IMPLICATION ……………………….. AND/SELECTOR …………………………… AND/SELECTOR …………………………… OR/OR ……………………………………….. OR/OR ……………………………………….. OR/INHIBITION …………………………….. OR/INHIBITION …………………………….. OR/IMPLICATION ………………………….. OR/SELECTOR ……………………………… OR/SELECTOR ……………………………… OR/SELECTOR ……………………………… OR/SELECTOR ……………………………… INHIBITION/INHIBITION …………………. INHIBITION/INHIBITION ………………... INHIBITION/IIMPLICATION …………….. INHIBITION/IIMPLICATION …………….. INHIBITION/SELECTOR …………………. INHIBITION/SELECTOR …………………. IMPLICATION/IMPLICATION …………… IMPLICATION/IMPLICATION …………… IMPLICATION/SELECTOR ………………. IMPLICATION/SELECTOR ………………. SELECTOR/SELECTOR ………………….. AND+AND/AND+AND …………………... AND+AND/AND+ ………………………… AND+AND/INHIBITION ………………… AND+AND/IMPLICATION ……………… AND+INHIBITION/AND+INHIBITION … AND+INHIBITION/INHIBITION+ ……… AND+INHIBITION/OR ………………….. AND+INHIBITION/AND ……………….. AND+INHIBITION/INHIBITION ………. AND+INHIBITION/IMPLICATION ……. AND+/AND+ …………………………….. AND+/INHIBITION ……………………… AND+/IMPLICATION ………………….. INHIBITION+/INHIBITION+ …………… INHIBITION+/OR ……………………….. INHIBITION+/AND ……………………... INHIBITION+/INHIBITIOM ……………. INHIBITION+/IMPLICATION …………..
T2=C T2=C’ T1=AB T1=AC T1=AC T1=AC T2=BC T2=AC T1=B+C T1=B+C T1=B+C T1=B+C T2=A+C T1=A+C T1=A+C T1=B+C T1=B+C T1=AC’ T1=AB’C T1=AC’ T1=AB’C T1=AC’ T1=BC’ T1=A+C’ T1=A+B+C’ T2=B+C’ T2=A+C’ T2=AC+BC’ T1=AB+AC T1=AB+AC T1=AB+AC T1=AB+AC T1=AB+AC’ T1=AB+AC’ T1=AB+AC’ T1=AB+AC’ T1=AB+AC’ T1=AB+AC’ T1=A+BC T1=A+BC T1=A+BC T1=A+BC’ T1=A+BC’ T1=A+BC’ T1=A+BC’ T1=A+BC’
T1=AC+BC’ T1=AC+BC’ T2=B+C T2=BC T2=BC’ T2=B+C’ T1=AC+BC’ T1=AC+BC’ T2=A+C T2=A+C T2=AC’ T2=AC’ T1=B+C’ T2=AC+BC’ T2=AC+BC’ T2=AC+BC’ T2=AC+BC’ T2=BC’ T2=ABC’ T2=B+C’ T2=A+B’+C T2=AC+BC’ T2=AC+BC’ T2=B+C’ T2=A+B’+C T1=AC+BC’ T1=AC+BC’ T1=AC’+BC T2=AC+BC T2=A+BC T2=A’BC T2=A+B+C’ T2=AB’+AC T2=A+BC’ T2=B+C T2=BC T2=BC’ T2=B’+C T2=C+AB T2=ABC’ T2=A’+B+C T2=A+B’C T2=B+C T2=BC T2=B’C T2=B+C’
B A B C C A 0 B C A B 0 C B 1 A C 1 A B C C A B C 0 A B C A B 1 C A B A
C A B 1 0 C A B 0 1 C A 0 B 0 C A 0 B 1 C A B A 0 C 1 B 1 A C C B C A C 1 B 0 A C C B 0 A C 1 B A B C C B A B C 0 A 0 B C 0 A B 1 C 0 B A B C A 1 B 1 C A B A 1
B C 0 A 0 B C 0 A 1 B C 1 A 1 C A A B C C A A B A C A A B 0 C A A B 1 B C A 0 A B C A B A B C A B C B C A 0 B B C A B 0 B C A 0 1 A C A B C A C A B 0 A C A B 1 C B A 1 A C B A 1 B C B A B C C B A 1 0 C B A B 1
Fig 6-15 : Valve Connections Yielding 2 Separate Output Functions, 3 Variables
6-8
���������������� ����������������� ���������
6-9
Fig. 6-16
���������������� ����������������� ���������
3/2 Valve 5/2 Valve No. Output 1 Output 2 2 3 2 3 4 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186
No Input Variables T=y T1=y’ T1=y
One Input Variables
T=Ay T=Ay’ T1=Ay’ T1=Ay T1=Ay T1=y T=A+y’ T=A+y T1=A+y T1=A+y’ T1=A+y’ T1=y’ T1=Ay’ T1=A+y
Two Input Variables T1=Ay T1=A+y’ T1=Ay+By’ T1=Ay+By’ T1=Ay+By’ T1=Ay’ T1=A+y T1=Ay+By’ Three Input Variables
T1=Ay+By’
T2=y T2=y’ T2=Ay T2=Ay’ T2=y’ T2=Ay’ T2=A+y’ T2=A+y T2=y T2=A+y T2=A+y’ T2=Ay T2=By’ T2=B+y T2=By T2=B+y’ T2=Ay+By’ T2=Ay+By’ T2=By+Ay’ T2=By+Cy’
1 0 A 0 0 A A 1 1 A A B
0 1 0 1 0 1 0 A 0 A 0 A A 0 1 1 0 A 1 A 1 A 1 A A 1 0 0 1 A 0 A 1 1 A 0 A 0 B A 1 B A B 0 A B 1 0 A B 1 A B A B A A B C
Fig. 6-17 : Valve Connections Yielding Flip-Flop Output Functions
6-10
���������������� ����������������� ���������
a2
b. System Block Diagram
CONTROLSYSTEM
are to be searched in first 4 tables
R
R2
X1
F2 = X1.X2 + X2'.X3
S2=a2.y1
+-
F2 is Selector Function
* Functions that contain only external variables
X3
C. Huffman Method Solution
CONTROLSYSTEM
Y
R1
y1
e. Design Considerations
F2 = X1.X2 + X2'.X3
(Huffman Method Realization)
A- = a2
a1.y2'
Start.a1.y2'
+ -
6-11
a2
S
a2.y1
R1
A-
R2
0
a2
R2
S2
166
y1'
S1
+-
y1.y2'+y1'.y2
R
S1
2
* S1,R1,S2,R2 are Set/Reset of those flip-flops
* In current system, all functions contain internal
* Start , a1, a2 are external signals
d. System Solution Block Diagram
R2
START,A+,A-,A+,A-
a1
S1
Fig. 6-19 : Example 2
f. System Valve Circuit
1
a2.y1'
Start
A+
a. Process Sequence
a1
F1 = X1.X2'
Y'
R1=a1.y2
Start
F1 = X1.X2'
Fig. 6-18 : Example 1
R1
Y1
variables, so they are to be searched in fifth table
+-
Y
S2
r2=a2.y1'
A+
Only 101 satisfies requirements
Y'
S1=Start.a1.y2'
a1
Y2
F1 is Inhibition Function
+-
a1.y2
S
S2
S1
162
Required Functions
Search in 3-variables table
180
166
are to be searchedfirst in fifth table
* y1 ,y2 are outputs of internal flip-flops
A+ = y1.y2'+y1'.y2
S2
R1
* Function that contain internal variables (y)
A+
Found Functions 101 and 103
X2
���������������� ����������������� ���������
-
B+ = a2.y'+a1.y
5
6
1 0
0
c1
1
-b2
a2
1
b1
0
a1a1
3
0
b2
-
-
0
0
y
-
b1
1
1
1
a1b2
d. Selected Option
B-
6
--
0
5
-
00
S
b2
a2
1
b1
0
a1a1
166
6
0
R
0
0
b. Primitive Flow Table
-
a2
-
0
b2
a2
1
b1
0
a1a1
1 3
a2b1
0
180
0
0
A+ A-
START,A+,B+,B-,A-,B+,B-
0
1
b2
a2
1
b1
0
a1a1
a2b2
g. Output Functions
a1
+-
f. Exitation Functions
4
4
0
-
1
y
0
0
{1,2,6} {3,4,5}
A+
4
1
6-12
0
-
2
5
1
4
A- = b1.y
-
0
Fig. 6-20 : Solution for Sequence START,A+,B+,B-,A-,B+,B-
a2.y'+a1.y
e. Merged Flow Table &
0
-
1
0 -
0
b2
a2
1
b1
0
a1a1
3
-
A+ = Start.b1.y'
0
R = a1.b2
b1.y'
-
c. Merge Diagram
0
- -1
1
0
a1b1
-
-
(a2.b2)166
B- = b2
2
1
h. System Valve Circuit
0
S
1
1
0
-
2
5
6
-
a2
a. Process Sequence
+ -
-
-
B+ B-
-
+-
3 -
States Assignment
b1.y
b2
a2
1
b1
0
a1a1
0
3
-
S = a2.b2
(a1.b2)
b2
a2
1
b1
0
a1a1
0
0
2 -
1
-
-
0
B+
0
6
-
-
1
-
A-
0
-
R
���������������� ����������������� ���������
Fig. 6-22 : STOP-RESTART With MultipleRemote-Control STOP Buttons
No Motion
STOP
To cylinder valves
+
Combination of No-Change and Lock-Piston modes.
Stop process due to emergency condition
RESTART
Cylinder in motion must complete its stroke, andremain at rest.
CONTINUE
Fig. 6-23 : Electric STOP-RESTARTSystem With Multiple Remote-ControlSTOP Buttons
No-Change/No-Motion
CONTINUE
To cylinder valves
+
Cylinder in motion must be locked at its current position.
Safety continuation Restart (Continue)
Cylinder must be moved to its either (+) or (-) position,which been pre-definrd as "Safety Position".
C
No-Change/Lock-Piston
Fig. 6-21 : STOP-RESTART Single/Separate Buttons
a. Target & Definition
To limitvalves
CONTINUE
No-Change/Safety-Position
Lock Piston
d. No-Motion ModeElectric Actuation
RESTART
EMERGENCY STOP
CONTINUEAdd-on
Cylinder at rest must remain at rest.C
+-
c. Separate STOP/RESTART buttons
cr1
Cylinder at rest must remain at rest.
b. No-Change ModeElectric Actuation
b. Single STOP-RESTART button
Cylinder at rest must remain at rest.
STOP
Easy accessible buttons
Cylinder in motion must be disconnected from pressureand move until stopped by friction (or end stroke).
c. No-Motion ModePneumatic Actuation
Safety Position
6-13
cr1
STOP
Combination of No-Change and Safety-Position modes. Fig. 6-25 : No-Change & No-Motion Circuits
To limitvalves
RESTART
Fig. 6-24 : Emergency Stop Modes Definition
STOP
No Change
RESTART
Combination of No-Change and No-Motion modes.
CR1
STOP
STOP
STOP
a. No-Change ModePneumatic Actuation
C
C
STOP
Different modes
���������������� ����������������� ���������
+-
VA-+
+ -
Cylinder "A"
-
+-
1
+
-
VA+ = C(A+)
Fig. 6-31 : "No-Change/Safety-Position" Mode Circuit
VA-
-0
C
one valve for thewhole system
Fig. 6-27 : "Safety-Position" Mode Circuit
A-
C
air supply tocontrolcircuit
0-
C
from controlcircuit
A-
0
VA- = C(A-)+C'.a2'
01
+ -
Cylinder "A"
Cylinder "A"
-
A+
0
-
a1
C
0
Fig. 6-29 : "No-Change/No-Motion" Mode Circuit
+-
1
VA-
C
+ -
from controlcircuit
1
A-
continuecycle
Fig. 6-28 : "Safety-Position" Mode Circuit
A- +-
VA+
C
a2
-
0
0
6-14
0--+
+
(Applied to an Individual Cylinder)
-
To all shuttle valves
one valvepercylinder
a2'
A+
+ -
Cylinder "A"
1 1
C
Fig. 6-26 : "Lock-Piston" Mode Circuit
A+
a1
a2
A+
C
Fig. 6-30 : Karnaugh Maps for"No-Change/Safety-Position"Circuit
+ -
+
-+
+-
C'
1
a1+a2
+
0
VA+
0
-
A+
a1
a2
A-
C
VA+=A+
Cylinder "A"
1
A+
(Applied to Entire System)
0
A-
C
���������������� ����������������� ���������
CHAPTER �
HARDWARE PROGRAMMERS
Drum Programmer Programmable Counter 1/n Programmable Counter 2/n
���������������� ����������������� ���������
Fig. 7-1 :
7-1
���������������� ����������������� ���������
1
E+5
Action
A+
D+
A+
B+
72
D+
7
4
7-2
E+
6
B+
6
A-
F+
A+
4
........
F+
3
D+
B-
B+
3
E+
4
1
d. Station 1 Positionb. Sequence Flow
B+
1
2
E+
C-
Station
F+
Station 1
6
A+
A+
Step 2
E-
4
B+
4
c. Drum arrangement
C+
5
B+A+
...
3
C+
7
e. Station 2 Position
A+
A+
6
Fig. 7-2 : Drum Programmer Action
E+
........
C+
C+
3
C+
D+
D+
C+
F+
5
f. Station 3 Position
3
2
5
C+
Station 2
C+
5
F+
���������������� ����������������� ���������
&
1
5 c2
X
8
4
Xn-1
X
3
D-
Y
b2
Cylinders A,B,C Types
>1
IX
7-3
Z1
a2
6d2
MATRIX BOARDS
Z1
1
A-
X
4
X
VIII
F+,
c1
12
Z3 Z4
4
b. Without Sneak Path
Start
B-
D+
D-
2
B
X
GoHome
A-, E-
VI
C-,
>1
a1
, A-
b1
/
7
I
+ -
Z4
2
c1
9
3
A+
13
>1
5
X
F+,
Z3
X
Cylinders D,E,F Types
B+
b2
D
2
---
C+
C+,E
Fig. 7-4 : Boards
Xn
Z2
a1
D
B-
E-
X6
NotUsed
C+
PROGRAMMABLE COUNTERS (SEQUENCERS)
Y+
6
2
a. With Sneak Path
Fig. 7-8 : Programmable Counter Circuit fora Sequence, Implenting Actuating ValvesWithout Return Springs (1/n)
X
IV
X4
>1
n
7
11
F+
a. Patch Board
+ -
B+,
C-
E+
2 4
NotUsed
DRUM PROGRAMMER (STEPPING SWITCHED)
In
>1
a2
Motor
VII
D-
y1
1
Start
6
1 3
1
X
f1
C+
II
X+
B+
Y-
4
X3
F-
b2
2
Z5 Z2
n+1
10
4
Step
d1 e1 f1
Out
, A+
Z6
1
a2
3
X
B-
a1
5
6
10
X
Zn
4 2
F+
X
C
3
B+
a1
START
8
X
x1
3
F-
, A+,
A
c2
B+b1
B+,
X
15-24
&
y2
---
a2
14
START
a2
X
9
6
START
7
D
1
X
Fig. 7-5 : Matrix Board
A+
D+
V
&X1
8
C-
Connected to
5
F-X
E+
F+
B
Fig. 7-6 : Schematic Representation ofProgrammable Counter
Fig. 7-7 : Programmable Counter WithSingle-Cycle START mode
, A+,
a1
3
X
F+
A
X2 X4
3
/
7
Xn
C+
f2
X
D+,b. Matrix Board
X
c2
SignaltoAdvance
, A- ,
e2 f2F+
1
2
c1
A+
Fig. 7-3 : Drum Programmer Solution
X3
5
C
1
DesiredEvent
F-,
2
Connectedto Module1
A+
, F-,
C
4
b1
f1
Connectedto Module 1
C-
E+
StartE-
X5
Z5
f2
Switches
B
5
X
X1
B-,
A3
C+
A-
NotUsed
F-
4
X2
III
x2
F-
Zn
n
NotUsed
Fig. 7-9 : Programmable Counter Circuit forSequence of Fig 7-8, While Actuating ValvesHave Return Springs (1/n)
8
���������������� ����������������� ���������
Z3
X2
RESETSET
y y'
X1
+-
Z4
X1
0 0 0 1 1
2Xi
0 0 0 1 0
Si+1
Z2
X3
RESETSET
y y'
step
+-
X2
y1
1 0 0 0 1
X4
a. actual General Cell
Zi
Si
step
RESETSET
y y'
Z4
From Zi-1
c. Equivalent General Cell
&&
+-
RESETSET
y y'
y4
&
Z2
+-
&
Z1 Z3
Zi
e. Counter cycle states
2
5
X3
0 0 0 0 1
To Zi+1 SET
1 0 0 0 0
3
d. Equivalent Counter Configuration
Xi
y3
+-
&
X2
0 0 1 0 0
+-
RESETSET
y y'
3
From Zi+1
e. Counter cycle states
From Zi-1
X4y1
RESETSET
y y'
Z3
y2
RESETSET
y y'
0 1 0 0 0
Z3
1
From Zi+1
+-
1
y2
Z4
&
Z1
Si
&
Xi
d. Equivalent Counter Configuration
+-
Fig. 7-11 : Programmer Based on 2/n Code
0 1 1 0 0
Zi
X3
Si+1Si
a. Actual General Cell
X4
RESETSET
y y'
&
X2 X4
c. Equivalent General Cell
&
X3
7-4
4
Fig. 7-10 : Programmer Based on 1/n Code
+-
Zi
To Zi-1 RESET
y1 y2 y3 y4 y5
Z2
+-
Ri
y3
+-
b. Actual Counter Configuration
b. Actual Counter Configuration
RESETSET
y y'
+-
Z1
Z1
4
To Zi+1 SET
1 1 0 0 0
Ri
RESETSET
y y'
Z4
y4
&
X1
y1 y2 y3 y4 y5
0 0 1 1 0
To Zi-1 RESET
+-
Xi
+-
Z2
5
X1
+-
���������������� ����������������� ���������
(D-)
Sta
rt
A+
b2
(With
Ret
urn
Spr
ings
)
a. S
eque
nce
1
(f)
b. 1
/n P
rog.
ram
mab
le C
ount
er C
ircu
it
a2
(B+)
(C+)
a2 &
1
4
&
B+
(B+)
D+
,
(B+)
- - -
-
a1
C+
6
5
(C-)
B+
Fig.
7-1
2 : P
rogr
amm
able
Cou
nter
Exa
mpl
e 1
,B-
C+
B+
(B+)
8a1
2
>1
a1
B+
(c)
>1
7
A+
C+
(a)
(B-)
5
3
A+
,
D+
Pul
se b
ut n
opr
oble
ms
7
b1
5
67
c2
c. 2
/n P
rogr
amm
able
Cou
nter
Cir
cuit
6
c1B
+
A+
A+
FLIP-FLOP
(B-)
(C-)
b2
>1
, C+
,
7
D+
b2
>1
FLIP-FLOP
2
D+
C+
(B+)
(B+)
b2
2
B+
B+
,
D-
,
C+
3
c1
d2
FLIP-FLOP
6a1
(With
Ret
urn
Spr
ings
)
star
t
a2
5
a1
STA
RT
, A+
, A- ,
B+
, C+
, B- .
C-
a2
SET
d1
B+
C+
,
b2
c2
b2
SET
B-
OR
SR
Q
FLIP-FLOP
(d)
D+
C+
c1
(C+)
(D-)
(With
Ret
urn
Spr
ings
)
(C-)
3
RESET
3
A-
,
B+
C-
,
(b)
b1
b2
b2
Fig.
7-1
4 : 2
/n -
Diff
eren
t Sta
bilit
y C
ases
b2
(A-)
C+
Sta
rt
- - -
-
a1
Fig.
7-1
3 : P
rogr
amm
able
Cou
nter
Exa
mpl
e 2
B+
RESET
7-5
(Bot
h B
and
C r
equi
re fl
ip-f
lops
)(e
)
(B-)
C+
star
tc1
a1
(B+)
(B+)
A-,
B+
c2
(A-)
b1
a. S
eque
nce
a1
B-
STA
RT
,
1
d1
8
A+
c2
C-
,
b. 1
/n P
rog.
Cou
nter
Cir
cuit
RESET
c1
c. 2
/n P
rogr
amm
able
Cou
nter
Cir
cuit
d2
B+
4c2
1
B-
B+
&
C+
2
4
OR
(C+)
c2
A-
SET
(B+)
A+
4
>1
A+
a2b1
Sta
rt
���������������� ����������������� ���������
Fig. 7-17 : 1/n Programmer for Program With Skip Steps Option
1
m
ZB2
P'
ABm
B1
k
ZA1
---
P'
&
ZBm
ZD2
Ck
>1
2 m
ZAn
ZB2
2
3
ZC1
7-6
B2
2
2
---
ZA1 ZA2ZD1
C21
Fig. 7-16 : 1/n Programmer for Two Alternative Parallel Paths (Parallel)
2
2
B3
ZB1
ZB2
>1 &
k
ZC2
An
&
Repeat for P=0
An
ZC2
B2
1
ZC2
2
ZC2
1
&
---
---
ABm
ZC1
Ck
k
An
B1
p
B3
m
1
ZC1
C2
---
&2
C1
2
B1
ZA2
A2
ZAn
Fig. 7-15 : 1/n Programmer fot Two Simultaneous Parallel Paths
C1
ZA1
1
ACk
A2
---
---
---
ACk
ZB1
D2
ZAn
2 m
1
---
Bm
ZB2
1
ZA2
&
2
ZDp
Bm
---
ZB1
Skip for P=0
2
C2
---
P'
CkA1
ZDp
ZA2
Dp
1
Bm
B2
ZD2
2
Ck
2
ZBm
>1
2
P
ZC1
1
2
A2
ZB2
D1
3
B1
D2
A1
Bm
&
ZCk
ZCk
P
---
---
3
3
ZD1
An
1
Path C for P=0
k
Dp
1
1
A1
A1
1
B2
D1
A2
p
---
Fig. 7-18 : 1/n Programmer for Program With Repeated Steps Option
ZB2
C2
Path B for P=1
ZA1
ZAn
ZB1
P
���������������� ����������������� ���������
met
hod
Mor
e th
an
met
hod
used
?
or H
uffm
an
used
?
Are
YE
Sca
scad
e
NO
tabl
eP
neum
atic
casc
ade
Pro
gram
mab
le
Are
7-7
met
hod
YE
S
NO
Are
coun
ter
elem
ent e
conp
my?
met
hod
repe
ated
NO
4 or
5
Pro
gram
mab
le
YE
S
Are
ther
e
NO
YE
SH
uffm
an
repe
ated
valv
es
rela
ys
Pne
umat
ic
even
ts?
Flow
-Tab
le
used
?
coun
ter
YE
S
4 or
5
Fig.
7-1
9 : F
low
Cha
rt fo
r S
elec
ting
Seq
uenc
e-C
ontr
ol S
yste
m D
esig
n M
etho
d
met
hod
YE
S
YE
S
met
hod
NO
Mor
e th
an
sim
plic
ity m
ore
Are
ther
e
Flow
-Tab
le
NO
cylin
ders
?
met
hod
Is d
esig
n YE
S
Is d
esig
n
Rel
ay
YE
S
NO
requ
este
d?fle
xibi
lity
impo
rtan
t tha
n
casc
ade
NO
Ope
ratio
n-
Pro
gram
mab
le
valv
es
even
ts?
cylin
ders
?
coun
ter
NO
���������������� ����������������� ���������
CHAPTER 8
MISCELLANEOUS SWITCHING ELEMENTS AND SYSTEMS
Timers Modes Timers Construction Pulse Shapers Flip-Flop Types Up/Down Counters Shift Registers Implementation Schmitt Trigger Binary Codes Error Detection Encoders
���������������� ����������������� ���������
Con
trol
f. D
elay
ed In
terv
al
(Out
put)
'
A y1 y1
Fig.
8-7
: S
eque
nce
Cha
rt fo
r a
Pul
se S
hape
r (M
onos
tabl
e, O
ne-S
hot)
a. O
n-D
elay
Con
trol
0
Del
ayA
Fig.
8-1
: S
eque
nce
Cha
rt o
f Com
mon
Tim
er M
odes
Con
trol
Sig
nal
0
(Out
put)
'
8-1
Fig.
8-3
: P
neum
atic
"O
ff-D
elay
" Ti
mer
Out
put
irre
leva
nt
Con
trol
Sig
nal
Con
trol
Inpu
t
Out
put
y2
0
Del
ay B
Con
trol
Sig
nal
Y1
Out
put
Out
put
A+
Del
ay
Out
put
Vol
ume
+-
+
-
Out
put
Out
put
Fig.
8-8
: R
elay
Pul
se S
hape
r
Con
trol
Sig
nal
8-1
Out
put
c. In
terv
al
Out
put
Con
trol
Sig
nal
Vol
ume
1
Out
put
Con
trol
e. O
n-D
elay
O
ff-D
elay
Con
trol
Fig.
8-9
: P
neum
atic
Pul
se S
hape
r
Che
ck V
alve
A-
Out
put
Y2
1
Out
put
Inpu
t
+-
Del
ay B
+
Vol
ume
Out
put
b. P
ulse
Str
etch
ing
Fig.
8-4
: P
neum
atic
"O
n-D
elay
Off
-Del
ay"
Tim
er
+
+
irre
leva
nt
Out
put
d. M
onito
red
Inte
rval
h. R
epea
t Cyc
le
Fig.
8-5
: P
neum
atic
"O
n-D
elay
" Ti
mer
Usi
ng B
ias
Pre
ssur
e
Bia
s P
ress
ure
(fro
m p
ress
ure
regu
lato
r)
Con
trol
Nee
dle
Val
ve
Con
trol
Out
put
Fig.
8-6
: Im
plem
ent "
On-
Del
ay"
Tim
er fo
r A
utom
atic
Cyl
inde
r R
etra
ctio
n (In
terv
al D
elay
)
Vol
ume
+
Out
put
Con
trol
Del
ay
Del
ayD
elay
AS
TAR
T
1
g. M
onito
red
Del
ayed
Inte
rval
+
a. P
ulse
Sho
reni
ng
Del
ayD
elay
B
STA
RT
Del
ayA
1 0
Vol
ume
b. O
ff-D
elay
Fig.
8-2
: P
neum
atic
"O
n-D
elay
" Ti
mer
Vol
ume
(Out
put)
'
���������������� ����������������� ���������
1
23
0 0 1 0
S (SET)
Q
AND
S (SET)
S
Q'
R
R (RESET)
Q'
T
CP
0 0 0 0
1
23
0 0 1 1
R
Q'
Q'
Q'
1
23
CLOCK
a. Delay Flip-Flop (D)
D
R
Q0
0 0 0 1
T
0 1 0 0
DOWN
D
AND
Fig. 8-12 : T Flip-Flop Implementation - Counters
FF3
Q'
c. Shift Registerr Based on D Flip-Flops
Q'
Q'
4
56
Q'
Q'
a. "UP" Counter
CP
Q1
Q
d. "UP/DOWN" Selector
b. "UP" Counter Timing Waveforms
0 1 0 1
R (RESET)
S
Q
Q1
AND
R (Reset)
S (Set)
INHIB
S
Q
Q
Q
0 1 1 0
.
.
.
.
Q'
Q
NAND
R
Q'
R (Reset)
D
CP
NAND
T
OUT
UP
D
Q2
S
1 0 0 0
Q3 :Q2 :Q1 :Q0 :
Q3
TQ'
S
CP
Clock
AND
T
Q2
D
AND
Fig. 8-11 : Toggle Flip-Flop (T)
AND
CP
Q'
.
.
.
.
NOR
Q'CLOCK
4
56
Q
T
Q
Q
CP
FF3
CPCP
Q
4
56
.
.
.
.
FF2
1 0 0 1
Q0
T
Q
NAND
Q
Q
Q'
Q'
Q
T
Q'
Q
(Flip-Flops are Triggered on High-to-Low Transition at T)
NOR
1 0 1 0
Q'
OR
CP
c. Short Symbol (Asynchronous FF)
INHIB
Q
D
Q
Q3
D
c. "DOWN" Counter
Q'
4
56
T
1 0 1 1
Q
Q
CP
S (Set)
Q
T
FF1
R
Q0
CLOCK
Fig. 8-10 : Basic Set-Reset Flip-Flop (SR)
NOR
Q3
R
CP
1 1 0 0
S
R
Q'
b. Master-Slave Type
Q2
Q
Q
8-2
R
Q
Fig. 8-13 : D Flip-Flop Implementation - Shift Register
b. Logic Circuit (Active LOW)
Clock
IN
SQ'
Q
T
a. Logic Circuit (Active HIGH)
1 1 0 1 RESET
Q
Q'
T
FF0
Q'T
Q
Q'
Q'
d. Clocked SR Flip-Flop (Synchronous)
AND
Q'
D
1 1 1 0
S
1
23
1
23
0 0 0 0
Q'
FF1
SELECTOR
Q Q
Q1
Q'
e. Clocked SR Flip-Flop (Synchronous)
Q'
a. Basic Logic Circuit
D
0 1 1 1
Q'
0 0 0 1
FF0
Q
f. Short Symbol of Clocked Flip-flop
AND
FF2
Q
b. Master-Slave Type
1 1 1 1
Q'
Q
���������������� ����������������� ���������
Q0
Q
Q
Q0
T
0010 = 2
FF2
FF1
FF0
FF1
Q
Q
Q0
FF2
0
FF3
0 0000 = 0
0
T
T
FF2
FF0
T
T
Q
Q
T
T
T
T CLOCK
Q0
Q'
Q
Q
CLOCK
FF1
CLOCK
Q'
FF2
FF3
1
Q0
Q
0011 = 3
Q2
Q
Q
Q3
T
Q CLOCK
CLOCK
0100 = 4
Q0
0
FF0
Q'
CLOCK
Q
T
Q0
Fig. 8-14 : Up-Counter Hardware Sequence
FF1
Q1
Q0
0
T
T
Q
T
T
Q
0
Q
FF3
0
Q
1
Q0
T
0
FF3
T
Q
FF3
Q
Q'
T
FF2
0001 = 1
FF0
0
T
Q0
FF1
Q0
Q0
FF0
8-3
a. "UP" Counter
Q
0
Q
FF3
T
Q0
FF2
0
FF1
T
T
0
Q0
FF0
T
1
Q0
0
1
Q
Q0
Q0
Q0
T
Q
Q0
10
Q0
Q0
Q
0
���������������� ����������������� ���������
Q'
Q3
FF0
T
Q'
(1)
FF0
FF0
FF0
Q'
Q'
c. "DOWN" Counter
Q'
(1)
Q2
Q2
Q1
Q0
FF0
Q
Q3
(1)
T
FF0
Q'
FF0
T
Q
(0)
1101 = 13
Q
FF0
Q
(1)
T
Q
(0)
Q2
Q'
1
Q'
(0)
(1)
T
TQ'
Q1
FF0
Q'
(0) (1)
Q
Q'
FF0
T
1
(0)
8-4
Q'
Q3
Q
Q0
(1)
T
Q
T
Q
0
Q1
CLOCK
1
T
T
T
Q'
Q0
FF0
Q
Q'
(0)
Q'
Q'
Fig. 8-15 : Down-Counter Hardware Sequence
T
(0)
1
T
FF0
T
FF0
Q3
(1)
Q
1
FF0
0
Q
(0)
T
(1)
(0)
0
Q'
Q'
1
Q'
CLOCK
1
Q
T
FF0
Q0
1
Q2
Q
T
Q'
FF1
Q
Q
Q
FF0Q
FF0
0
0
Q0
T
Q'
Q
Q
FF0
Q1
CLOCK
0
Q
1
Q'
T
0
(0)
1
FF0
0000 = 0
0000 = 15
Q'
Q2
FF3
(1)
FF0
1
Q0
0000 = 15
Q1
Q'
CLOCKQ
0
T
Q3
1
Q1
(0)
T
Q
FF2
CLOCK
FF0
Q3 Q2
T
Q
T
1110 = 14
CLOCK
���������������� ����������������� ���������
6
Load
Fig. 8-16 : 10 Stages Shift Registers
Parallel Input
2
0
1
1
B-
10
1
0
1
8
0
1
0
START
0
0
b. Shift Register (Cyclic) - Parallel In,Serial Out
D+
0
Load
0
C+
1
d. Shift Register (Cyclic) - Serial/Parallel In,Serial Out
2
0
B+
410
0
1
0
1
0
A+B-
Serial Ouput
Shift
0
1
Serial Ouput
D+C-
11
Load
0
5
1
1
0
1
Shift
0
Fig. 8-17 : Implementation of Multi Track Shift Registerfor Operating Synchronous Sequence
c. Shift Register (Cyclic) - Parallel In,Serial/Parralel Out
7
0
1
0
1
1
1
8
1
A-
0
Shift
D-
Serial Input
9
0
1
8-5
1
Steps
1
InputControl
a. 10-Step Synchronous Sequence Definition
Serial Input
A+
0
Parallel Output
1
A+1
0
0
0
0
4
0
0
Shift
0
1
0
0
Shift
1
5
1
Steps
B+
Serial Ouput0
1
C+
1
1
Outputs
00
0
1
0
3
0
7
A+
0
1
0
A+
Selector
1
0
1
B+
3 9
0
6
1
a. Shift Register - Serial In,Serial Out
0
1
Serial Ouput
0
1
A-
1
b. Shift Register With Four Parallel Tracks Implementation
0
Parallel Input
1
1
C+
0
0
0
0
���������������� ����������������� ���������
Fig. 8-20: Standard/Schmitt Response to Fuzzy Waveform
In
b. Correct Input Signal
InputVoltage Out
Fig. 8-18 : Response of Standard Gate
a. Typical Gate I/O
High-to-Low Threshold
Low-to-High Threshold
HI
In
OutputVoltage
c. Noisy Input Signal
Out
a. Electronic Schmitt Gate
In
In
ElectronicStandardGate
8-6
b. Response of Schmitt Trigger Gate
a. Hysteresis I/O Graph
High-to-Low Threshold
Out
HI (3.4V)
Low-to-High Threshold
0.95V
In
In
High-to-Low Threshold
b. Typical Response
ElectronicSchmittGate
Out
Out
1.8V
Out
Fig. 8-19: Schmitt-Trigger Response
Low-to-High Threshold
LO (0.3V)
LO
���������������� ����������������� ���������
(b)
0 0 0 0
Fig. 8-21: Comparison BetweenNatural-Binary and Reflected-Cyclic Code
0 1 0 0
0
11
1 1 0 1
1 0 0 1
1 1 1 1
A
B
C
D
1 1 0
0 0 1 1
1 0 1 1
Fig. 8-24: Construction of "Reflected" Cyclic Code
1 1 0 1
1 1 1 1
1 1 0 0
0 1 1 0
0 1 1 1
0 0 0
C
A
B
8-7
1 0 1 1
0 1 0 0
2
1413
(c)
0 0 1 1
ReflectedCyclicCode
1 0 1 1
1
1 0 0 1
0 0 0 00
9
0 1 0 1
10
6
1 0 0
0 0 1 0
1 0 0 0
0 0 0 0
7
1 0 0 1
C
A
B
0 1 0 1
DecimalValue
0
0 1 0
(d)
5
1 0 1 0
0 1 1 1
1 1 0 0
0 0 1 0
0 1 1 0
1 1 1 0
Fig. 8-23: Reflected CyclicCode for 6 Numbers
0 1 1 1
1 1 0 1
8
1
12
1 0 1
0 0 1 1
0 1 1 0
1 1 0 0
1 1 1 0
0 0 0 1
0 0 1
1 0 1 0
1 0 1 0
C
A
B
(a)
1 1 1 0
0 0 0 1
3
1 1 1 1
1 0 0 0
0 1 0 0
0 1 1 1
Fig. 8-22: Use of Karnaugh Map to Obtain Cyclic Codes
15
0 1 1 0
1 0 0 0
NaturalBinaryCode
0 0 1 0
1
40 1 0 1
0 0 0 1
���������������� ����������������� ���������
1
1
0
2
12
1
1
1
0
1
1
0
15
1
1
0
1
0
13
0
1
0 0
1
1
0
1
1
0
1
2
1
0
1
1
3
Number
4
1
1
5
1
0
7
0
0
0 0
1
0
0
1
7
0
0
1
0
11
0
1
0
0
4Number
1
0
0
0
0 0
0
1
1
a. Natural Code
0
1
0
0
0
1
0
1
0
14
6
0
0
0
3
1
0
1
0
1
13
0
1
00
1
0
0
0
0
0
1
4
1
1
1
0
1
Weight
0
1
0
1
(Even Parity)
1
0
9
1
1
0
0
Fig. 8-26: Truth Tables for BCD Code
1
1
0
1
9
15
7
7
1
8-8
Weight
0
1
1
5
0
8
1
0
P = Parity Bit
0
110
Number
1
0
0
0
Number
0
0
1
8
1
12
8
1
0
1
8
0
0
1
2
1
1
0
50
0
Weight
P
0
0
0
2
1
9
0
1
1
0
11
1
0
8 2
1
0
0
0
0
0
0
9
1
6
14 1
0
0
0
1
8
0
3
1
0
1
6
2
1
1
0
0
0
1
1
1
2
1
1
0
1
0
1
3
0
P
0
1
1
4
1
1
1
1
1
0
1
1
0
0
0
0
4
1
4
1
Fig. 8-25: Truth Tables for Natural Code
8
5
1
1
0
0
0
0
b. 2-out-of-5 BCD Code
1
2
1
0
1
1
0
(With Even Parity bit)
0
0
1
1
0
(No Parity)b. Natural Code With Binary Parity Bit
6
1
1
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
0
0
4
0
10
0
1
a. Weighted BCD Code
0
1
P
0
0
0
1
1
1
0
0
0
0
00
1
1
1
0
7
0
1
0
1
Weight
1
4
1
���������������� ����������������� ���������
Send Data
Parity Bit = "1"
Reaceive Data
Even ?
Add Parity Bit to Data
Count Number of "1"s
8-9
Save Data
Parity Bit = "0"
(Total n Bits)
yes
StatusReturn "OK"
Correct Single Error &Detect 2 Errors
no
Return "Error"
c. Multiple Parity Bits
Fig 8-27 : Common Modes
Fig 8-28: Parity Check Process
Data Output Register
Count Number of "1"s
a. Natural Code
Handle Error
Delete Parity Biy
(Total n+1 Bits)
Error Detection Not Available
yes
Even ?no
Detect ODD numbers of Errors
Confirmation
(Total n Bits)
b. Single Parity Bit
(Total n+1 Bits)
���������������� ����������������� ���������
Absolute Coordinates
110
c. Incremental Encoder Output
101
8-10
111
000
Fig. 8-31:Single Output Incremental Encoder
WRONG
001
F
001
110
B
100 OK
D
D
110
b. Encoder Photo-Cells
c. Sections Border Problem
010
Fig. 8-29: Binary 8-Sections Encoder
G
H
G
b. Encoder Photo-Cells
111
F
c. Border Problem Solved
No Sense for Direction
F
E
E
Fig. 8-30: Typical 8-Sections Encoder
A000
011
WRONG
100
OK
C
111
a. Encoder Plate
101
100
G
a. Encoder Plate
010
B G
101
F
H
b. Encoder Photo-Cells
Absolute Coordinates
011
110
100
a. Encoder Plate
OK
E
H
C
OK
A
���������������� ����������������� ���������
that is to say, while CR1 and CR2 are not set.
Servo Motor
(1)
8
100/0
6
0
3
R3 = CR2.A'.B' + CR4.A'B
0
8
S2 = CR1.AB' + CR3.A.'B'
710/1
Fig. 8-33: Motor Direction Detection System Design (Copy of 6-4)
O
CONTROL
(1)
CR2
90
00 01 11 10
AB
CR1
2
R4 = CR1.A'.B' + CR3.AB'
CR3
S3 = CR2.A.B + CR4.A.B'
501/1
2
CR1
A
Load
7
(1)
0
CR1
5
Program
1
7
i. Corrected System Initialization
1
S4 = CR1.A.B + CR3.A'B
2
O
StepMotor
(0)
CR4
1
3
b. Encoder Code Waveforms for Both Directions
ControlLogic
4
h. Exitation and Output Functions
6
1
O
6
Tachometer
8
1
(0)
CR3 3
-
600/1
a. Control System Block Diagram
A
311/0
Direction
1
O3
3
SYSTEM
Load
210/0
(0)
f. Merged Flow-Table States Transitions
5
D
d. Merge Diagram
"Clock" direction
b. Primitive Flow-diagram
5
O
B
Encoder
Pulses
8
7
Fig. 8-35: Block Diagram of an Open-Loop NC System (One Control Axis)
-
00 01 11 10
AB
811/1
1
(0)
1
-
a. Plate Sensors Arrangement
or
0
O
4
00 01 11 10
AB
5
4
5
1
"Counterclock" direction
7
01
2
8
1
Servo Valve
2
7
6
7
O
1
CR2
1
01
5
4
"Clock" direction
Position
CR4
1
7
6
Program
ChangeDirection
11
-
CR3
8-11
00 01 11 10
AB
"Counterclock" direction
8 7
4
1
Binary Signal
S1 = A'B'.CR2'.CR3'
8
8
O
401/0 CR4
10
c. Primitive Flow-table
10
Error
CR2
-
5
1
2
At that state, Flip-flop 1 must be set, with no confilict later,
DigitalComparator
6
11
g. Output Table
A
5
c. Cells A and B sequences
Amplifier
3
3
D = CR1.B + CR2.A' + CR3.B' + CR4.A
Fig. 8-34: Simplified Block Diagram of a Closed Loop NC System (One Control Axis)
2
1
360
1
6
D
B
00
Fig. 8-32: Two Output Incremental Encoder
4
3
4
0
2
R1 = CR2.A.B' + CR4.A.B
4
-
D/AConverter
e. Merged Flow-table & State Assignment
B
00
S1 = CR4.A.B' + CR2.A'B'
Initially, A=B=0 and all Flip-flops are in reset state (CRi=0).
(1)
1
D
1
-
1
R2 = CR1.A'B + CR3.AB
0
6
-
���������������� ����������������� ���������
CHAPTER �
ITERATIVE SYSTEMS
Iterative Binary Adder Iterative Design Samples Binary Numbers Comparator Cyclic Codes Converters
���������������� ����������������� ���������
Ci
1
1
0
1
0
0
C1
Xi
0
Z1
4
56
0
1
C=1
Cn-1
1
0
0
1
c. Karnaugh Map Methose Limitation
FA
0
01/1
Yi
1
1
1
0
0
FA
0
X0
+ X1.X0'Y1' + X1'Y1.Y0' + X1'X0'Y1
1
1
Yi
Si
0
X1
1
1 0 0 0 1
1
0
b. FA Truth Table Fig. 9-3 : Iterative Binary Adder Design
1
0
1
Z2 = X1.Y1 + X1.X0.Y0 + X0.Y1.Y0
FA
0
1
C0=0
0
1
Z0
0
a. General Cell (FA) Flow Chart
b. Sum Output Minimized Functions
Ci+1 = Xi.Yi+ Ci (Xi + Yi)
1
0
00
0
Ci+1
0
0
Yn-1
Xi,Yi/Si
Y1
1
1
0
Z1 = X1'X0.Y1'Y0 + X1.X0.Y1.Y0 + X1.Y1'Y0' +
1
Y1
S0
0
1
1
Ci
1
Cn
0
Xn-1
0
1
1
0
4
56
FA
0
01/0
1
Y0Xn
1
23
1
Z0 = X0.Y0' + X0'Y0
0
00
1
23
Si
c. FA Logic Circuit
1
0
10/1
1
Cn+1
1
0
Fig. 9-1 : Adder for 2-Bit Numbers
X0
Yi
0
1
1
a. Truth Table
Ci+1
Y0
1 0 1 1 0
1
4
56
S1
10/0
0
0 1 1 1 0
0 0
1
* 32-Bit Numbers Adder requires 64-Variable Map
11/1
1 1 1 1 1
1
0
1
1
1
1
0 0 0 0 0
1
1
C2
0
00/1
9-1
XiYn
0
0
0
0
* Karnaugh Map Metode Is Limited to 4-Bit Numbers
0 0 1 0 1
1
C=0
1
1 1 0 1 0
0
0
0 1 0 0 1
0
0
1
23
Z2
* 4-Bit Numbers Adder requires 8-Variable Map
Sn-1
Xi
1
Si
1 1
11
1
0
0
00/0
Si = (XI) xor (Yi) xor (Ci)
0
1
0
X1
1
0
0
0
Fig. 9-2 : Iterative Adder Block Diagram
0
0
11/0
Ci+1
Sn
FA
Ci
1
1
0* 3-Bit Numbers Adder requires 6-Variable Map
���������������� ����������������� ���������
Pn+1
a. Requirements Definition
Di-1
Ai
1
1
f. General Cell Function
-
Xi
1
00-
Design a circuit that checks vectors and announces
-
0
9-2
0
0
B0
Di =Ci-1.Xi +Di-1
Cn
1
Di0
1
g. General Cell Logic Circuit
e. General Cell Truth Table1
N=2
It produces a single output line P, where :
0
-
-
Fig. 9-4: Iterative Parity Checker
(11000000, 00101000, 010000001 etc).
X (Vector)
X (Vector)
-Xi
1
P=0 denotes even parity
Bi
N>2
vector, is odd or even.
C1
11
D
-
-0
Ci
-
P1
Xn
P=1 denotes odd parity
B C
-
c. Iterative Block Diagram
"0"
0
Pi
e. General Cell Truth Table
0
1
0
Bi-1
1
1
An+1
N=1
Cn+1
DESIGN OF A PARITY CHECKER
Pi
exactly two "1"'s, and all other bits are "0".
Z
1
An
-
0
- 1
Pi-1
Ai-1
-
0
0
Pi-1
0
0
N=0
A
Bi-1
1
A0
-
Ai
1
X0
0
Pi = Pi-1.Xi' + Pi-1'.Xi = Pi-1 xor X
Pn
-
b. Simplified Block Diagram
Fig. 9-5 : Iterative 2-Out-of-n Checker
D1
0
0
a. Requirements Definition
c. General Cell Flow Chart
-
0
-
-
Xi
Dn
Ci-1
b. Simplified Block Diagram
Pi-1
Ai = Ai-1.Xi'
B1
1
1
0
A1
1
Ci-1
0
Bi
f. General Cell Function
"0"
-0
1
0
Ci =Bi-1.Xi + Ci-1.Xi'
DESIGN OF 2-OUT-OF-5 CHECKER
0
1
1
d. General Cell Flow Chart
1
Di*
Bn
4
56
Checker detects if number of "1" in a binary
0
P=0
0
Pi
Xn
1
1
1
0
0
1
0
0
1
Ai-1
Xi
Dn+1
Xi
d. Iteratice Block Diagram
1
1
0
0
0
Bi = Ai-1.Xi + Bi-1.Xi'
A specific code consists of vectors that contain
Bn+1
-
P
"0"
Z=1 when detected vector been found valid.
0
C0
1 0
D0
P0
-
-
0
-0
1
"1"
Di-1
Ci
0
-
0
0
P=1
���������������� ����������������� ���������
Cn C1
An-2
Ci
-
0
0
0
0
Line C : C=1 if X<YDesign refers to positive numbers of n+1 bits, where n may vary according to case.
Bi-1
(X=Y)
Ci
Y0
1
1
Ai = Ai-1 + Bi-1.Xi.Yi'
Ai
Yi
A
-10
Ai
Cn+1
0
Line A : A=1 if X>Y
10 0
Fig. 9-6 : Iterative Binary Numbers Comparator
1
B0
11
0
0
A1
1
B1
Yn-1
0
b. Simplified Block Diagram
9-3
Yi
0
1
Xi
Bi-1
Bi
A>B
Bi
0
Ai-1
0
Xn
0
1
AnBn-2
0
Ci = Ci-1 + Bi-1.Xi.'Yi
1
Ai-10
X0
C
0
Yi
-
01
Ci-1
1
Xn-1
Bi-1
a. Requirements Definition
00
4
56
(X>Y)
1
Ai
0
Ci
c. Iterative Block Diagram
A=B
-
B
0
Bn
0
0 0
f. General Cell Functions
Ai-1
(X<Y)
1
Comparator compares 2 binary numbers X,Y (of equal length), and produces 3 output signals:
01
0
Ci-1
Xi
1
0
C0
A0An+1
DESIGN OF A BINARY COMPARATOR
Bi
0
AB
Xi
1
0
0
d. General Cell Flow Chart
Cn-2
Ci-1
Line B : B=1 if X=Y
Y (Vector)
0
-
-1
Yn
Bn+1
Bi = Bi-1(Xi.Yi+Xi'.Yi') = Bi-1(Xi xor Yi)'
g. General Cell Logic Circuit
X (Vector)
A<B
1
1
0
e. General Cell Truth Table
���������������� ����������������� ���������
1
Fig. 9-9 : Iterative Circuit for TranslatingReflected-Cyclic into Natural-Binary Code
6
8
N(i-1)= N(i)
N(m-1)
0
14
C(m-2)
1 1 1 0
0 0 0 01
1 0 1 1
1
0 1 0 0
1 1 1 1
Fig. 9-8 : Iterative Circuit for Translating Natural-Binary into Reflected-Cyclic Code
Fig. 9-10 : Truth Table for Translating Natural-Binaryinto Reflected-Cyclic Code
0
1 0 1 0
0 0 0 1
1
C(m)
4
0 1 0 0
NaturalBinaryCode
0 0 1 0
12
C(i-1)
N(m-2)
9-4
N(m-1)
0 1 0 1
1 0 0 1
0 1 1 1
0
C(m-1)
1 1 0 1
1
7
1 0 0 1
11
0 0 0 1
1
1 0 0 0
C(m-3)
2
13
1 1 0 1
N(i-1)
0
C(m-3)
C(m-1)
0 0 1 1
50 1 1 0
C(i-1)= N(i)
N(i)
1 0 1 0
N(m-3)
0 1 1 0
ReflectedCyclicCode
Fig. 9-7 : Comparison Between Natural-Binaryand Reflected-Cyclic Code
1 0 1 11 1 0 0
9
0
0 1 1 1
C(m-2)
10
N(m-3)
C(i-1)
N(m)
0 0 1 0
0
0 0 1 1
N(m-2)
1
1 0 0 015
N(m)
DecimalValue
1 1 0 0
N(i-1)
0 0 0 0
1 1 1 1
0 1 0 1
0
C(m)
3
1 1 1 0
���������������� ����������������� ���������
CHAPTER 10
MULTI VARIABLES
KARNAUGHT MAPS
5-Variables Map 6-Variables Map 7-Variables Map 8-Variables Map
���������������� ����������������� ���������
0
0
with impossible conditions :
Fig. 10-4 : 5-Variable Minimzation Exercise (Without Solution)
0
*
-
1
1
1
0
0
1
1
E
1
T=B'C'D'+A'BC'D+CDE'+ABCE
E
F
*
0
0
0
0
-0
A'B'CD'=1
1
with impossible conditions :-
1
b. Karnaugh Map
0
A
B
C
D
0 0
0
0
b. Flat Representation
1
0 0 0
A'B'C'D'=1-
A
B
C
D
E
2
0
0
0
Fig. 103-6 : 6-Variable Minimzation Exercise (WithSolution)
4
1
T=A'B'C'D'+A'BDE'+A'B'CDE'+AB'C'D'+A'BC'DE+ABCDE+ABCD'E
1
1*
A
B
C
D
T=A'C'F'+ACE+C'DE'F+ABDF2
0
a. Original Function
-
0
E'
0
1
0
0
0
*
1
0
1
c. Simplified Function
1
F
a. Original Function
Fig. 10-2 : Optional Constructionof Five-Variable Karnaugh Map (Not Recommended)
1
0
T=A'BC'F'+AB'C'DE'F+ABDF+ACDE+ACD'E++A'C'DE'+A'C'DEF'
Fig. 10-1 : Three-Dimentional Five-VariableKarnaugh Map, and Its Developmenet
0
1A
B
C
D
a. Original Function
A
B
C
D
0
0
0
-
1
b. Karnaugh Map
Fig. 10-5 : Three-Dimentional sIx-VariableKarnaugh Map, and Its Developmenet
E'
0
0
A
B
C
DE
D
1
0
A
B
C
D
b. Karnaugh Map
-
0
1 0
A
B
C
Db. Flat Representation
*
4
0
0
0
T=
-
1
1
*
1
0
c. Simplified Function
0
E'
0
ACDE'=1
0
*
3
0
-
1 1
E
0
1
0
A
B
C
D c. Simplified Function
1
1
-
1 1
E
0
0
0
1
a. 3-D Representation
0
Fig. 10-3 : 5-Variable Minimzation Exercise (With Solution)
0
0
0
10-1
a. 3-D Representation
A'BCD'F=1
3
T=A'B'C'E'+A'B'CD'+ABC'DE'+AB'C'E'+AB'CD'E'+B'C'D'E+A'B'C'DE+CD'E
0
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a. Lower Level
1
-
G
F
E
H
1
a. Upper Level
F
-
*
2
A
B
C
D
-
-
-
-
1
1
-
11
64-Square Cell
1 2 3 4 5 6 7
-
E
1 2
16-Square Cell
1
-
-
1
- --
G
1
-
1
-
1
- -
-
1
- -
a. Function Karnaugh Map
--
Fig. 10-10 : 8-Variable Minimzation Exercise
1
-
-4-Square Cell
E'FG'H
-
- -
*
-
1
3
3
-
-
1
-
b. Lower Level
A
B
C
D
-
-- -
-
A
B
C
D
1
1
a. Upper Level
-
-
F
-
1
1
-
-2 3 4 5 6 7 8
F
--
-
-
-
G
1
--
10-2
8-Square Cell
1
4
1
1
b. Simplified Function
*
-
-
1
11
-
1
1
-
-1
2 3 4 5 6 7 8
-
H
-
-
1
-
1
1
1
Fig. 10-9 : Eight-Variable KarnaughMap, and Its Developmenet
Fig. 10-11 : Number of VariablesRequired to Define Certain CellAddress
A
B
C
D
1
1 2 3 4 5
E
1
-
1
-
1 2 3 4 5 6
-
-
1
1
1
-
1 2 3
-
1
-
--
-
-
1
-
-
-Size of Cell
1
-
11
2-Square Cell
T=A'C'D'G'+ABCF'+B'D'FG+A'C'EF'
-
-
Number of Variablesin The Function
-
1
1 1
--
4
G
1
-
Fig. 10-7 : Seven-Variable KarnaughMap, and Its Developmenet
*
- -1
--Single Square
1
A
B
C
D
1
-
1
1
32-Square Cell
-
-
c. Flat Representation
-
EF'G'
-
-
1
1
1 2 3 4
-
1
1
-
128-Square Cell
E
F
G
1
Fig. 10-8 : 7-Variable MinimzationExercise (With Solution)
-
1
1
2
E
-
--
AB'C'D'EF'G'
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Semi-Karnaugh Maps T.B.D.
10-3
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CHAPTER 11
PNEUMATIC FLOW-TABLE METHODE
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1
a2
6
c2.y1.y2'
S1
,A-,B-
+-
R1
S2
1
c. Complete Flow Table
S2
a2.b2.y2'
+-
S
a2.b2
1
a1.b2.y3
4
a1.y1'
1
S1
A- = a2.b2.y2'+a2.b2.y2 = a2.b2
R2
R2
Fig. 11-5 : Pneumatic Flow-Table Design for
y3.y4
y'
c2.y1.y2'
b2
3
S1
1
R1
R1
A-
c. Exitation and Output Functions
y1.y2
S1= a2.y3'
S1
y1'
B-
11-1
a1
1
1
R2
B- = a1.b2.y3'+a1.b2.y3 = a1.b2
1
c2
a2.y3
+-
S3
R1 = a2.y3.y4
y1
3
R
c2.y1'
R2
R3
1
S1
R1
1
S3
S1
a2.y3.y4
A+
y2
+-
a1
1
S2 = a2.y3.y4'
s2
+-
c2
y3'
S1
y
A- B+
5
a1.y1
1
a1.b1.y1'
c2.y1'
S2
B+
1
R2 = a2.y3'
y3'
1
c2
R1
R4
a1.b1
S3
+-
4
+-
A+
S3
S2 = a1.b1.y1
(a1.b1)
+-
R3
R1
,A-,B-
1
S3 = a1.y1.y2'
S1
B-
c2.y1.y2
y1.y2'
a1.b2
c2.y'
R3
A+a2
y3
S3
B+ = a2.b1+a1.b1.y1
R1
c2.y1.y2.y3'
R3
R3 = a1.y1'
a2.b1
d. Control Circuit
+
c2.yS2
S2
b. Complete Flow Table
a1
A+
+-
R4
y1'
R1
S2
S3
e. Control Circuit
S4 = a1.y1.y2
a. Process sequence
7
y3.y4'
a. Flip-Flop Valve
S1 = a1.b2.y3'
A-
Sequence START,A+,B+,A-,B-,
S4
b2
a2.b2
+-
c2.y1.y2.y3
a1.y1.y2'
Fig. 11-4 : Pneumatic Flow-Table Design for
R4 = a1.y1.y2'
START,A+,B+,A-,B-,
b. Steering Valve
S4
R1 = a1.b2.y3
R21
START
(a2.b1)
a1.b2
a2.b2.y2
+-
Fig. 11-2 : Two SteeringValves providing 3addresses
R2
A+ = a1.y1'.Start+a1.y1.y2'+a1.y1.y2 = a1.y1'.Start+a1.y1
A+
a1
R2 = a2.b1
R31
1
R3
a2.y3'
sequences START,A+,A-,A+,A-,A+,A-
A+
a1.y1.y2
R2
Fig.11-1 : Flip-Flop Valveand Steering Valve
+-
B+
2
+-
a2
S3 = a2.b2.y2
y2'
+-
1
Fig. 11-3 : Three SteeringValves providing 4addresses
1
S3
a. Process sequence
a1
6
a2
S4
6
B+
5
3
A+
1
R3 = a2.b2.y2'
2
4
1
1
A- = a2.y3'+a2.y3.y4'+a2.y3.y4 = a2.y3'+a2.y3 = a2
b1
S
a2
START,A+,A-,A+,A-,A+,A-
A-
a2.y3.y4'
S2R3
5
A-
A+ = a1.b1.y1'.Start+a1.b1.y1 = a1.b1.Start+a1.b1.y1
1
d. Exitation and Output Functions
+-
R
R2
b. Flow Table
a1.b1.y1
+
a1.b2.y3'
R4
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C- = b1.c2.y3
a2.b2.c1
(b1.c2)
1R2
R2
a1a2
1
S2 = b1.c2.y3
a1.b1.c1A-
B-
3 S1
X
(b1.c2)
S2
B+ = a2.b1.c1.y1'+b1.c2.y3'
4
7
+-
b1.c2.y3'
y3
1
e. Control Circuit
a2.b1.c1
B- = b2.c1+b2.c2 = (b2)
S3
11-2
B-
a2 b2 c2 b2 c2
(a1)
A-
a2.b1.c2
(b2.c2)
R1
y1.y2'
c. Simplifiying Input Map
+
a2.b2.c2
c2
C+
1
R2 = b2.c1
y1.y2
A- = a2.b1.c1.y1.y2
XS1 = b2.c1
C-
1
a2.b1.c1.y1.y2'
R2
C-
a1 b1 c1 a1
5
C+ = a2.b1.c1.y1.y2'
1
c1
1
S3 = b2.c2
(b2.c2)
a. Process sequence
+-
b. Complete Flow Table
S3
a2.b1.c1.y1'
y3'
S2
R3
b1
a2.b1.c1
a2
b2
c2
a1
c1
b1b1
R3
a2.b1.c1.y1.y2
S2
B+
(b1.c1)
(b2.c1)
S1
A+
d. Exitation and Output Functions
A+
X
1
c2
X R3 = a2.b1.c1.y1.y2'a2 b2 c1 b2 a1
R1
b1.c2.y3
8
START,A+,B+,B-,C+,B+,B-,C-,A-
1
X
6
R3
S1B+
S3
y1'
Fig. 11-6 : Pneumatic Flow-Table Design for Sequence START,A+,B+,B-,C+,B+,B-,C-,A-
+-
R1
a2 b1 c2 b1 c2
+-
R1 = a1
A+ = a1.START
C+
c1
b2
+-
2
(b2.c1)
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CHAPTER 1,
MOTION ACTUATORS
Linear and Angular Motion Electrical Linear Actuators Electrical Rotary Actuators Fluid-power Linear Actuators Fluid-power Rotating Actuators Boolean Functions Standard Formats
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Fig. 11-3 : Eight types of Pneumatic rotary actuators
12-1
Fig. 11-1 : Solenoid
Fig. 11-2 : Force-stroke curve for Typical ½” diameter solenoid
Fig. 11-4 : Pneumatic cylinder With air cushions
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Fig. 12-5 : Basic cylinder types
12-2
Fig. 12-6 : Fifteen ways of using cylindres
Fig. 12-7 : Two application of “airstroke” Actuator (Firestonr)
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13-3
Fig. 12-8 : Eight types of Pneumatic rotary actuators
Fig. 12-9 : Air motor
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CHAPTER �#
SENSORS
Electric Position Sensors Contacts Symbols Photoelectric Sensors Reed Switches Proximity Sensors Pressure, Flow and Level Switches Pneumatic Limit Valves Back-Pressure Sensors
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Fig. 13-1
Fig. 13-3 : Limit-switch symbols for different contact configurations
Fig. 13-2 : Common contact arrangements
Fig. 13-4 : SPDT switch with (a) break-before-make (BBM) contacts, and (b) make-before-break (MBB) contacts
Fig. 13-5 :
13-1
Fig. 13-11 : Use of magnetic proximity sensor To measure rotational velocity
Fig. 13-5 : SPDT Three operating modes of photoelectric sensor –
(a) through beam (b) reflection from target (c) retroreflection
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13-2
Fig. 13-6 : Methods for actuating Reed switches
Fig. 13-7 : Use of reed switch to sense piston position
Fig. 13-8 : Arc suppression method for protecting relay & switch controls
Fig. 13-9 : Proximity sensor Fig. 13-10 : Proximity sensor application
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13-3
Fig. 13-12 : Four basic types of pressure switches
Fig. 13-13 : pressure switch (diagram and Step acts on a limit
Fig. 13-14 : Level switch (based On reed switch)
Fig. 13-15 : Two flow switches (based on reed switch)
Fig. 13-16 : Symbols for various sensor switches (normally-open contacts)
Fig. 13-17 : Sensor switch - (a ) without dead band (b) With dead band (hysteresis)
Fig. 13-18 : Fig. 13-19 :
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13-4
Fig. 13-20 : Flapper-Nozzle system used as back-pressure
Fig. 13-21 : Back-pressure sensor with overtravel rotection
Fig. 13-21 : Back-pressure sensor with overtravel rotection
Fig. 13-22 : Detecting liquid level of power level using back-pressure sensor (bubble tube)
Fig. 13-23 : Annular back-pressure (a) output pressure P0 low Fig. 13-23 : Annular back-pressure (a) output pressure P0 low (b) sensor P0 high
Fig. 13-24 : Interruptable-jet sensor
Fig. 13-25 : Interruptable-jet sensor (insensitive to dirt)
Fig. 13-26 : Interruptable-jet sensor (with remote actuation)
Fig. 13-27 : Ultrasonic sensor, and several applications
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CHAPTER ��
FRAFCET METHODE
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STA
RT
- L'
Xi+
1
ZAj
XA
J-1
ZB1
Val
ve D
is C
lose
d
A2
F'
A2
Xi
.....
Bk
4
XA
2X
A2
XB
k-1
XA
J-1
Fig.
14-
2 : G
RA
FCE
T fo
rA
ltern
ate
Par
alle
l Pat
hs
XB
1
ZA1
.....
F"Rea
dy"
Sig
nal
Zi
ZA1
i+1
H
Ytm
r
5
Xi-P
XA
j
XA
1
XB
k-1
XA
1
XB
2
ZA2
XA
j.XB
k
Ytm
r
ZB1
Zi+1
ZB2
2
i+1
B1
Fig.
14-
3 : G
RA
FCE
T fo
rS
imul
tane
ous
Par
alle
l Pat
hs
i
.....
A1
Fig.
14-
1 : G
RA
FCE
T fo
rA
utom
ated
Mix
ing
Sys
tem
(Fig
. 5-1
1)
ZBk
B1
1
M'
Aj
Xi-P
D'
B2
ZAj
14-1
D
B2
ZB2
L'
A1
Zi Zi+1Bk
XB
2
Xi+
1
M
Aj
.....
EN
D
XB
k
Wai
t
i
ZBk
3
ZA2
XB
1
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Rot
ate
Pla
te
Pla
te R
otat
ed
Gau
ge U
p
11R
aise
Gau
ge
T=2s
2
15R
etra
ctLo
ader
3
14-2
4
14
=1
Wai
t
T>2s
Ret
ract
Eje
ctor
Ret
ract
Cla
mp
Man
ual R
eset
Sta
rt A
ND
Initi
al C
ondi
tions
16
Dis
cend
Gau
ge5
Wai
t
6D
isce
ndD
rill
Adv
ance
Load
er
Adv
ance
Eje
ctor
Load
er R
etra
cted
Dri
ll D
own
8
Eje
ctor
Ret
acte
d
Rai
seG
auge
Wai
t9
Pie
ce L
oade
d
Gau
ge U
p
13
Fig.
14-
4 : G
RA
FCE
T fo
r D
rilli
ng S
tatio
n
1
Adv
ance
Cla
mp
7
Pie
ce U
ncla
mpe
d
10
Dri
ll U
pP
iece
Eje
cted
Ras
eD
rill
Pie
ce C
lam
ped
Gau
ge D
own
AN
D T
<2s
12
(Fro
m T
elem
echa
niqu
e TS
X T
607
Man
ual)
17
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