5th International VLBI Technology Workshop, MIT Haystack Observatory, October 12-14, 2016

Institute of Applied Astronomy

Influence of digitization in digital backends on VLBI sensitivity loss

Evgeny Nosov

Institute of Applied Astronomy Russian Academy of Sciences

5th International VLBI Technology Workshop, MIT Haystack Observatory, October 12-14, 2016 2

Digital backend parameters

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Jitter

Usual approach: Sine input signal without noise -> infinite SNR Jitter produces error signal that affects input signal The error signal limits SNR:

𝜎𝑗 ≤1

2𝜋𝑓2𝑞

𝑆𝑁𝑅 = −20 ∙ log10 2𝜋𝑓𝜎𝑗

f – input sine frequency, σj – rms jitter

VLBI case: Input signal is wideband noise with low SNR

In case of direct RF sampling with 8-bits ADC and 14 GHz highest frequency the restriction for jitter rms is about 44 femtosecond. Hard to implement!

To keep the noise due to jitter less than quantization error:

5th International VLBI Technology Workshop, MIT Haystack Observatory, October 12-14, 2016 4

Approach №1. Initial assumption

ADCs input signals: normal noise rectangular spectrum from f1 to f2 signal and noise power on both stations

are equal => equal SNR Jitter: random jitter with zero-mean normal

distribution equal jitter RMS (σj) on both stations

𝑆𝑁𝑅𝑖𝑛 =𝑃𝑠𝑃𝑛

Ps

Pn

f1 f2

S(f)

f

𝑆𝑁𝑅𝑜𝑢𝑡 =𝑃𝑠

𝑃𝑛 + 𝑃𝑒𝑟𝑟

𝑙𝑜𝑠𝑠 =𝑆𝑁𝑅𝑜𝑢𝑡

𝑆𝑁𝑅𝑖𝑛=

𝑃𝑠𝑃𝑛 + 𝑃𝑒𝑟𝑟

∙𝑃𝑛𝑃𝑠

=𝑃𝑛

𝑃𝑛 + 𝑃𝑒𝑟𝑟

+ ADC~fclk

Jitter σj

Ps – signal power Pn – noise power Perr – power of error signal caused by jitter

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Power of error signal

[Kobayashi H., Kobayashi K., Morimura M., Onaya Y., Takahashi Y., Enomoto K., Kogure H. Sampling Jitter and Finite Aperture Time Effects in Wideband Data Acquisition Systems. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Vol.E85-A, No.2, 2002]

𝑃𝑒𝑟𝑟 = 2 𝑆 𝑓 2 1 − 𝑒−2𝜋2𝑓2𝜎𝑗2

𝑑𝑓∞

−∞

𝑃𝑒𝑟𝑟 = 2 𝑃𝑠 + 𝑃𝑛 1 − 𝑒−2𝜋2𝑓2𝜎𝑗

2

𝑑𝑓𝑓2𝑓1

𝑓2 − 𝑓1

erf 𝑥 =2

𝜋 𝑒−𝑡2

𝑥

0

𝑑𝑡

𝑃𝑒𝑟𝑟 = 2 𝑃𝑠 + 𝑃𝑛 1 −1

2 2𝜋𝜎𝑗∙erf 2𝜋𝑓2𝜎𝑗 − er f 2𝜋𝑓1𝜎𝑗

𝑓2− 𝑓1)

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Verification

f2 = 1 GHz f1 = f2 1 Hz

𝑆𝑁𝑅𝑗 =𝑃𝑠𝑃𝑒𝑟𝑟

=1

2 1 −1

2 2𝜋𝜎𝑗∙𝑒𝑟𝑓 2𝜋𝑓2𝜎𝑗 − 𝑒𝑟𝑓 2𝜋𝑓1𝜎𝑗

𝑓2− 𝑓1)

𝑆𝑁𝑅𝑠𝑖𝑛 = −20 ∙ log10 2𝜋𝑓𝜎𝑗

[Nicola Da Dalt, Moritz Harteneck, Christoph Sandner, and Andreas Wiesbauer. On the Jitter Requirements of the Sampling Clock for Analog-to-Digital Converters. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol.49, No.9, Sept. 2002. p.1354—1360]

𝑆𝑁𝑅𝑛𝑜𝑖𝑠𝑒 = −20 ∙ log10

1

32𝜋𝑓𝜎𝑗

Input signal: Sine Noise with rectangular spectrum from DC to f

f2 = 1 GHz f1 = 0

Assume Pn = 0 =>

Sine Noise

𝜎𝑗 ≪ 1 𝑓

5th International VLBI Technology Workshop, MIT Haystack Observatory, October 12-14, 2016 7

Verification by known case

𝑆𝑁𝑅𝑠𝑖𝑛 = −20 ∙ log10 2𝜋𝑓𝜎𝑗 𝑆𝑁𝑅𝑛𝑜𝑖𝑠𝑒 = −20 ∙ log10

1

32𝜋𝑓𝜎𝑗

𝑆𝑁𝑅𝑗 =𝑃𝑠𝑃𝑒𝑟𝑟

=1

2 1 −1

2 2𝜋𝜎𝑗∙𝑒𝑟𝑓 2𝜋𝑓2𝜎𝑗 − 𝑒𝑟𝑓 2𝜋𝑓1𝜎𝑗

𝑓2− 𝑓1)

5th International VLBI Technology Workshop, MIT Haystack Observatory, October 12-14, 2016 8

Coefficient of sensitivity loss due to jitter. 1-1.5 GHz.

𝑙𝑜𝑠𝑠 =1

1 + 2 𝑆𝑁𝑅𝑖𝑛 + 1 1 −1

2 2𝜋𝜎𝑗∙erf 2𝜋𝑓2𝜎𝑗 − er f 2𝜋𝑓1𝜎𝑗

𝑓2− 𝑓1)

f1=1024 MHz f2=1536 MHz

5th International VLBI Technology Workshop, MIT Haystack Observatory, October 12-14, 2016 9

f1=2 GHz f2=14 GHz

Coefficient of sensitivity loss due to jitter. 2-14 GHz.

loss < 0.1% when jitter < 574 fs (input SNR<0.1)

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Alternate approach

𝑅𝑗 𝜏 = 𝑥 𝑛𝑡𝑠 + 𝑡𝑗𝑥 𝑦∗ 𝑚𝑡𝑠 + 𝑡𝑗𝑦

𝑅𝑗 𝜏 = 𝑋 𝑓 𝑒𝑗2𝜋𝑓𝑡𝑗𝑥𝑌∗ 𝑓)∞

−∞

𝑒−𝑗2𝜋𝑓𝑡𝑗𝑦𝑒𝑗2𝜋𝑓𝜏𝑑𝑓

𝑅𝑗 0 = 𝐴2 𝑒𝑗2𝜋𝑓 𝑡𝑗𝑥−𝑡𝑗𝑦𝑓2

𝑓1

𝑑𝑓

m, n – sample numbers ts – sampling time tjx, tjy – jitters affecting input signals σj – jitters rms

𝑒𝑗2𝜋𝑓𝑡𝑗 = cos 2𝜋𝑓 𝑡𝑗𝑥 − 𝑡𝑗𝑦 + 𝑗 sin 2𝜋𝑓 𝑡𝑗𝑥 − 𝑡𝑗𝑦 = 1 −1

22𝜋𝑓 2(2𝜎𝑗

2)

The error of approximation is less than 1% if |2𝜋𝑓 𝑡𝑗𝑥 − 𝑡𝑗𝑦 | <𝜋

5

Correlation with jitter:

Correlation without jitter:

𝑅𝑗 0 = 𝐴2 1 − 2𝜋𝑓𝜎𝑗2

𝑓2

𝑓1

𝑑𝑓 = 𝐴2 𝑓2− 𝑓

1− 2𝜋𝜎𝑗

2

𝑓23

3−

𝑓13

3

𝑅 0 = 𝑋 𝑓 𝑌∗ 𝑓∞

−∞

𝑑𝑓 = 𝐴2 1𝑓2

𝑓1

𝑑𝑓 = 𝐴2 𝑓2− 𝑓

1

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𝑙𝑜𝑠𝑠 =𝑅𝑗 0)

𝑅 0)= 1 −

2𝜋𝜎𝑗2 𝑓

23 − 𝑓

13)

3 𝑓2− 𝑓

1)

Alternate approach

5th International VLBI Technology Workshop, MIT Haystack Observatory, October 12-14, 2016 12

ADC input signal level

ADC full scale: −UADC to + UADC

Input signal is normal noise SNR << 1

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ADC input signal level

[A.R.Thompson. Quantization Efficiency for Eight or more Sampling Levels. MMA Memo 220. 1998]

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ADC input signal level

18.248 ∙ 𝑈𝐴𝐷𝐶

2𝑞 < 𝜎 <𝑈𝐴𝐷𝐶

2.77

10 ≤ 𝜎′ ≤2𝑞

5.54

To keep loss<0.1% input signal rms has to be

or

∙ − floor operator 𝜎′ =𝜎

𝑈𝐿𝑆𝐵

Can be used in AGC loop controlled by FPGA

(for ADC resolution ≥ 8 bits)

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THANK YOU FOR ATTENTION!