instruction set 3.4.5 instruction set description sheet mkiii.pdfas ad d/s register syntax...

MSP430 Addressing Modes

As Ad d/s Register Syntax Description

00 0 ds n ≠ 3 Rn Register direct. The operand is the contents of Rn. Ad=0

01 1 ds n ≠ 0, 2, 3 x(Rn) Indexed. The operand is in memory at address Rn+x.

10 - s n ≠ 0, 2, 3 @Rn Register indirect. The operand is in memory at the address held in Rn.

11 - s n ≠ 0, 2, 3 @Rn+ Indirect auto-increment. As above, then the register is incremented by 1 or 2.

Addressing modes using R0 (PC)

01 1 ds 0 (PC) LABEL Symbolic. x(PC) The operand is in memory at address PC+x.

11 - s 0 (PC) #x Immediate. @PC+ The operand is the next word in the instruction stream.

Addressing modes using R2 (SR) and R3 (CG), special-case decoding

01 1 ds 2 (SR) &LABEL Absolute. The operand is in memory at address x.

10 - s 2 (SR) #4 Constant. The operand is the constant 4.


00 - s 3 (CG) #0 Constant. The operand is the constant 0.

01 - s 3 (CG) #1 Constant. The operand is the constant 1. There is no index word.


11 - s 3 (CG) #−1 Constant. The operand is the constant −1.

MSP430 Instruction Set 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Instruction

0 0 0 1 0 0 opcode B/W As register Single-operand arithmetic

0 0 0 1 0 0 0 0 0 B/W As register RRC Rotate right through carry

0 0 0 1 0 0 0 0 1 0 As register SWPB Swap bytes

0 0 0 1 0 0 0 1 0 B/W As register RRA Rotate right arithmetic

0 0 0 1 0 0 0 1 1 0 As register SXT Sign extend byte to word

0 0 0 1 0 0 1 0 0 B/W As register PUSH Push value onto stack

0 0 0 1 0 0 1 0 1 0 As register CALL Subroutine call; push PC and move source to PC

0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 RETI Return from interrupt; pop SR then pop PC

0 0 1 condition 10-bit signed offset Conditional jump; PC = PC + 2×offset

0 0 1 0 0 0 10-bit signed offset JNE/JNZ Jump if not equal/zero

0 0 1 0 0 1 10-bit signed offset JEQ/JZ Jump if equal/zero

0 0 1 0 1 0 10-bit signed offset JNC/JLO Jump if no carry/lower

0 0 1 0 1 1 10-bit signed offset JC/JHS Jump if carry/higher or same

0 0 1 1 0 0 10-bit signed offset JN Jump if negative

0 0 1 1 0 1 10-bit signed offset JGE Jump if greater or equal

0 0 1 1 1 0 10-bit signed offset JL Jump if less

0 0 1 1 1 1 10-bit signed offset JMP Jump (unconditionally)

opcode source Ad B/W As destination Two-operand arithmetic

0 1 0 0 source Ad B/W As destination MOV Move source to destination

0 1 0 1 source Ad B/W As destination ADD Add source to destination

0 1 1 0 source Ad B/W As destination ADDC Add source and carry to destination

0 1 1 1 source Ad B/W As destination SUBC Subtract source from destination (with carry)

1 0 0 0 source Ad B/W As destination SUB Subtract source from destination

1 0 0 1 source Ad B/W As destination CMP Compare (pretend to subtract) source from destination

1 0 1 0 source Ad B/W As destination DADD Decimal add source to destination (with carry)

1 0 1 1 source Ad B/W As destination BIT Test bits of source AND destination

1 1 0 0 source Ad B/W As destination BIC Bit clear (dest &= ~src)

1 1 0 1 source Ad B/W As destination BIS Bit set (logical OR)

1 1 1 0 source Ad B/W As destination XOR Exclusive or source with destination

1 1 1 1 source Ad B/W As destination AND Logical AND source with destination (dest &= src)

MSP430 Emulated Instructions

Mnemonic Operation Emulation Description

LogicalandRegisterControlInstructions

INV(.Bor.W)dst .NOT.dst→dst XOR(.Bor.W)#0(FF)FFh,dst Invertbitsindestination

RLA(.Bor.W)dst C←MSB←MSB1

LSB+1←LSB←0

ADD(.Bor.W)dst,dst Rotateleftarithmetically

RLC(.Bor.W)dst C←MSB←MSB1

LSB+1←LSB←C

ADDC(.Bor.W)dst,dst Rotateleftthroughcarry

ProgramFlowControl

BRdst dst→PC MOVdst,PC Branchtodestination

DINT 0→GIE BIC#8,SR Disable(general)interrupts

EINT 1→GIE BIS#8,SR Enable(general)interrupts

NOP None MOV#0,R3 Nooperation

RET @SP→PCSP+2→SP MOV@SP+,PC Returnfromsubroutine


DataInstructions

CLR(.Bor.W)dst 0→dst MOV(.Bor.W)#0,dst Cleardestination

CLRC 0→C BIC#1,SR Clearcarryflag

CLRN 0→N BIC#4,SR Clearnegativeflag

CLRZ 0→Z BIC#2,SR Clearzeroflag

POP(.Bor.W)dst @SP→temp

SP+2→SP

temp→dst

MOV(.Bor.W)@SP+,dst Popbyte/wordfromstacktodestination

SETC 1→C BIS#1,SR Setcarryflag

SETN 1→N BIS#4,SR Setnegativeflag

SETZ 1→Z BIS#2,SR Setzeroflag

TST(.Bor.W)dst dst+0FFFFh+1

dst+0FFh+1

CMP(.Bor.W)#0,dst Testdestination


ArithmeticInstructions

ADC(.Bor.W)dst dst+C→dst ADDC(.Bor.W)#0,dst Addcarrytodestination

DADC(.Bor.W)dst dst+C→dst(decimally) DADD(.Bor.W)#0,dst Decimaladdcarrytodestination

DEC(.Bor.W)dst dst1→dst SUB(.Bor.W)#1,dst Decrementdestination

DECD(.Bor.W)dst dst2→dst SUB(.Bor.W)#2,dst Decrementdestinationtwice

INC(.Bor.W)dst dst+1→dst ADD(.Bor.W)#1,dst Incrementdestination

INCD(.Bor.W)dst dst+2→dst ADD(.Bor.W)#2,dst Incrementdestinationtwice

SBC(.Bor.W)dst dst+0FFFFh+C→dst

dst+0FFh→dst

SUBC(.Bor.W)#0,dst Subtractsourceandborrow/.NOT.carry

fromdest.

0xxx

4xxx

8xxx

Cxxx

1xxx

14xx

18xx

1Cxx

20xx

24xx

28xx

2Cxx

30xx

34xx

38xx

3Cxx

4xxx

5xxx

6xxx

7xxx

8xxx

9xxx

Axxx

Bxxx

Cxxx

Dxxx

Exxx

Fxxx

RRC RRC.B SWPB RRA RRA.B SXT PUSH PUSH.B CALL RETI

000 040 080 0C0 100 140 180 1C0 200 240 280 2C0 300 340 380 3C0

JNE/JNZ

JEQ/JZ

JNC

JC

JN

JGE

JL

JMP

MOV, MOV.B

ADD, ADD.B

ADDC, ADDC.B

SUBC, SUBC.B

SUB, SUB.B

CMP, CMP.B

DADD, DADD.B

BIT, BIT.B

BIC, BIC.B

BIS, BIS.B

XOR, XOR.B

AND, AND.B

www.ti.com Instruction Set

3.4.5 Instruction Set DescriptionThe instruction map is shown in Figure 3-12 and the complete instruction set is summarized in Table 3-17.

Figure 3-12. Core Instruction Map

Table 3-17. MSP430 Instruction SetMnemonic Description V N Z C

ADC(.B) (1) dst Add C to destination dst + C → dst * * * *ADD(.B) src,dst Add source to destination src + dst → dst * * * *ADDC(.B) src,dst Add source and C to destination src + dst + C → dst * * * *AND(.B) src,dst AND source and destination src .and. dst → dst 0 * * *BIC(.B) src,dst Clear bits in destination not.src .and. dst → dst - - - -BIS(.B) src,dst Set bits in destination src .or. dst → dst - - - -BIT(.B) src,dst Test bits in destination src .and. dst 0 * * *BR (1) dst Branch to destination dst → PC - - - -CALL dst Call destination PC+2 → stack, dst → PC - - - -CLR(.B) (1) dst Clear destination 0 → dst - - - -CLRC (1) Clear C 0 → C - - - 0CLRN (1) Clear N 0 → N - 0 - -CLRZ (1) Clear Z 0 → Z - - 0 -CMP(.B) src,dst Compare source and destination dst - src * * * *DADC(.B) (1) dst Add C decimally to destination dst + C → dst (decimally) * * * *DADD(.B) src,dst Add source and C decimally to dst src + dst + C → dst (decimally) * * * *DEC(.B) (1) dst Decrement destination dst - 1 → dst * * * *

(1) Emulated Instruction

65SLAU144I–December 2004–Revised January 2012 CPUSubmit Documentation Feedback

Copyright © 2004–2012, Texas Instruments Incorporated

Rnx(Rn)

LABEL

&LABEL

































































































NOTE: 0(Rn) = @Rn when source

asm code machine code source RegAd

(dest) B/~W destination* IF NEEDED

Additional Data 1* IF NEEDED

Additional Data 2

mov.w R5, R6 4506 0 1 0 0 5 0 0 0 0 6 -‐ -‐

add.b R4, R8 5448 0 1 0 1 4 0 1 0 0 8 -‐ -‐

bit.w @R7, R12 B72C 1 0 1 1 7 0 0 1 0 C

bit.b 0(R7), R15 B76F 1 0 1 1 7 0 1 1 0 F

bic.b 2(R8), 0(R8) C8D8 0002 0000 1 1 0 0 8 1 1 0 1 8 0002 0000

bic.w 2(R8), 4(R7) C897 0002 0004 1 1 0 0 8 1 0 0 1 7

bis.w #0xAAAA, R11 D03B AAAA 1 1 0 1 0 0 0 1 1 B AAAA

rra.b R10 114A 0 0 0 1 0001 0 1 0 0 A

rrc.w R11 100B 0 0 0 1 0000 0 0 0 0 B

jmp LABEL 3 [11xx xxx xxxx] 0 0 1 1 11xx x x x x (offset -‐ Δ inst. words)

cmp R13, 2(R8) 9D88 0002 1 0 0 1 D 1 0 0 0 8 0002

jnz LABEL 2 [00xx xxxx xxxx] 0 0 1 0 00xx x x x x (offset -‐ Δ inst. words)

rla.b R10 5A4A

add.b R10, R10 ç (emulated code) é 0 1 0 1 A 0 1 0 0 A

rlc.w R11 6B0B

addc.w R11, R11 ç (emulated code) é 0 1 1 0 B 0 0 0 0 B

inv.w R10 E33A

xor.w #0xFFFF, R10 ç (emulated code) é 1 1 1 0 3 0 0 1 1 A

inc.w R11 531B

add.w #0x0001, R11 ç (emulated code) é 0 1 0 1 3 0 0 0 1 B

opcode As (Src)

SR Bit

add.w inc.w incd.b add.b 0100 0000 0000 0000 0111 1111 1111 1111 0111 1110 1011 0000+0111 0100 0010 1011 + 1000 1000 1011 0100 0010 1011 1000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0011 1000

cmp.w inv.w dec.b sub.b 0000 0010 0101 0101 0101 0000 1111 1010 0000 0000 0000 0000 0000 0101 1111 1100 1110 0000 - 0000 0111 1111 1111 0011 0101 1010 1111 0000 0101 0000 0000 1111 1111 0000 0000 1111 1110

sub.w rra.w and.b xor.b 0000 0010 0101 0101 0000 0000 0000 0001 1010 1010 0010 1101-0000 0010 0101 0101 0101 0101 0010 1101 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

add.w rra.w rlc.b rrc.b 1000 0000 0000 0000 0000 0100 0000 0001 0000 0000 1000 0010 0000 0000 1101 1011 1000 0000 0000 0001(1) 0000 0000 0000 0001 0000 0010 0000 0000 (1) (1) 0000 0000 0000 0100 0000 0000 0110 1101 (1)

After the operation is complete, the SR bits are set based on these conditions

Negative: The leading digit (MSB) is 1 -‐ the number "negative" if you are using signed numbers

oVerflow: "signed" overflow -‐ leading digit (MSB) switched from (+) to (-‐) or from (-‐) to (+)

Zero: All the bits are 0

Carry: "unsigned" overflow -‐ there was not enough space -‐ a digit got knocked off either end

examples in binary

examples in binary

examples in binary

examples in binary

V

N

Z

C

NOTE: 0(Rn) = @Rn when source

asm code machine code source RegAd

(dest) B/~W destination* IF NEEDED

Additional Data 1* IF NEEDED

Additional Data 2

mov.w R5, R6 4506 0 1 0 0 5 0 0 0 0 6 -‐ -‐

add.b R4, R8 5448 0 1 0 1 4 0 1 0 0 8 -‐ -‐

bit.w @R7, R12 B72C 1 0 1 1 7 0 0 1 0 C

bit.b 0(R7), R15 B76F 1 0 1 1 7 0 1 1 0 F

bic.b 2(R8), 0(R8) C8D8 0002 0000 1 1 0 0 8 1 1 0 1 8 0002 0000

bic.w 2(R8), 4(R7) C897 0002 0004 1 1 0 0 8 1 0 0 1 7

bis.w #0xAAAA, R11 D03B AAAA 1 1 0 1 0 0 0 1 1 B AAAA

rra.b R10 114A 0 0 0 1 0001 0 1 0 0 A

rrc.w R11 100B 0 0 0 1 0000 0 0 0 0 B

jmp LABEL 3 [11xx xxx xxxx] 0 0 1 1 11xx x x x x (offset -‐ Δ inst. words)

cmp R13, 2(R8) 9D88 0002 1 0 0 1 D 1 0 0 0 8 0002

jnz LABEL 2 [00xx xxxx xxxx] 0 0 1 0 00xx x x x x (offset -‐ Δ inst. words)

rla.b R10 5A4A

add.b R10, R10 ç (emulated code) é 0 1 0 1 A 0 1 0 0 A

rlc.w R11 6B0B

addc.w R11, R11 ç (emulated code) é 0 1 1 0 B 0 0 0 0 B

inv.w R10 E33A

xor.w #0xFFFF, R10 ç (emulated code) é 1 1 1 0 3 0 0 1 1 A

inc.w R11 531B

add.w #0x0001, R11 ç (emulated code) é 0 1 0 1 3 0 0 0 1 B

opcode As (Src)

















































No. Emulated Mnemonic Operand(s) V N Z C

1 ¤ ADC(.B) dst Add C to destination dst+C→dst * * * *2 ADD(.B) src,dst Add source to destination src+dst→dst * * * *3 ADDC(.B) src,dst Add source and C to destination src+dst+C→dst * * * *4 AND(.B) src,dst AND source and destination src .and. dst → dst 0 * * *5 BIC(.B) src,dst Clear bits in destination not.src .and. dst → dst - - - -6 BIS(.B) src,dst Set bits in destination src .or. dst → dst - - - -7 BIT(.B) src,dst Test bits in destination src .and. dst 0 * * *8 ¤ BR dst Branch to destination dst → PC - - - -9 CALL dst Call destination PC+2 → stack, dst → PC - - - -

10 ¤ CLR(.B) dst Clear destination 0 → dst - - - -11 ¤ CLRC Clear C 0→C - - - 012 ¤ CLRN Clear N 0→N - 0 - -13 ¤ CLRZ Clear Z 0→Z - - 0 -14 CMP(.B) src,dst Compare source and destination dst - src * * * *15 ¤ DADC(.B) dst Add C decimally to destination dst + C → dst (decimally) * * * *16 DADD(.B) src,dst Add source and C decimally to dst src + dst + C → dst (decimally) * * * *17 ¤ DEC(.B) dst Decrement destination dst - 1 → dst * * * *18 ¤ DECD(.B) dst Double-decrement destination dst - 2 → dst * * * *19 ¤ DINT Disable interrupts 0 → GIE - - - -20 ¤ EINT Enable interrupts 1 → GIE - - - -21 ¤ INC(.B) dst Increment destination dst +1 → dst * * * *22 ¤ INCD(.B) dst Double-increment destination dst+2 → dst * * * *23 ¤ INV(.B) dst Invert destination .not.dst → dst * * * *24 JC/JHS label Jump if C set/Jump if higher or same - - - -25 JEQ/JZ label Jump if equal/Jump if Z set - - - -26 JGE label Jump if greater or equal - - - -27 JL label Jump if less - - - -28 JMP label Jump PC + 2 × offset → PC - - - -29 JN label Jump if N set - - - -30 JNC/JLO label Jump if C not set/Jump if lower - - - -31 JNE/JNZ label Jump if not equal/Jump if Z not set - - - -32 MOV(.B) src,dst Move source to destination src → dst - - - -33 ¤ NOP No operation - - - -34 ¤ POP(.B) dst Pop item from stack to destination @SP → dst, SP+2 → SP - - - -35 PUSH(.B) src Push source onto stack SP - 2 → SP, src → @SP - - - -36 ¤ RET Return from subroutine @SP → PC, SP + 2 → SP - - - -37 RETI Return from interrupt * * * *38 ¤ RLA(.B) dst Rotate left arithmetically * * * *39 ¤ RLC(.B) dst Rotate left through C * * * *40 RRA(.B) dst Rotate right arithmetically 0 * * *41 RRC(.B) dst Rotate right through C * * * *42 ¤ SBC(.B) dst Subtract not(C) from destination dst + 0FFFFh + C → dst * * * *43 ¤ SETC Set C 1→C - - - 144 ¤ SETN Set N 1→N - 1 - -45 ¤ SETZ Set Z 1→Z - - 1 -46 SUB(.B) src,dst Subtract source from destination dst + .not.src + 1 → dst * * * *47 SUBC(.B) src,dst Subtract source and not(C) from dst dst + .not.src + C → dst * * * *48 SWPB dst Swap bytes - - - -49 SXT dst Extend sign 0 * * *50 ¤ TST(.B) dst Test destination dst+0FFFFh+1 0 * * 151 XOR(.B) src,dst Exclusive OR source and destination src .xor. dst → dst * * * *

Description

-‐ not affected* changes based on opSpecial Registers: PC (Program Counter)=R0; SP (Stack Pointer)=R1;

SR (Status Register)=R2; CG (Constants Generator)=R3;

www.ti.com CPU Registers

Figure 3-6. Status Register Bits15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OSC CPUReserved V SCG1 SCG0 GIE N Z COFF OFFrw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0

Table 3-1 describes the status register bits.

Table 3-1. Description of Status Register BitsBit DescriptionV Overflow bit. This bit is set when the result of an arithmetic operation overflows the signed-variable range.

Set when:ADD(.B),ADDC(.B)Positive + Positive = NegativeNegative + Negative = PositiveOtherwise resetSet when:SUB(.B),SUBC(.B),CMP(.B)Positive – Negative = NegativeNegative – Positive = PositiveOtherwise reset

SCG1 System clock generator 1. When set, turns off the SMCLK.SCG0 System clock generator 0. When set, turns off the DCO dc generator, if DCOCLK is not used for MCLK or SMCLK.OSCOFF Oscillator Off. When set, turns off the LFXT1 crystal oscillator, when LFXT1CLK is not use for MCLK or SMCLK.CPUOFF CPU off. When set, turns off the CPU.GIE General interrupt enable. When set, enables maskable interrupts. When reset, all maskable interrupts are disabled.N Negative bit. Set when the result of a byte or word operation is negative and cleared when the result is not negative.

Word operation: N is set to the value of bit 15 of the result.Byte operation: N is set to the value of bit 7 of the result.

Z Zero bit. Set when the result of a byte or word operation is 0 and cleared when the result is not 0.C Carry bit. Set when the result of a byte or word operation produced a carry and cleared when no carry occurred.

3.2.4 Constant Generator Registers CG1 and CG2Six commonly-used constants are generated with the constant generator registers R2 and R3, withoutrequiring an additional 16-bit word of program code. The constants are selected with the source-registeraddressing modes (As), as described in Table 3-2.

Table 3-2. Values of Constant Generators CG1, CG2Register As Constant Remarks

R2 00 – – – – – Register modeR2 01 (0) Absolute address modeR2 10 00004h +4, bit processingR2 11 00008h +8, bit processingR3 00 00000h 0, word processingR3 01 00001h +1R3 10 00002h +2, bit processingR3 11 0FFFFh 1, word processing

The constant generator advantages are:• No special instructions required• No additional code word for the six constants• No code memory access required to retrieve the constant

49SLAU144I–December 2004–Revised January 2012 CPUSubmit Documentation Feedback


Active Mode

CPU Is Active

Peripheral Modules Are Active

LPM0

CPU Off, MCLK Off,

SMCLK On, ACLK On

CPUOFF = 1

SCG0 = 0

SCG1 = 0

CPUOFF = 1

SCG0 = 1

SCG1 = 0

LPM2

CPU Off, MCLK Off, SMCLK

Off, DCO Off, ACLK On

CPUOFF = 1

SCG0 = 0

SCG1 = 1LPM3

CPU Off, MCLK Off, SMCLK

Off, DCO Off, ACLK On

DC Generator Off

LPM4

CPU Off, MCLK Off, DCO

Off, SMCLK Off,

ACLK Off

DC Generator Off

CPUOFF = 1

OSCOFF = 1

SCG0 = 1

SCG1 = 1

RST/NMI

NMI Active

PUC RST/NMI is Reset Pin

WDT is Active

POR

WDT Active,

Security Key Violation

WDT

Time Expired, Overflow WDTIFG = 1

WDTIFG = 1

RST/NMI

Reset ActiveSVS_POR

WDTIFG = 0

LPM1

CPU Off, MCLK Off,

DCO off, SMCLK On,

ACLK On

DC Generator Off if DCO

not used for SMCLK

CPUOFF = 1

SCG0 = 1

SCG1 = 1

Operating Modes www.ti.com

Figure 2-9. Operating Modes For Basic Clock System

Table 2-2. Operating Modes For Basic Clock SystemSCG1 SCG0 OSCOFF CPUOFF Mode CPU and Clocks Status

0 0 0 0 Active CPU is active, all enabled clocks are active0 0 0 1 LPM0 CPU, MCLK are disabled, SMCLK, ACLK are active

CPU, MCLK are disabled. DCO and DC generator are0 1 0 1 LPM1 disabled if the DCO is not used for SMCLK. ACLK is

active.CPU, MCLK, SMCLK, DCO are disabled. DC generator1 0 0 1 LPM2 remains enabled. ACLK is active.CPU, MCLK, SMCLK, DCO are disabled. DC generator1 1 0 1 LPM3 disabled. ACLK is active.

1 1 1 1 LPM4 CPU and all clocks disabled

42 System Resets, Interrupts, and Operating Modes SLAU144I–December 2004–Revised January 2012Submit Documentation Feedback


Low Power Modes

Pulldown

Vo=0

Pullup

Vo=1Functions, Interrupts, and Low-Power Modes 189

2. The PC, which points to the next instruction, is pushed onto the stack.

3. The SR is pushed onto the stack.

4. The interrupt with the highest priority is selected if multiple interrupts are waitingfor service.

5. The interrupt request flag is cleared automatically for vectors that have a singlesource. Flags remain set for servicing by software if the vector has multiplesources, which applies to the example of TAIFG.

6. The SR is cleared, which has two effects. First, further maskable interrupts aredisabled because the GIE bit is cleared; nonmaskable interrupts remain active.Second, it terminates any low-power mode, as explained in the section“Low-Power Modes of Operation” on page 198. (The SCG0 bit is not cleared inthe MSP430x4xx family, which means that the frequency-locked loop is notautomatically reactivated; see “Frequency-Locked Loop, FLL+” on page 172.)

7. The interrupt vector is loaded into the PC and the CPU starts to execute theinterrupt service routine at that address.

This sequence takes six clock cycles in the MSP430 before the ISR commences. The stackat this point is shown in Figure 6.5. The position of SR on the stack is important if thelow-power mode of operation needs to be changed.

The delay between an interrupt being requested and the start of the ISR is called thelatency. If the CPU is already running it is given by the time to execute the currentinstruction, which might only just have started when the interrupt was requested, plus thesix cycles needed to execute the launch sequence. This should be calculated for the slowestinstruction to get the worst case. Format I instructions take up to 6 clock cycles so theoverall latency is 12 cycles. The time required to start MCLK replaces the duration of the

(a) Before interrupt (b) After entering interrupt

return addressstatus register

SP←

SP←

Figure 6.5: Stack before and after entering an interrupt service routine. The returnaddress (PC) and status register (SR) have been saved, with SR on the top of thestack.

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www.ti.com USCI Operation: UART Mode

15.3.13 Typical Baud Rates and ErrorsStandard baud rate data for UCBRx, UCBRSx and UCBRFx are listed in Table 15-4 and Table 15-5 for a32768-Hz crystal sourcing ACLK and typical SMCLK frequencies. Ensure that the selected BRCLKfrequency does not exceed the device-specific maximum USCI input frequency (see the device-specificdata sheet).The receive error is the accumulated time versus the ideal scanning time in the middle of each bit. Theworst case error is given for the reception of an 8-bit character with parity and one stop bit includingsynchronization error.The transmit error is the accumulated timing error versus the ideal time of the bit period. The worst caseerror is given for the transmission of an 8-bit character with parity and stop bit.

Table 15-4. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0BRCLK Baud RateFrequency UCBRx UCBRSx UCBRFx Maximum TX Error [%] Maximum RX Error [%][Baud][Hz]32,768 1200 27 2 0 -2.8 1.4 -5.9 2.032,768 2400 13 6 0 -4.8 6.0 -9.7 8.332,768 4800 6 7 0 -12.1 5.7 -13.4 19.032,768 9600 3 3 0 -21.1 15.2 -44.3 21.3

1,048,576 9600 109 2 0 -0.2 0.7 -1.0 0.81,048,576 19200 54 5 0 -1.1 1.0 -1.5 2.51,048,576 38400 27 2 0 -2.8 1.4 -5.9 2.01,048,576 56000 18 6 0 -3.9 1.1 -4.6 5.71,048,576 115200 9 1 0 -1.1 10.7 -11.5 11.31,048,576 128000 8 1 0 -8.9 7.5 -13.8 14.81,048,576 256000 4 1 0 -2.3 25.4 -13.4 38.81,000,000 9600 104 1 0 -0.5 0.6 -0.9 1.21,000,000 19200 52 0 0 -1.8 0 -2.6 0.91,000,000 38400 26 0 0 -1.8 0 -3.6 1.81,000,000 56000 17 7 0 -4.8 0.8 -8.0 3.21,000,000 115200 8 6 0 -7.8 6.4 -9.7 16.11,000,000 128000 7 7 0 -10.4 6.4 -18.0 11.61,000,000 256000 3 7 0 -29.6 0 -43.6 5.24,000,000 9600 416 6 0 -0.2 0.2 -0.2 0.44,000,000 19200 208 3 0 -0.2 0.5 -0.3 0.84,000,000 38400 104 1 0 -0.5 0.6 -0.9 1.24,000,000 56000 71 4 0 -0.6 1.0 -1.7 1.34,000,000 115200 34 6 0 -2.1 0.6 -2.5 3.14,000,000 128000 31 2 0 -0.8 1.6 -3.6 2.04,000,000 256000 15 5 0 -4.0 3.2 -8.4 5.28,000,000 9600 833 2 0 -0.1 0 -0.2 0.18,000,000 19200 416 6 0 -0.2 0.2 -0.2 0.48,000,000 38400 208 3 0 -0.2 0.5 -0.3 0.88,000,000 56000 142 7 0 -0.6 0.1 -0.7 0.88,000,000 115200 69 4 0 -0.6 0.8 -1.8 1.18,000,000 128000 62 4 0 -0.8 0 -1.2 1.28,000,000 256000 31 2 0 -0.8 1.6 -3.6 2.012,000,000 9600 1250 0 0 0 0 -0.05 0.0512,000,000 19200 625 0 0 0 0 -0.2 012,000,000 38400 312 4 0 -0.2 0 -0.2 0.212,000,000 56000 214 2 0 -0.3 0.2 -0.4 0.5

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www.ti.com USCI Operation: UART Mode

15.3.13 Typical Baud Rates and ErrorsStandard baud rate data for UCBRx, UCBRSx and UCBRFx are listed in Table 15-4 and Table 15-5 for a32768-Hz crystal sourcing ACLK and typical SMCLK frequencies. Ensure that the selected BRCLKfrequency does not exceed the device-specific maximum USCI input frequency (see the device-specificdata sheet).The receive error is the accumulated time versus the ideal scanning time in the middle of each bit. Theworst case error is given for the reception of an 8-bit character with parity and one stop bit includingsynchronization error.The transmit error is the accumulated timing error versus the ideal time of the bit period. The worst caseerror is given for the transmission of an 8-bit character with parity and stop bit.

Table 15-4. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0BRCLK Baud RateFrequency UCBRx UCBRSx UCBRFx Maximum TX Error [%] Maximum RX Error [%][Baud][Hz]32,768 1200 27 2 0 -2.8 1.4 -5.9 2.032,768 2400 13 6 0 -4.8 6.0 -9.7 8.332,768 4800 6 7 0 -12.1 5.7 -13.4 19.032,768 9600 3 3 0 -21.1 15.2 -44.3 21.3

1,048,576 9600 109 2 0 -0.2 0.7 -1.0 0.81,048,576 19200 54 5 0 -1.1 1.0 -1.5 2.51,048,576 38400 27 2 0 -2.8 1.4 -5.9 2.01,048,576 56000 18 6 0 -3.9 1.1 -4.6 5.71,048,576 115200 9 1 0 -1.1 10.7 -11.5 11.31,048,576 128000 8 1 0 -8.9 7.5 -13.8 14.81,048,576 256000 4 1 0 -2.3 25.4 -13.4 38.81,000,000 9600 104 1 0 -0.5 0.6 -0.9 1.21,000,000 19200 52 0 0 -1.8 0 -2.6 0.91,000,000 38400 26 0 0 -1.8 0 -3.6 1.81,000,000 56000 17 7 0 -4.8 0.8 -8.0 3.21,000,000 115200 8 6 0 -7.8 6.4 -9.7 16.11,000,000 128000 7 7 0 -10.4 6.4 -18.0 11.61,000,000 256000 3 7 0 -29.6 0 -43.6 5.24,000,000 9600 416 6 0 -0.2 0.2 -0.2 0.44,000,000 19200 208 3 0 -0.2 0.5 -0.3 0.84,000,000 38400 104 1 0 -0.5 0.6 -0.9 1.24,000,000 56000 71 4 0 -0.6 1.0 -1.7 1.34,000,000 115200 34 6 0 -2.1 0.6 -2.5 3.14,000,000 128000 31 2 0 -0.8 1.6 -3.6 2.04,000,000 256000 15 5 0 -4.0 3.2 -8.4 5.28,000,000 9600 833 2 0 -0.1 0 -0.2 0.18,000,000 19200 416 6 0 -0.2 0.2 -0.2 0.48,000,000 38400 208 3 0 -0.2 0.5 -0.3 0.88,000,000 56000 142 7 0 -0.6 0.1 -0.7 0.88,000,000 115200 69 4 0 -0.6 0.8 -1.8 1.18,000,000 128000 62 4 0 -0.8 0 -1.2 1.28,000,000 256000 31 2 0 -0.8 1.6 -3.6 2.012,000,000 9600 1250 0 0 0 0 -0.05 0.0512,000,000 19200 625 0 0 0 0 -0.2 012,000,000 38400 312 4 0 -0.2 0 -0.2 0.212,000,000 56000 214 2 0 -0.3 0.2 -0.4 0.5



USCI Operation: UART Mode www.ti.com

Table 15-4. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 (continued)BRCLK Baud RateFrequency UCBRx UCBRSx UCBRFx Maximum TX Error [%] Maximum RX Error [%][Baud][Hz]

12,000,000 115200 104 1 0 -0.5 0.6 -0.9 1.212,000,000 128000 93 6 0 -0.8 0 -1.5 0.412,000,000 256000 46 7 0 -1.9 0 -2.0 2.016,000,000 9600 1666 6 0 -0.05 0.05 -0.05 0.116,000,000 19200 833 2 0 -0.1 0.05 -0.2 0.116,000,000 38400 416 6 0 -0.2 0.2 -0.2 0.416,000,000 56000 285 6 0 -0.3 0.1 -0.5 0.216,000,000 115200 138 7 0 -0.7 0 -0.8 0.616,000,000 128000 125 0 0 0 0 -0.8 016,000,000 256000 62 4 0 -0.8 0 -1.2 1.2

Table 15-5. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 1BRCLK Baud RateFrequency UCBRx UCBRSx UCBRFx Maximum TX Error [%] Maximum RX Error [%][Baud][Hz]

1,048,576 9600 6 0 13 -2.3 0 -2.2 0.81,048,576 19200 3 1 6 -4.6 3.2 -5.0 4.71,000,000 9600 6 0 8 -1.8 0 -2.2 0.41,000,000 19200 3 0 4 -1.8 0 -2.6 0.91,000,000 57600 1 7 0 -34.4 0 -33.4 04,000,000 9600 26 0 1 0 0.9 0 1.14,000,000 19200 13 0 0 -1.8 0 -1.9 0.24,000,000 38400 6 0 8 -1.8 0 -2.2 0.44,000,000 57600 4 5 3 -3.5 3.2 -1.8 6.44,000,000 115200 2 3 2 -2.1 4.8 -2.5 7.34,000,000 230400 1 7 0 -34.4 0 -33.4 08,000,000 9600 52 0 1 -0.4 0 -0.4 0.18,000,000 19200 26 0 1 0 0.9 0 1.18,000,000 38400 13 0 0 -1.8 0 -1.9 0.28,000,000 57600 8 0 11 0 0.88 0 1.68,000,000 115200 4 5 3 -3.5 3.2 -1.8 6.48,000,000 230400 2 3 2 -2.1 4.8 -2.5 7.38,000,000 460800 1 7 0 -34.4 0 -33.4 012,000,000 9600 78 0 2 0 0 -0.05 0.0512,000,000 19200 39 0 1 0 0 0 0.212,000,000 38400 19 0 8 -1.8 0 -1.8 0.112,000,000 57600 13 0 0 -1.8 0 -1.9 0.212,000,000 115200 6 0 8 -1.8 0 -2.2 0.412,000,000 230400 3 0 4 -1.8 0 -2.6 0.916,000,000 9600 104 0 3 0 0.2 0 0.316,000,000 19200 52 0 1 -0.4 0 -0.4 0.116,000,000 38400 26 0 1 0 0.9 0 1.116,000,000 57600 17 0 6 0 0.9 -0.1 1.016,000,000 115200 8 0 11 0 0.9 0 1.616,000,000 230400 4 5 3 -3.5 3.2 -1.8 6.416,000,000 460800 2 3 2 -2.1 4.8 -2.5 7.3

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Table 15-4. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 (continued)BRCLK Baud RateFrequency UCBRx UCBRSx UCBRFx Maximum TX Error [%] Maximum RX Error [%][Baud][Hz]

12,000,000 115200 104 1 0 -0.5 0.6 -0.9 1.212,000,000 128000 93 6 0 -0.8 0 -1.5 0.412,000,000 256000 46 7 0 -1.9 0 -2.0 2.016,000,000 9600 1666 6 0 -0.05 0.05 -0.05 0.116,000,000 19200 833 2 0 -0.1 0.05 -0.2 0.116,000,000 38400 416 6 0 -0.2 0.2 -0.2 0.416,000,000 56000 285 6 0 -0.3 0.1 -0.5 0.216,000,000 115200 138 7 0 -0.7 0 -0.8 0.616,000,000 128000 125 0 0 0 0 -0.8 016,000,000 256000 62 4 0 -0.8 0 -1.2 1.2

Table 15-5. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 1BRCLK Baud RateFrequency UCBRx UCBRSx UCBRFx Maximum TX Error [%] Maximum RX Error [%][Baud][Hz]

1,048,576 9600 6 0 13 -2.3 0 -2.2 0.81,048,576 19200 3 1 6 -4.6 3.2 -5.0 4.71,000,000 9600 6 0 8 -1.8 0 -2.2 0.41,000,000 19200 3 0 4 -1.8 0 -2.6 0.91,000,000 57600 1 7 0 -34.4 0 -33.4 04,000,000 9600 26 0 1 0 0.9 0 1.14,000,000 19200 13 0 0 -1.8 0 -1.9 0.24,000,000 38400 6 0 8 -1.8 0 -2.2 0.44,000,000 57600 4 5 3 -3.5 3.2 -1.8 6.44,000,000 115200 2 3 2 -2.1 4.8 -2.5 7.34,000,000 230400 1 7 0 -34.4 0 -33.4 08,000,000 9600 52 0 1 -0.4 0 -0.4 0.18,000,000 19200 26 0 1 0 0.9 0 1.18,000,000 38400 13 0 0 -1.8 0 -1.9 0.28,000,000 57600 8 0 11 0 0.88 0 1.68,000,000 115200 4 5 3 -3.5 3.2 -1.8 6.48,000,000 230400 2 3 2 -2.1 4.8 -2.5 7.38,000,000 460800 1 7 0 -34.4 0 -33.4 012,000,000 9600 78 0 2 0 0 -0.05 0.0512,000,000 19200 39 0 1 0 0 0 0.212,000,000 38400 19 0 8 -1.8 0 -1.8 0.112,000,000 57600 13 0 0 -1.8 0 -1.9 0.212,000,000 115200 6 0 8 -1.8 0 -2.2 0.412,000,000 230400 3 0 4 -1.8 0 -2.6 0.916,000,000 9600 104 0 3 0 0.2 0 0.316,000,000 19200 52 0 1 -0.4 0 -0.4 0.116,000,000 38400 26 0 1 0 0.9 0 1.116,000,000 57600 17 0 6 0 0.9 -0.1 1.016,000,000 115200 8 0 11 0 0.9 0 1.616,000,000 230400 4 5 3 -3.5 3.2 -1.8 6.416,000,000 460800 2 3 2 -2.1 4.8 -2.5 7.3



www.ti.com USCI Registers: UART Mode

15.4.2 UCAxCTL1, USCI_Ax Control Register 1

7 6 5 4 3 2 1 0UCSSELx UCRXEIE UCBRKIE UCDORM UCTXADDR UCTXBRK UCSWRST

rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-1

UCSSELx Bits 7-6 USCI clock source select. These bits select the BRCLK source clock.00 UCLK01 ACLK10 SMCLK11 SMCLK

UCRXEIE Bit 5 Receive erroneous-character interrupt-enable0 Erroneous characters rejected and UCAxRXIFG is not set1 Erroneous characters received will set UCAxRXIFG

UCBRKIE Bit 4 Receive break character interrupt-enable0 Received break characters do not set UCAxRXIFG.1 Received break characters set UCAxRXIFG.

UCDORM Bit 3 Dormant. Puts USCI into sleep mode.0 Not dormant. All received characters will set UCAxRXIFG.1 Dormant. Only characters that are preceded by an idle-line or with address bit set will set

UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a breakand synch field will set UCAxRXIFG.

UCTXADDR Bit 2 Transmit address. Next frame to be transmitted will be marked as address depending on the selectedmultiprocessor mode.0 Next frame transmitted is data1 Next frame transmitted is an address

UCTXBRK Bit 1 Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automaticbaud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields.Otherwise 0h must be written into the transmit buffer.0 Next frame transmitted is not a break1 Next frame transmitted is a break or a break/synch

UCSWRST Bit 0 Software reset enable0 Disabled. USCI reset released for operation.1 Enabled. USCI logic held in reset state.

15.4.3 UCAxBR0, USCI_Ax Baud Rate Control Register 0

7 6 5 4 3 2 1 0UCBRx

rw rw rw rw rw rw rw rw


7 6 5 4 3 2 1 0UCBRx


UCBRx 7-0 Clock prescaler setting of the Baud rate generator. The 16-bit value of (UCAxBR0 + UCAxBR1 × 256) formsthe prescaler value.


















7 6 5 4 3 2 1 0UCBRx



7 6 5 4 3 2 1 0UCBRx


















7 6 5 4 3 2 1 0UCBRx



7 6 5 4 3 2 1 0UCBRx


















7 6 5 4 3 2 1 0UCBRx



7 6 5 4 3 2 1 0UCBRx




Copyright © 2004–2012, Texas Instruments Incorporatedwww.ti.com USCI Registers: UART Mode

15.4.7 UCAxRXBUF, USCI_Ax Receive Buffer Register

7 6 5 4 3 2 1 0UCRXBUFx


UCRXBUFx Bits 7-0 The receive-data buffer is user accessible and contains the last received character from the receive shiftregister. Reading UCAxRXBUF resets the receive-error bits, the UCADDR or UCIDLE bit, and UCAxRXIFG.In 7-bit data mode, UCAxRXBUF is LSB justified and the MSB is always reset.

15.4.8 UCAxTXBUF, USCI_Ax Transmit Buffer Register

7 6 5 4 3 2 1 0UCTXBUFx


UCTXBUFx Bits 7-0 The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shiftregister and transmitted on UCAxTXD. Writing to the transmit data buffer clears UCAxTXIFG. The MSB ofUCAxTXBUF is not used for 7-bit data and is reset.

15.4.9 UCAxIRTCTL, USCI_Ax IrDA Transmit Control Register

7 6 5 4 3 2 1 0UCIRTXPLx UCIRTXCLK UCIREN


UCIRTXPLx Bits 7-2 Transmit pulse length. Pulse length tPULSE = (UCIRTXPLx + 1) / (2 × fIRTXCLK)UCIRTXCLK Bit 1 IrDA transmit pulse clock select

0 BRCLK1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK

UCIREN Bit 0 IrDA encoder/decoder enable.0 IrDA encoder/decoder disabled1 IrDA encoder/decoder enabled

15.4.10 UCAxIRRCTL, USCI_Ax IrDA Receive Control Register

7 6 5 4 3 2 1 0UCIRRXFLx UCIRRXPL UCIRRXFE


UCIRRXFLx Bits 7-2 Receive filter length. The minimum pulse length for receive is given by: tMIN = (UCIRRXFLx + 4) / (2 ×fIRTXCLK)

UCIRRXPL Bit 1 IrDA receive input UCAxRXD polarity0 IrDA transceiver delivers a high pulse when a light pulse is seen1 IrDA transceiver delivers a low pulse when a light pulse is seen

UCIRRXFE Bit 0 IrDA receive filter enabled0 Receive filter disabled1 Receive filter enabled





7 6 5 4 3 2 1 0UCRXBUFx




7 6 5 4 3 2 1 0UCTXBUFx



















7 6 5 4 3 2 1 0UCRXBUFx




7 6 5 4 3 2 1 0UCTXBUFx



















7 6 5 4 3 2 1 0UCRXBUFx




7 6 5 4 3 2 1 0UCTXBUFx

















USCI Registers: UART Mode www.ti.com

15.4.11 UCAxABCTL, USCI_Ax Auto Baud Rate Control Register

7 6 5 4 3 2 1 0Reserved UCDELIMx UCSTOE UCBTOE Reserved UCABDEN

r-0 r-0 rw-0 rw-0 rw-0 rw-0 r-0 rw-0

Reserved Bits 7-6 ReservedUCDELIMx Bits 5-4 Break/synch delimiter length

00 1 bit time01 2 bit times10 3 bit times11 4 bit times

UCSTOE Bit 3 Synch field time out error0 No error1 Length of synch field exceeded measurable time.

UCBTOE Bit 2 Break time out error0 No error1 Length of break field exceeded 22 bit times.

Reserved Bit 1 ReservedUCABDEN Bit 0 Automatic baud rate detect enable

0 Baud rate detection disabled. Length of break and synch field is not measured.1 Baud rate detection enabled. Length of break and synch field is measured and baud rate settings

are changed accordingly.

15.4.12 IE2, Interrupt Enable Register 2

7 6 5 4 3 2 1 0UCA0TXIE UCA0RXIE

rw-0 rw-0

Bits 7-2 These bits may be used by other modules (see the device-specific data sheet).UCA0TXIE Bit 1 USCI_A0 transmit interrupt enable

0 Interrupt disabled1 Interrupt enabled

UCA0RXIE Bit 0 USCI_A0 receive interrupt enable0 Interrupt disabled1 Interrupt enabled

15.4.13 IFG2, Interrupt Flag Register 2

7 6 5 4 3 2 1 0UCA0TXIFG UCA0RXIFG

rw-1 rw-0

Bits 7-2 These bits may be used by other modules (see the device-specific data sheet).UCA0TXIFG Bit 1 USCI_A0 transmit interrupt flag. UCA0TXIFG is set when UCA0TXBUF is empty.

0 No interrupt pending1 Interrupt pending

UCA0RXIFG Bit 0 USCI_A0 receive interrupt flag. UCA0RXIFG is set when UCA0RXBUF has received a complete character.0 No interrupt pending1 Interrupt pending






r-0 r-0 rw-0 rw-0 rw-0 rw-0 r-0 rw-0










rw-0 rw-0






rw-1 rw-0









r-0 r-0 rw-0 rw-0 rw-0 rw-0 r-0 rw-0










rw-0 rw-0






rw-1 rw-0









r-0 r-0 rw-0 rw-0 rw-0 rw-0 r-0 rw-0










rw-0 rw-0






rw-1 rw-0






Serial_MSP.cvoid serial_init(void) { P1SEL = 0x04; // Select UART as the pin function P1SEL2 = 0x04; UCA0CTL1|=UCSWRST; //DisableUARTmoduleforconfiguration UCA0CTL0=0x00; //Noparity,LSBfirst,8-bitdata,1stopbit,UART,Asynchronous UCA0CTL1 |= 0xC0; // SMCLK source, keep in reset state UCA0BR0=104; //9600Baudrate-Assumes1MHzclocks(1000000/9600=104) UCA0MCTL=0x02; //2ndStagemodulation=1,Oversamplingoff IE2 = 0x00; // Interrupts disabled UCA0CTL1 &= ~UCSWRST; // Enable UART module}void serial_charTX(char c) { while( !(IFG2 & UCA0TXIFG) ); // Wait until the transmit buffer is emptyUCA0TXBUF=c; //SendthecharacterthroughtheXmitbuffer}void clock_init(void) { DCOCTL=0x00; BCSCTL1=CALBC1_1MHZ; //Calibrateto1MHz DCOCTL=CALDCO_1MHZ;}mainTX.c#include<msp430g2553.h>#include“serial_msp.h”voidmain(void){ WDTCTL=WDTHOLD+WDTPW; //StopWatchdogtimer P1DIR|=BIT0+BIT6; //ConfigureLEDpinsasoutputs P1OUT&=~(BIT0+BIT6); //TurnoffLEDs P2DIR&=~(BIT0+BIT1+BIT2); //Makebuttonpinsasinputs clock_init(); //Setclockfrequencyto1MHz serial_init(); //InitializeUARTmodule while(1) { if( (P2IN & BIT2) == BIT2) { serial_charTX(‘r’); P1OUT|=(BIT0+BIT6); //TurnonBOTHLEDs __delay_cycles(1000000); } if( (P2IN & BIT1) == BIT1) { serial_charTX(‘i’); P1OUT|=BIT6; //TurnOngreenLED P1OUT&=~BIT0; //TurnOffredLED __delay_cycles(1000000); } if( (P2IN & BIT0) == BIT0) { serial_charTX(‘d’); P1OUT|=BIT0; //TurnOnredLED P1OUT&=~BIT6; //TurnOffgreenLED __delay_cycles(1000000); } else { P1OUT&=~(BIT0+BIT6); //TurnonLEDs } }}Serial_MSP_Interrupt.cvoid serial_init_inter(void) { P1SEL = 0x02; P1SEL2 = 0x02; UCA0CTL1|=UCSWRST; //DisableUARTmoduleforconfiguration UCA0CTL0=0x00; //Noparity,LSBfirst,8-bitdata,1stopbit,UART,Asynchronous UCA0CTL1 |= 0xc0; // SMCLK source, keep in reset state UCA0BR0=104; //9600Baudrate -Assumes1MHzclock UCA0MCTL=0x02; //2ndStagemodulation=1,Oversamplingoff UCA0CTL1 &= ~UCSWRST; // Enable UART module}char serial_charRX(void) { while(!(IFG2&UCA0RXIFG)); //Waituntilacharacterhasbeenreceived returnUCA0RXBUF; //Returnreceivedcharacter}void clock_init(void) { DCOCTL=0x00; BCSCTL1=CALBC1_1MHZ;//Calibrateto1MHz DCOCTL=CALDCO_1MHZ; BCSCTL1|=XT2OFF+DIVA_0; BCSCTL3=XT2S_0+LFXT1S_2+XCAP_1;}mainRX.c#include<msp430g2553.h>#include“Serial_MSP_Interrupt.h”void main(void) { WDTCTL=WDTHOLD+WDTPW; //StopWatchdogtimer P1DIR|=BIT0+BIT6; //ConfigureLEDpinsasoutputs P1OUT&=~(BIT0+BIT6); //TurnoffLEDs clock_init(); //Setclockfrequencyto1MHz serial_init_inter(); //InitializeUARTmodule IFG2 &= ~(UCA0RXIFG); IE2 |= UCA0RXIE; // Enable UART interrupt __bis_SR_register(GIE); while(1) { }}#pragmavector=USCIAB0RX_VECTOR//interruptvectorroutine__interrupt void RX_Function(void) { char c; while(!(IFG2&UCA0RXIFG));//ThisshouldmaketheCPUwaitsincetheflagshouldbesetalready c=UCA0RXBUF; //Storereceivedcharacter switch(c) { case ‘r’: // Reset the counter P1OUT|=(BIT0+BIT6); //TurnoffLEDs break; case ‘i’: P1OUT|=BIT6; //TurnOngreenLED P1OUT&=~BIT0; //TurnOffredLED break; case ‘d’: P1OUT|=BIT0; //TurnOnredLED P1OUT&=~BIT6; //TurnOffgreenLED break; default: P1OUT&=~(BIT0+BIT6); //TurnoffLEDs break; }}

188 Chapter 6

F2013 as an example, the vector for TACCR0 CCIFG has an address 0xFFF2 andtherefore has a higher priority than the shared vector for TAIFG and TACCR1 CCIFG,whose address is 0xFFF0. Five other vectors are used in this device to give a total of 9,although space for up to 32 is reserved (16 in older devices).

Interrupts must be handled in such a way that the code that was interrupted can be resumedwithout error. This means in particular that the values in the CPU registers must berestored. The hardware can take two extreme approaches to this:

• Copies of all the registers are saved on the stack automatically as part of theprocess for entering an interrupt. This is done in the Freescale HCS08, for example,which is a CISC and has only a few registers. The disadvantage is the timerequired, which means that the response to an interrupt is delayed. An alternative isto switch to a second set of registers, which is done in the Z80 and descendants.

• The opposite approach is for the hardware to save only the absolute minimum,which is the return address in the PC as in a subroutine. This is much faster but it isup to the user to save and restore values of the critical registers, notably the statusregister. The Microchip PIC16 takes this approach, consistent with its minimalistphilosophy.

The MSP430 is close to the second extreme but stacks both the return address and thestatus register. The SR gets this privileged treatment because it controls the low-powermodes and the MCU must return to full power while it processes the interrupt. This isexplored further in the section “Low-Power Modes of Operation” on page 198. The otherregisters must be saved on the stack and restored if their contents are modified in the ISR.Instructions have been added to the MSP430X to push and pop multiple registers, whichmakes this process faster.

6.7 What Happens when an Interrupt Is Requested?A lengthy chain of operations lies between the cause of a maskable interrupt and the startof its ISR. It starts when a flag bit is set in the module when the condition for an interruptoccurs. For example, TAIFG is set when the counter TAR returns to 0. This is passed to thelogic that controls interrupts if the corresponding enable bit is also set, TAIE in this case.The request for an interrupt is finally passed to the CPU if the GIE bit is set. Hardwarethen performs the following steps to launch the ISR:

1. Any currently executing instruction is completed if the CPU was active when theinterrupt was requested. MCLK is started if the CPU was off.

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UCPEN Bit 7 Parity enable 0 Parity disabled. 1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In

address-bit multiprocessor mode, the address bit is included in the parity calculation.UCPAR Bit 6 Parity select. UCPAR is not used when parity is disabled. 0 Odd parity 1 Even parityUCMSB Bit 5 MSB first select. Controls the direction of the receive and transmit shift register. 0 LSB first 1 MSB firstUC7BIT Bit 4 Character length. Selects 7-bit or 8-bit character length. 0 8-bit data 1 7-bit dataUCSPB Bit 3 Stop bit select. Number of stop bits. 0 One stop bit 1 Two stop bitsUCMODEx Bits 2-1 USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0. 00 UART mode 01 Idle-line multiprocessor mode 10 Address-bit multiprocessor mode 11 UART mode with automatic baud rate detectionUCSYNC Bit 0 Synchronous mode enable 0 Asynchronous mode 1 Synchronous mode

UCSSELx Bits 7-6 USCI clock source select. These bits select the BRCLK source clock. 00 UCLK 01 ACLK 10 SMCLK 11 SMCLKUCRXEIE Bit 5 Receive erroneous-character interrupt-enable 0 Erroneous characters rejected and UCAxRXIFG is not set 1 Erroneous characters received will set UCAxRXIFGUCBRKIE Bit 4 Receive break character interrupt-enable 0 Received break characters do not set UCAxRXIFG. 1 Received break characters set UCAxRXIFG.UCDORM Bit 3 Dormant. Puts USCI into sleep mode. 0 Not dormant. All received characters will set UCAxRXIFG. 1 Dormant. Only characters that are preceded by an idle-line or with address bit set will

set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG.

UCTXADDR Bit 2 Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode.

0 Next frame transmitted is data 1 Next frame transmitted is an addressUCTXBRK Bit 1 Transmit break. Transmits a break with the next write to the transmit buffer. In UART

mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer.

0 Next frame transmitted is not a break 1 Next frame transmitted is a break or a break/synchUCSWRST Bit 0 Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state.



7 6 5 4 3 2 1 0UCPEN UCPAR UCMSB UC7BIT UCSPB UCMODEx UCSYNC


UCPEN Bit 7 Parity enable0 Parity disabled.1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit

multiprocessor mode, the address bit is included in the parity calculation.UCPAR Bit 6 Parity select. UCPAR is not used when parity is disabled.

0 Odd parity1 Even parity

UCMSB Bit 5 MSB first select. Controls the direction of the receive and transmit shift register.0 LSB first1 MSB first

UC7BIT Bit 4 Character length. Selects 7-bit or 8-bit character length.0 8-bit data1 7-bit data

UCSPB Bit 3 Stop bit select. Number of stop bits.0 One stop bit1 Two stop bits

UCMODEx Bits 2-1 USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0.00 UART mode01 Idle-line multiprocessor mode10 Address-bit multiprocessor mode11 UART mode with automatic baud rate detection

UCSYNC Bit 0 Synchronous mode enable0 Asynchronous mode1 Synchronous mode



&

UCBRx 7-0 Clock prescaler setting of the Baud rate generator. The 16-bit value of (UCAxBR0 + UCAxBR1 × 256) forms the prescaler value.

UCBRFx Bits 7-4 First modulation stage select. These bits determine the modulation pattern for BITCLK16 when UCOS16 = 1. Ignored with UCOS16 = 0. Table 15-3 shows the modulation pattern.

UCBRSx Bits 3-1 Second modulation stage select. These bits determine the modulation pattern for BITCLK. Table 15-2 shows the modulation pattern.

UCOS16 Bit 0 Oversampling mode enabled 0 Disabled 1 Enabled

UCRXBUFx Bits 7-0 The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UCAxRXBUF resets the receive-error bits, the UCADDR or UCIDLE bit, and UCAxRXIFG. In 7-bit data mode, UCAxRXBUF is LSB justified and the MSB is always reset.

UCTXBUFx Bits 7-0 The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted on UCAxTXD. Writing to the transmit data buffer clears UCAxTXIFG. The MSB of UCAxTXBUF is not used for 7-bit data and is reset.

Bits 7-2 These bits may be used by other modules (see the device-specific data sheet).UCA0TXIE Bit 1 USCI_A0 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabledUCA0RXIE Bit 0 USCI_A0 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled


15.4.5 UCAxMCTL, USCI_Ax Modulation Control Register

7 6 5 4 3 2 1 0UCBRFx UCBRSx UCOS16


UCBRFx Bits 7-4 First modulation stage select. These bits determine the modulation pattern for BITCLK16 when UCOS16 =1. Ignored with UCOS16 = 0. Table 15-3 shows the modulation pattern.

UCBRSx Bits 3-1 Second modulation stage select. These bits determine the modulation pattern for BITCLK. Table 15-2 showsthe modulation pattern.

UCOS16 Bit 0 Oversampling mode enabled0 Disabled1 Enabled

15.4.6 UCAxSTAT, USCI_Ax Status Register

7 6 5 4 3 2 1 0UCLISTEN UCFE UCOE UCPE UCBRK UCRXERR UCADDR UCBUSY

UCIDLErw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 r-0

UCLISTEN Bit 7 Listen enable. The UCLISTEN bit selects loopback mode.0 Disabled1 Enabled. UCAxTXD is internally fed back to the receiver.

UCFE Bit 6 Framing error flag0 No error1 Character received with low stop bit

UCOE Bit 5 Overrun error flag. This bit is set when a character is transferred into UCAxRXBUF before the previouscharacter was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared bysoftware. Otherwise, it will not function correctly.0 No error1 Overrun error occurred

UCPE Bit 4 Parity error flag. When UCPEN = 0, UCPE is read as 0.0 No error1 Character received with parity error

UCBRK Bit 3 Break detect flag0 No break condition1 Break condition occurred

UCRXERR Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on ormore error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read.0 No receive errors detected1 Receive error detected

UCADDR Bit 1 Address received in address-bit multiprocessor mode.0 Received character is data1 Received character is an address

UCIDLE Idle line detected in idle-line multiprocessor mode.0 No idle line detected1 Idle line detected

UCBUSY Bit 0 USCI busy. This bit indicates if a transmit or receive operation is in progress.0 USCI inactive1 USCI transmitting or receiving




15.4.5 UCAxMCTL, USCI_Ax Modulation Control Register

7 6 5 4 3 2 1 0UCBRFx UCBRSx UCOS16


UCBRFx Bits 7-4 First modulation stage select. These bits determine the modulation pattern for BITCLK16 when UCOS16 =1. Ignored with UCOS16 = 0. Table 15-3 shows the modulation pattern.

UCBRSx Bits 3-1 Second modulation stage select. These bits determine the modulation pattern for BITCLK. Table 15-2 showsthe modulation pattern.

UCOS16 Bit 0 Oversampling mode enabled0 Disabled1 Enabled

15.4.6 UCAxSTAT, USCI_Ax Status Register

7 6 5 4 3 2 1 0UCLISTEN UCFE UCOE UCPE UCBRK UCRXERR UCADDR UCBUSY

UCIDLErw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 r-0

UCLISTEN Bit 7 Listen enable. The UCLISTEN bit selects loopback mode.0 Disabled1 Enabled. UCAxTXD is internally fed back to the receiver.

UCFE Bit 6 Framing error flag0 No error1 Character received with low stop bit

UCOE Bit 5 Overrun error flag. This bit is set when a character is transferred into UCAxRXBUF before the previouscharacter was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared bysoftware. Otherwise, it will not function correctly.0 No error1 Overrun error occurred

UCPE Bit 4 Parity error flag. When UCPEN = 0, UCPE is read as 0.0 No error1 Character received with parity error

UCBRK Bit 3 Break detect flag0 No break condition1 Break condition occurred

UCRXERR Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on ormore error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read.0 No receive errors detected1 Receive error detected

UCADDR Bit 1 Address received in address-bit multiprocessor mode.0 Received character is data1 Received character is an address

UCIDLE Idle line detected in idle-line multiprocessor mode.0 No idle line detected1 Idle line detected

UCBUSY Bit 0 USCI busy. This bit indicates if a transmit or receive operation is in progress.0 USCI inactive1 USCI transmitting or receiving



Bits 7-2 These bits may be used by other modules (see the device-specific data sheet).UCA0TXIE Bit 1 USCI_A0 transmit interrupt flag. UCA0TXIFG is set when UCA0TXBUF is empty. 0 No interrupt pending 1 Interrupt pendingUCA0RXIE Bit 0 USCI_A0 receive interrupt flag. UCA0RXIFG is set when UCA0RXBUF has received a

complete character. 0 No interrupt pending 1 Interrupt pending

www.ti.com ADC10 Registers

22.3.1 ADC10CTL0, ADC10 Control Register 0

15 14 13 12 11 10 9 8SREFx ADC10SHTx ADC10SR REFOUT REFBURST

rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)

7 6 5 4 3 2 1 0MSC REF2_5V REFON ADC10ON ADC10IE ADC10IFG ENC ADC10SCrw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)

Can be modified only when ENC = 0

SREFx Bits 15-13 Select reference.000 VR+ = VCC and VR- = VSS

001 VR+ = VREF+ and VR- = VSS

010 VR+ = VeREF+ and VR- = VSS. Devices with VeREF+ only.011 VR+ = Buffered VeREF+ and VR- = VSS. Devices with VeREF+ pin only.100 VR+ = VCC and VR- = VREF-/ VeREF-. Devices with VeREF- pin only.101 VR+ = VREF+ and VR- = VREF-/ VeREF-. Devices with VeREF+/- pins only.110 VR+ = VeREF+ and VR- = VREF-/ VeREF-. Devices with VeREF+/- pins only.111 VR+ = Buffered VeREF+ and VR- = VREF-/ VeREF-. Devices with VeREF+/- pins only.

ADC10SHTx Bits 12-11 ADC10 sample-and-hold time00 4 × ADC10CLKs01 8 × ADC10CLKs10 16 × ADC10CLKs11 64 × ADC10CLKs

ADC10SR Bit 10 ADC10 sampling rate. This bit selects the reference buffer drive capability for the maximum sampling rate.Setting ADC10SR reduces the current consumption of the reference buffer.0 Reference buffer supports up to ~200 ksps1 Reference buffer supports up to ~50 ksps

REFOUT Bit 9 Reference output0 Reference output off1 Reference output on. Devices with VeREF+ / VREF+ pin only.

REFBURST Bit 8 Reference burst.0 Reference buffer on continuously1 Reference buffer on only during sample-and-conversion

MSC Bit 7 Multiple sample and conversion. Valid only for sequence or repeated modes.0 The sampling requires a rising edge of the SHI signal to trigger each sample-and-conversion.1 The first rising edge of the SHI signal triggers the sampling timer, but further

sample-and-conversions are performed automatically as soon as the prior conversion is completedREF2_5V Bit 6 Reference-generator voltage. REFON must also be set.

0 1.5 V1 2.5 V

REFON Bit 5 Reference generator on0 Reference off1 Reference on

ADC10ON Bit 4 ADC10 on0 ADC10 off1 ADC10 on

ADC10IE Bit 3 ADC10 interrupt enable0 Interrupt disabled1 Interrupt enabled

567SLAU144I–December 2004–Revised January 2012 ADC10Submit Documentation Feedback


ADC_MSP.cvoid adc_init(){ //InitializeADC P1DIR &= 0x0001; // Set Pins as inputs ADC10CTL0=ADC10ON+ADC10SHT_0+SREF_0; //configureADCmodule ADC10CTL1=CONSEQ_0+ADC10SSEL_0+ADC10DIV_0+SHS_0+INCH_0; ADC10AE0=0x0001; //Enableanalogfunctioninpins}int adc_measureAll(void) { // Return the sum of all ADC channels return(adc_measure(X_AXIS)+adc_measure(Y_AXIS)+adc_measure(Z_AXIS));}int adc_measure(int channel){ //measureselectedADCChannel:X_AXIS,Y_AXIS,Z_AXIS ADC10CTL0 &= ~ENC; // Disable ADC //ConfiguretheMUXchanneltosample ADC10CTL1=CONSEQ_0+ADC10SSEL_0+ADC10DIV_0+SHS_0+(channel<<12); ADC10CTL0|=ENC+ADC10SC; //EnableADCandstartconversion while((ADC10CTL0&ADC10IFG)==0); //Waituntiltheconversionisfinished ADC10CTL0&=~ENC; //DisableADCbeforeretrievingtheconversionfrommemory returnADC10MEM; //Returnmeasurementvalue}mainADC.c#include<msp430g2553.h>#include“adc_msp.h”#include“lcd_lib.h”void main(void) { WDTCTL=WDTPW+WDTHOLD;//StopWatchdog adc_init();//initializeAtoDconverter lcd_init();//initializeLCD P1DIR |= BIT6; send_cmd(0x0C);//disabletheblinkingcursor while(1) { int x; x=adc_measure(0);//use0forchannel0(P1.0) if(x>=512){ P1OUT|=BIT6; } else { P1OUT&=~BIT6; } delay_ms(250); gotoXy(0,0); write_int(x); write_string(“Value”); gotoXy(0,1);//Movecursorto2ndrow write_int(x); write_string(“Value”); }}

ADC10 Registers www.ti.com

ADC10IFG Bit 2 ADC10 interrupt flag. This bit is set if ADC10MEM is loaded with a conversion result. It is automatically resetwhen the interrupt request is accepted, or it may be reset by software. When using the DTC this flag is setwhen a block of transfers is completed.0 No interrupt pending1 Interrupt pending

ENC Bit 1 Enable conversion0 ADC10 disabled1 ADC10 enabled

ADC10SC Bit 0 Start conversion. Software-controlled sample-and-conversion start. ADC10SC and ENC may be set togetherwith one instruction. ADC10SC is reset automatically.0 No sample-and-conversion start1 Start sample-and-conversion

568 ADC10 SLAU144I–December 2004–Revised January 2012Submit Documentation Feedback




15 14 13 12 11 10 9 8INCHx SHSx ADC10DF ISSH


7 6 5 4 3 2 1 0ADC10DIVx ADC10SSELx CONSEQx ADC10BUSY

rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) r-0


INCHx Bits 15-12 Input channel select. These bits select the channel for a single-conversion or the highest channel for asequence of conversions. Only available ADC channels should be selected. See device specific datasheet.0000 A00001 A10010 A20011 A30100 A40101 A50110 A60111 A71000 VeREF+

1001 VREF-/VeREF-

1010 Temperature sensor1011 (VCC - VSS) / 21100 (VCC - VSS) / 2, A12 on MSP430F22xx devices1101 (VCC - VSS) / 2, A13 on MSP430F22xx devices1110 (VCC - VSS) / 2, A14 on MSP430F22xx devices1111 (VCC - VSS) / 2, A15 on MSP430F22xx devices

SHSx Bits 11-10 Sample-and-hold source select.00 ADC10SC bit01 Timer_A.OUT1(1)

10 Timer_A.OUT0(1)

11 Timer_A.OUT2 (Timer_A.OUT1 on MSP430F20x0, MSP430G2x31, and MSP430G2x30 devices)(1)

ADC10DF Bit 9 ADC10 data format0 Straight binary1 2s complement

ISSH Bit 8 Invert signal sample-and-hold0 The sample-input signal is not inverted.1 The sample-input signal is inverted.

ADC10DIVx Bits 7-5 ADC10 clock divider000 /1001 /2010 /3011 /4100 /5101 /6110 /7111 /8

ADC10SSELx Bits 4-3 ADC10 clock source select00 ADC10OSC01 ACLK10 MCLK11 SMCLK

(1) Timer triggers are from Timer0_Ax if more than one timer module exists on the device.



SP-2; PCàSP.SP-2; SRàSP









1001 VREF-/VeREF-



10 Timer_A.OUT0(1)









ADC10 Registers www.ti.com

CONSEQx Bits 2-1 Conversion sequence mode select00 Single-channel-single-conversion01 Sequence-of-channels10 Repeat-single-channel11 Repeat-sequence-of-channels

ADC10BUSY Bit 0 ADC10 busy. This bit indicates an active sample or conversion operation0 No operation is active.1 A sequence, sample, or conversion is active.

22.3.3 ADC10AE0, Analog (Input) Enable Control Register 0

7 6 5 4 3 2 1 0ADC10AE0x


ADC10AE0x Bits 7-0 ADC10 analog enable. These bits enable the corresponding pin for analog input. BIT0 corresponds to A0,BIT1 corresponds to A1, etc. The analog enable bit of not implemented channels should not be programmedto 1.0 Analog input disabled1 Analog input enabled

22.3.4 ADC10AE1, Analog (Input) Enable Control Register 1 (MSP430F22xx only)

7 6 5 4 3 2 1 0ADC10AE1x Reserved


ADC10AE1x Bits 7-4 ADC10 analog enable. These bits enable the corresponding pin for analog input. BIT4 corresponds to A12,BIT5 corresponds to A13, BIT6 corresponds to A14, and BIT7 corresponds to A15. The analog enable bit ofnot implemented channels should not be programmed to 1.0 Analog input disabled1 Analog input enabled

Reserved Bits 3-0 Reserved

22.3.5 ADC10MEM, Conversion-Memory Register, Binary Format

15 14 13 12 11 10 9 80 0 0 0 0 0 Conversion Resultsr0 r0 r0 r0 r0 r0 r r

7 6 5 4 3 2 1 0Conversion Results

r r r r r r r rConversion Bits 15-0 The 10-bit conversion results are right justified, straight-binary format. Bit 9 is the MSB. Bits 15-10 areResults always 0.

570 ADC10 SLAU144I–December 2004–Revised January 2012Submit Documentation Feedback










1001 VREF-/VeREF-



10 Timer_A.OUT0(1)









C àasm:

if(b>=5&&c==2){ do_this;} else { do_that;}

switch (myByte) { case a: do_A; break; case b: do_B; break; default: do_D; break;}

int i;for(i=10;i>0;i--){ do_dot(); delay(); do_dash(); delay();}

(J, K = integer; index for stack frame pointer) CMP #0x05,J(R7) JL do_that CMP #0x02,K(R7) JNE do_that JMP do_thisdo_that... JMP donedo_this... JMP donedone CMP #a, &myByte JNE sw_01 CALL #do_A JMP sw_endsw_01: CMP #b, &myByte JNE sw_def CALL #do_B JMP sw_endsw_def: CALL #do_D JMP sw_endsw_end: .bss i,2;2bytesglobalvariablei mov.w #10,&ifl_ck: call #do_dot call #delay call #do_dash call #delay dec &i jnz fl_ckfor_done:

C àasm:

while(i!=3){ do_it;}

for(i=0;i<64;i++){ do_rep;}

go_back CMP #0x03,J(R7) JEQ done CALL #do_it JMP go_backdone...do_it: CLR J(R7)go_back MOV J(R7),R5 CMP #0x64,R5 JGE done CALL #do_rep INC J(R7) JMP go_backdone...do_rep:

instruction set 3.4.5 instruction set description sheet mkiii.pdfas ad d/s register syntax...

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