integrated circuit design of a mixed analog digital pll

Arend Huysman

for frequency synthesisIntegrated Circuit design of a Mixed Analog Digital PLL

Academic year 2013-2014Faculty of Engineering and ArchitectureChairman: Prof. dr. ir. Jan Van CampenhoutDepartment of Electronics and Information Systems

Master of Science in Electrical EngineeringMaster's dissertation submitted in order to obtain the academic degree of

Counsellor: Dr. ir. Johan RamanSupervisor: Prof. dr. ir. Pieter Rombouts

i

Preamble

Today’s society relies more than ever on mobile high speed communications and wireless devices.

Everyone expects having a 4G internet connection in the most deserted places or use high

performance smartphones that can run the most demanding apps. Furthermore people expect

these devices to be as small as possible and use as little power as possible. While technology

evolves, designers of these devices are faced with many conflicting specifications. Constant

research into new architectures and new ideas is an absolute must to keep up with the rising

demands of the world around us. This thesis hopes to give a small contribution is this quest for

high speed communications, or at least formulate some ideas and analyses that might one day

help developing the future.

I would like to thank Pieter Rombouts, my promoter,who proposed this subject and was himself

also always willing to help. Furthermore this thesis would not have been possible without the

help of Johan Raman, who was always willing to answer any question or discuss new ideas, I

would like to thank him for his help during the year. Also the help of Amir and Dries, who

are part the team, and partook in some discussions is acknowledged. Furthermore I should also

thank friends and family, who o↵ered all the necessary support during this year.

Arend Huysman, juni 2014

iii

Permission for usage

“The author gives permission to make this master dissertation available for consultation and

to copy parts of this master dissertation for personal use. In the case of any other use, the

limitations of the copyright have to be respected, in particular with regard to the obligation to

state expressly the source when quoting results from this master dissertation.”

Arend Huysman, juni 2014

Integrated Circuit design

of a Mixed Analog Digital PLL

for frequency synthesis.

by

Arend Huysman

Master’s dissertation submitted in order to obtain the academic degree of

Master of Science in Electrical Engineering

Academic year 2013-2014

Supervisor: Prof. dr. ir. Pieter Rombouts

Counsellor: Dr. ir. Johan Raman

Faculty of Engineering and Architecture

Ghent university

Department of Electronics and Information Systems

Chariman: Prof. Dr. Ir. Jan Van Campenhout

Summary

This work tries to investigate the possibilities of using a ring oscillator in an ADPLL. By analysisof multirate phase noise, the output noise spectrum can be shaped as desired by the designerby changing the properties of digital filters. Furthermore a new TDC architecture is discussed,integrated fully within the ring oscillator. The proposed design is compared to theoretical phasenoise.

Trefwoorden

ADPLL, TDC, DCO, frequency-synthesis

Integrated Circuit design of a Mixed

Analog Digital PLL for frequency

synthesis

Arend Huysman

Supervisor: Pieter RomboutsCounsellor: Johan Raman

Abstract– This article presents an ALL

Digital Phase Locked Loop, used as fre-

quency synthesiser for frequency modula-

tion in the bluetooth range. Both a the-

oretical analysis of the loop behaviour as

an actual chip design of the analog inten-

sive parts are discussed. New design pos-

sibilities combining a ring oscillator and

TDC are explored. Spectre simulations

confirm the analysed loop behaviour.

I. Introduction

MOST high performance PLL’s today usea classical charge pump architecture. Fre-

quency synthesis is performed by dividing theoutput frequency by a digital counter. Thephase detector compares the in and outputclocks and generates a phase difference usingthe low pass charge pump (figure 1). Fractionalfrequency division is performed by dithering thedivision factor at high speed with a ⌃� modu-lator in a structure called an N-fractional PLL(figure 2). This architecture becomes harderto implement in modern CMOS technologies.This is because the voltage headroom decreases,meaning lower dynamic range for the analogsignals. Furthermore on modern day chips, alarge part is digital logic which can inject switch-ing noise into the analog parts. The sometimesvery large capacitance that are required for thecharge pump also contribute to the fact thatnew architectures are explored. A fairly recentarchitecture is the ADPLL. It will become in-creasingly interesting, since the shift towards

more digital integration will only grow in thefuture.

D Q

D Q

A

B

1

1rst

QA

QB

Figure 1: Phase detector with charge pump

PD Loop Filter VCO

Divider

Frequency control

f

out

(e.g. 2.4GHz)f

in

(50MHz)

Figure 2: Fractional-N PLL structure

II. ADPLL overview

The basic ADPLL architecture is presented infigure 3. A few important differences can im-mediately be noted. The input is a frequencycontrol word FCW, this is an exact digital word,consisting out of a defined number of bits. Ithas the same function as the division factor Nof the fractional PLL, with the difference thatit can also be a fractional number. The inputclock is not a direct input, but all digital blocksuse this reference frequency as clock. For exam-ple the FCW is accumulated at the referenceclock rate to determine the input phase. Phaseis normalised to the output oscillator frequency,

1

meaning a phase increase of 1 equals one extraclock transition. The output phase has to besampled at the reference clock transitions. It isthan substracted from the input phase. Phasedetection in the digital domain is just a subtrac-tion. A benefit of the ADPLL is that all phaseinformation is directly represented by a digitalword. Making filtering very straightforward toimplement.Analysis of loop dynamics will alsobe performed in the digital domain. Only theDCO and some parts of the phase detector arevery analog intensive and have to be designedmanually. The digital control part can be de-signed with a hardware description languageand synthesised automatically. Significantly re-ducing the design time.

⌃ Loop filterFCW �

in

��

�

out

f

n+ -

clk

ref

clk

ref

Analog time blocks

clk

ref

DCO PD

Figure 3: Basic ADPLL structure in the phase do-main

I. DCO

The digital control logic of the ADPLL gener-ates an oscillator tuning word that is also digital.The oscillator that is used in most ADPLL loopsis a DCO, or digitally controlled oscillator.Its fre-quency is controlled by switching on and off dis-crete elements using the bits of the tuning word.In most literature about ADPLL’s for frequencysynthesis in communications, the used oscillatoris a LC-oscillator. Which gives supreme resultsin terms of phase noise. However in this work adesign based on a ring oscillator (figure 4) willbe used. The tuning happens by changing thecurrent trough the ring.

V

DD

TuningDCW

Figure 4: Structure of the used ring oscillator withcurrent tuning block

Tuning is done by dynamically switching offcurrent sources (figure 5), directly using the dig-ital word. A larger current results in a fasterfrequency of the oscillator

�I

tune

I

min

2Imin

4Imin

tune2 tune1 tune0

I0

Figure 5: Switched current sources

II. TDC

The phase of the output oscillator has to beestimated at the sampling instances of the ref-erence clock. This is done by calculating howmuch the phase has changed since the last ris-ing edge. This can be done with a fractionalcounter that counts the integer phase increase.To increase the resolution a TDC is used. Thisis to convert the time between the rising edgesof the two clocks. Normally an array of delayelements is used for this purpose. Because aring oscillator already consists out of such anarray. An attempt will be made to integratethis ring oscillator directly into the TDC. Thiswill allow the use of a short delay line, with stillreasonable resolution.

III. Results

A circuit of both the DCO and the TDC is de-signed in 65 nm CMOS. The digital control logic

2

is modelled in verilog. Together they are sim-ulated in a mixed signal analysis. The phasenoise in the output spectrum is extracted andcompared with the theoretically expected phasenoise. Experiments are done both with andwithout DCO phase noise. Results are shown infigure 6 and 7. The spectrum is quite differentin both cases, DCO phase noise is dominant andstill too large for communications applications.

Figure 6: Output phase noise PSD, without DCOnoise

Figure 7: Output phase noise PSD, with DCOnoise

IV. Conclusion

A design was demonstrated implementing a ringoscillator DCO and a novel TDC implementa-tion. Phase noise analysis corresponds with thetheoretical model. The DCO itself is not suit-able for communication applications, but otherapplication such as clock generation might be

possible. Extra design effort should be put in alow phase noise ring oscillator

References

[1] Robert Bogdan Staszwski and Poras T. Bal-sara, All-Digital frequency synthesizer indeep-submicron CMOS Wiley, New Jersey,1st edition, 2006.

3

CONTENTS ix

Contents

Preamble i

Permission for usage iii

Summary v

Extended abstract vi

Used Abbreviations xiii

1 Introduction 1

1.1 Fractional-N PLL for frequency synthesis . . . . . . . . . . . . . . . . . . . . . . 2

1.2 The ADPLL structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.1 Digital Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2.2 Time to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

x CONTENTS

2 ADPLL loop analysis 7

2.1 Closed loop response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Noise behaviour in the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.1 Clock jitter and phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.2 TDC noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.3 Tuning resolution phase noise . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.4 DCO phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.5 Noise contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3 Multirate ADPLL analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.1 Multirate block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.2 Multirate transfer funtions . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3 Design of a DCO 29

3.1 Digital controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2 LC oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.3 Ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.3.1 Basic principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.3.2 Di↵erential ring oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.3.3 Design choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.4 Tuning of the ring frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.4.1 Concept of Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.4.2 Circuit implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.4.3 Designing the switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.5 Output bu↵ering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.6 Simulation verifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.7 DCO phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

CONTENTS xi

4 TDC implementation in a ring oscillator 49

4.1 Basic TDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.2 Vernier delay line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.3 Implementation in a ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.3.1 Coarse fractional phase estimation . . . . . . . . . . . . . . . . . . . . . . 52

4.3.2 Fine fractional phase estimation . . . . . . . . . . . . . . . . . . . . . . . 54

5 Digital implementation 61

5.1 Clock retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.2 Phase acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.3 Phase error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.4 Switching state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6 Experimental results and conclusion 67

6.1 PLL tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.2 Phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.2.1 Proportional filter ↵=0.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.2.2 Proportional filter ↵=1/256 . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.2.3 Type II loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.2.4 DCO noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.3 Conclusions and further work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Used Abbreviations

ADPLL All-Digital PLL

PLL Phased Locked Loop

DSP Digital Signal Processor

FCW Frequency Control Word

DCO Digital Controlled Oscillator

TDC Time to Digital Converter

PD Phase Detector

PFD Phase Frequency Detector

PWM Pulse Width Modulation

PSD Power Spectral Density

STF Signal Transfer Function

NTF Noise Transfer Function

DAC Digital to Analog Converter

DCW Digital Control Word

PHI Integer Phase word

ZOH Zero Hold Filter

SNR Signal Noise Ratio

PVT Process Voltage Temperature

NTW Normalised Tuning Word

OTW Oscillator Tuning Word

1

Chapter 1

Introduction

The PLL or Phased Locked Loop, is a well known electronic circuit that is since long used

in e.g. frequency synthesis. It is found in most of today’s integrated communication systems.

A frequency synthesiser generates a waveform with an accurately controllable stable output

frequency. While CMOS-technologies get smaller and smaller, an important issue to face is the

integration of digital processing power with the analog front-end on the same chip. This can lead

to di↵erent problems on chip, since fast switching digital electronics inject so called switching

noise in the analog parts of the system. Furthermore, while CMOS scales down the switching

becomes faster and faster, but the analog properties of these transistor get worse, they behave

less and less like standard transistor models describe. Furthermore, supply voltage is being

scaled down, which leaves less headroom for analog signals and deteriorates the SNR. Therefore,

nowadays there is a trend towards more digital based design, replacing as much of the analog

building blocks as possible by digital counterparts.

The classical PLL however is an analog intensive structure, often depending on large capacitances

used in the filters. This has resulted in the development of an All Digital Phased Locked Loop.

The basic concept is to represent all information by digital control words, which can be processed

by digital logic. For example, the analog intensive loop filters found in the classical PLL can be

replaced by digital operations on the control words. A very important contribution to ADPLL

research was performed by a team lead by Staszewski at Texas Instruments [1]. His book can

be considered as an important standard work within this domain. There are however still some

very analog dependant elements in the ADPLL, most notably the oscillator itself. In many

cases an LC-oscillator is used for reasons of better phase noise performance. This is however

2 CHAPTER 1. INTRODUCTION

less integrable in recent CMOS technologies, especially because of the inductor. In this thesis

the possibility will be investigated to use a ring oscillator, which lies closer to a digital system.

This chapter will first give a short overview of the classical PLL used in modern day frequency

synthesisers and will introduce the new structure of the ADPLL. Next chapters will first perform

a full analysis of the ADPLL in the digital domain and look at di↵erent noise sources that are

introduced in this loop. The design of an oscillator and phase detector will be discussed on circuit

level. The ADPLL will then be designed in a combination of both circuit level blocks for analog

parts and behavioural verilog code for the digital signal properties. Finally a time domain phase

noise analysis will be performed to compare the simulation results with the expected analytical

results.

1.1 Fractional-N PLL for frequency synthesis

An example of a frequency synthesiser for communication purposes is presented in figure 1.1.

The digital processor generates a baseband signal based on digital information to be transmitted

over the channel. This baseband signal modulates the carrier via frequency modulation ( or more

complex modulation techniques are possible). For example, bluetooth or GSM use a structure

like this. Because they are wireless application power consumption is an important factor. In

this work, the ADPLL will not be designed for a specific type of communication, but bluetooth

will be used as a reference to make certain design choices such as frequency bands and to compare

the resulted phase noise with the bluetooth specification. Table 1.1 lists some of the bluetooth

specifications.

Table 1.1: Bluetooth specifications

Band 2.402 - 2.480GHz

Channel spacing 1MHz

Accuracy 75 kHz

Rate 1600 hops/s

Phase noise @ 550 kHz -180 dBc/Hz

Phase noise @ 2MHz -101 dBc/Hz

Phase noise @ 3 kHz -111 dBc/Hz

1.1 Fractional-N PLL for frequency synthesis 3

DSPFCW

fref = 50 kHz

fdco = FCW.fref : around 2.4GHzFrequencySynthesizer

Figure 1.1: Basic principle of a frequency synthesiser

PD Loop Filter VCO

Divider

Frequency control

fout (e.g. 2.4GHz)fin(50MHz)

Figure 1.2: N-fractional PLL for frequency synthesis

An often used structure is the so called N-fractional PLL. It is a loop based on a PLL, equipped

with a frequency divider to generate a higher output frequency than the input. Its general

structure is shown in figure 1.2. A normal PLL would try to generate an output frequency

equal to the input frequency. By dividing the output frequency by an integer number N (this

can be easily performed by a digital counter), the loop will force the signals at the phase

detector to have the same frequency, meaning the output frequency will be N times higher. The

PLL is already partially digital since square waves are used and the phase detector is partially

implemented with digital logic.

A standard phase detector is the so called phase frequency detector, or PFD followed by a charge

pump, shown in figure 1.3. It is here, in this phase detector that the two digital clocks, A and

B are converted to an analog voltage representing the phase di↵erence. This conversion of the

PWM signals QA and QB, using the charge pump is getting problematic in modern CMOS

technologies.

Furthermore, dividing frequency with a counter can only be done with an integer factor. This

means the output resolution can only be an integer times the input frequency, resulting in a

frequency resolution of tens of MHz’s. Of course, for communication applications this is not

su�cient. Resolution in the kHz range at least is required. To solve this problem the factor N


D Q

D Q

A

B

1

1

rst

QA

QB

Figure 1.3: PSD and charge pump used in many modern PLL’s

is dithered with a high speed clock, higher than the reference signal. The frequency division

is quickly alternated between N1 and N1 + 1. The mean value of N than represents the actual

output frequency. However this inserts spurs into the system because of the periodicity of the

alternation. Higher order ⌃� modulators are used to spread out the noise over a wider frequency

band. Fractional-N PLL’s will not be discussed further in this thesis, since it will focus on the

design of an ADPLL for frequency synthesis.

1.2 The ADPLL structure

While a standard PLL is often analysed in the phase domain, there is no physical signal that

directly represents phase. The phase detector only performs an action on two oscillating signals

that generates a voltage proportional to the phase (after filtering). The basic idea of an All

Digital PLL is to represent both the input reference phase as the output oscillator phase by

an actual digital word. This is then sampled at certain fixed time instances determined by the

stable reference clock of the system. In the digital domain, it is easy to generate the phase by

accumulating the rising edges of the oscillator and just interpret the number of edges as the

phase. This phase is then sampled at the rising edge of the reference clock and compared to

a certain desired input phase. Since both phases are directly represented by a digital word,

calculating the phase di↵erence is just a digital sum, easily implemented and insensitive to

noise. This is one of the great strengths of an ADPLL, once signals are represented in the

digital domain, all subsequent operations can be modelled exactly, exploiting the full power of

1.2 The ADPLL structure 5

⌃ Loop filterFCW�in

��outfn

+ -

clkref clkref

Analog time blocks

clkref

DCO PD

Figure 1.4: General schematic layout of the ADPLL

the digital domain for a normally analog application. Figure 1.4 shows the schematic of the

ADPLL. When compared to a fractional-N PLL, there are some big di↵erences. First of all, the

input is no longer the reference clock. But it is a digital control word represented by a fixed

number of bits. The reference clock fref is not a direct input of the system, but all the digital

blocks are clocked with this signal. The FCW is accumulated at this rate, generating the input

phase. Since phase is in fact an integral (or accumulation) of frequency, phase is also represented

in the digital domain by a fixed number of bits. The same is done with the output frequency.

At the sampling instances of the reference clock a value of the output phase is determined in

the phase detector. This phase detector will consist out of a counter, accumulating the number

of rising edges of the output clock, giving the floor of the phase. There is also a fractional phase

part, by estimating the time between the two clock edges, an estimate of the output phase can

be made. Calculating the phase error is just a subtraction in the digital domain.

1.2.1 Digital Controlled Oscillator

An important building block in every PLL is the oscillator. While in a classical PLL a standard

voltage controlled oscillator is used, converting an analog input voltage to an output frequency,

for an ADPLL is it desirable to have an oscillator that varies its frequency based on a digital

input. Hence a DCO or digital controlled oscillator. A DCO is mostly based on the principle

that the bits of the oscillator tuning word (OTW) switch on or o↵ discrete components such

as capacitors or current sources. In the phase domain the DCO behaves as an accumulator,

accumulating the input frequency word to the output phase. An important work in this thesis

is the design of the DCO. Chapter 3 will discuss this design.


t

t

01234567 �out

Vdco

Vhigh

Vlow

Figure 1.5: Relationship between DCO output and output phase

t

fdco

fref

�out,frac(n)

n – 1 nt

Figure 1.6: Principle of fractional phase sampling at reference clock

1.2.2 Time to digital converter

Another crucial building block is responsible for the conversion of the time di↵erences between

the variable oscillator and the reference oscillator to a phase quantity that can be used to calcu-

late the phase error. Figure 1.5 shows the relationship between the time DCO output waveform

and the instantaneous output phase. The phase throughout this thesis will be normalised. This

means instead of considering an increase in phase of 2⇡ per clock period, this will be a phase

increase of 1. This simplifies the notations and is more intuitive in the digital domain, where

a counter indeed increases its value by 1 per clock transition. The integer part can indeed be

determined by a counter and figure 1.6 shows conceptually how the time di↵erence between two

clock transitions has to be converted to a fractional phase part. TDC design is discussed in

chapter 4. The novelty in this work will be that is attempted to integrate the TDC within the

oscillator itself, resulting in a shorter delay line and a faster phase detection.

7

Chapter 2

ADPLL loop analysis

To get a good idea on the dynamics of the ADPLL and especially the influence of di↵erent noise

and quantisation errors on the output, this chapter will start with a general analysis of the closed

loop ADPLL using idealised models for the di↵erent components. Since the ADPLL behaves as

a fully discrete system, digital transfer functions can be used to model every idealized building

block. As standard for every PLL analysis, signals are represented in the phase domain, with

the big advantage that in an ADPLL these signals represent physical digital words. The output

phase is first considered only at instances of the reference frequency fref . In later analysis it

will also be sampled at the variable DCO frequency fdco. Because the entire digital system is

clocked at the reference clock, it is easy and intuitive to only consider phase in the reference clock

domain. This represents a system where all signals are sub-sampled at the reference frequency.

This analysis however only contains spectral information in the reference band. The oscillator

itself will also add phase noise upto higher frequencies and various sub-sample e↵ects of the

output spectrum should be taken into account. This will be done in the last section where a full

multirate analysis will be presented.

2.1 Closed loop response

Figure 1.4 shows the general layout of a ADPLL composed out of its building blocks. All signals

are represented by a digital word except the interaction between the inherently analog DCO and

phase detector (PD). At this point the signal is a time varying clock pulse. The entire analysis

8 CHAPTER 2. ADPLL LOOP ANALYSIS

1

z – 1H(z)

1

z – 1FCW

�in �� outfn+

-

Figure 2.1: ADPLL model in the phase domain

is done in the phase domain with a normalised DCO phase, as discussed in the previous chapter.

At every clock transition of the reference clock; the input phase is accumulated with the FCW

or frequency command word. This digital input determines the desired relationship between

reference signal and variable output signal since in steady state:

fdco = FCW · fref .

FCW can perfectly be a fractional number, an advantage of the ADPLL structure over a

fractional-N PLL, where the frequency division is in the feedback path can only be integer.

The FCW accumulator can be modelled as a digital integrator with transfer functionz

z – 1.

The loop filter is a custom chosen filter H(z) that outputs the normalised frequency fn or NTW.

This signal is applied to the normalised DCO, normalising the DCO means the output frequency

equals fn · fref . Assuming a perfect phase detector, the output phase at a reference clock transi-

tion equals the previous value added with the number of DCO clock transitions that happened

since the last reference pulse, including the fractional di↵erence. The entire cascade DCO-TDC

can simply be modelled in the digital phase domain as another digital integrator accumulating

the DCO frequency control fNTW, since phase is defined as the integral of the frequency.

�out(n) = �out(n – 1) + NTW(n – 1)

) HDCO =1

z – 1

(2.1)

The equivalent model is represented in figure 2.1. It is fully in the phase domain, sampled at

the reference clock. The actual behaviour of interest for the application of frequency modula-

tion is the transfer function of the input FCW to the output frequency fn. When writing the

accumulator of the frequency control word as G(z) , the DCO-transfer function as HDCO(z), the

z-transform of the FCW as Fi(z) and the z-transform of the normalised frequency fn as Fo(z),

the result is as follows:

Fo(z) =H(z)G(z)

1 + H(z)Hdco(z)Fi(z)

=zH(z)

z – 1 + H(z)Fi(z)

(2.2)

2.1 Closed loop response 9

0.0001 0.001 0.01 0.1 0.5−30

−25

−20

−15

−10

−5

0

f(fr ef)

Magnitude(d

B)

Figure 2.2: Loop magnitude response for ↵ = 0.1

The transfer function from input phase �in to output �out is very similar and will be more

important in following noise analysis, it is given by

HADPLL(z) =H(z)

z – 1 + H(z)(2.3)

When choosing a simple proportional loop filter of the form H(z) = ↵, the closed loop transfer

function becomes:

Fo(z) =↵z

z – 1 + ↵Fi(z) (2.4)

The transfer function (2.4) is a standard first order filter. It is stable for 0 < ↵ < 2 and has a

bandwidth fBW =1 – ↵

2⇡fref for fBW ⌧ fref/2. Figure 2.2 shows the magnitude response of the

ADPLL closed loop response for a value of ↵ = 0.1. In a classical PLL the phase detection adds

a high frequency component to the phase di↵erence that has to be filtered out by the (analog)

loop filter, meaning it is normally not possible to choose a proportional filter. Because of the

digital nature of the phase detection in an ADPLL, there are less stringent demands on the loop

filter and the bandwidth of the loop. Note that there will always be a certain uncertainty on

the filter coe�cient value because a normalised DCO is assumed, meaning the oscillator gain Kp

has to be known. Even with estimation techniques there will always be a certain uncertainty on

this non linear parameter.


2.2 Noise behaviour in the loop

In every realistic circuit, noise will be added at di↵erent points in the circuit. The great benefit of

digital electronics is of course that the signals can not be corrupted any further by noise, and all

calculations are exact. The resolution is only determined by the number of bits. Subsequently

all the noise sources in the ADPLL come from the analog domain or from the quantisation

of analog signals. A first major contribution of phase noise is the quantisation of the output

phase by the TDC. Figure 1.6 shows how at the reference sampling instances, the DCO output

phase contains a fractional part, determined by the time di↵erence between the rising edge of

the reference clock and the DCO. There will be a minimal amount of time di↵erence that can

be detected based on the architecture of the TDC. More details on the design of a TDC are

presented in chapter 4. For now it is enough to understand how much phase error a certain

minimum time resolution will cause, disused in 2.2.2.

A second source of noise is where the digital signal path is converted again to an analog signal,

the tuning of the DCO. Because of the nature of the oscillator, digitally controlled, its frequency

can only be tuned in discrete time steps, defined as �dco. As discussed further it is possible

to update the frequency tuning word NTW at a higher rate then fref , using a ⌃� modulator

resulting in a smaller e↵ective resolution. A similar concept to dithering in N-fractional PLL’s.

Finally the DCO itself is an oscillator, which is an analog circuit. As any oscillator it adds phase

noise to its output spectrum. Contrary to the other two sources, the DCO-phase noise is not

added in the fref clock domain. This is analog noise and should be sampled at fdco for a full

analysis. For a first analysis however, the noise can be sampled at fref and higher frequency

components can be ignored, section 2.3 will discuss an exacter phase noise analysis in the DCO

clock domain. Figure 2.3 shows a schematic block diagram of the ADPLL with the main noise

sources, all signals are sampled at the reference frequency.

2.2.1 Clock jitter and phase noise

The phase noise of the output spectrum is one of the most important characteristics of the

ADPLL. However small or low-power the ADPLL might be, if the output spectrum is too noisy

for the application, the game is over. It is the phase noise that will be used to compare di↵erent

2.2 Noise behaviour in the loop 11

H(z)1

z – 1

�in �� outfn

+-

�TDC

�tune �dcos

Figure 2.3: The ADPLL in the phase domain including the main noise sources, all sampled at

the reference frequency

architecture and decide where the design of this thesis stands, and how using a ring oscillator

compares to the use of a commonly used LC-oscillator.

For communication applications the output spectrum of the oscillator is analysed to measure

the phase noise. In analysis of clock signals however, the amount of clock jitter is often used.

It can prove useful to describe a relationship between these two properties of oscillators. First

both properties will be defined. A single frequency carrier waveform is a sinusoidal periodic

function of phase

V(t) = VC cos(!t + �(t)). (2.5)

Here !t + �(t) is the total phase at instance t. For �(t) ⌘ 0, the waveform V(t) represents

a single frequency wave represented by a single Dirac in the frequency domain. However, the

phase will not be a deterministic signal in any realistic situation. Noise sources deform every

waveform which can be modelled as a certain uncertainty in the phase, modelled by the stochastic

signal �(t), the phase error. The power spectrum of V(t) will then not be a single Dirac, but the

power will be spread out over a continuous frequency range. The di↵erence in power spectrum is

represented in figure 2.4. This figure demonstrate the problem of phase noise for communication

applications. A strong oscillator will inject noise in nearby frequency bands, which could possibly

mask weaker oscillators. There is a direct relationship between the properties of the phase

error �(t) and the output power spectral density of the waveform, the measurable quantity by

spectrum analysers [2, p. 35,...]. When �(t) is relatively small (2.5) can be rewritten as

V(t) = VC cos(!0t) + VC�(t) sin(!0t). (2.6)

The spectrum now consists out of a Dirac at the carrier frequency added with the power spectrum

of �(t), upconverted to the carrier frequency due to multiplication in the time-domain. The


f

PSD

f0 f

PSD

f0

Figure 2.4: Comparison between the power spectra of a single frequency waveform. Both with

(right) and without (left) phase noise

power density is however still infinite at the carrier frequency in this approximation, in reality

this approximation is not valid for frequencies very close to the carrier, but it will be an adequate

relation between phase noise power and the PSD of the waveform for this thesis. The phase

noise power density L(�f) is expressed in dBc (dB of signal power/Hz relative to the carrier

power).

L(�f) =SV(f +�f)

CarrierPower(2.7)

SV(f +�f) represents the power of the signal at (f +�f) in a 1Hz bandwidth. Using this and

the relation between phase noise and the frequency spectrum, it can be shown that

S�(f) =Sv(f0 + f)

Pc.

With Pc the power of the carrier wave. This analysis was now done for a single frequency

waveform, but the result is equivalent for a random shaped periodic function. The frequency

spectrum will not consist out of one dirac, but the power of the carrier is divided over di↵erent

multiples of the base frequency. As long as the noise power is contained within a region ± f02,

di↵erent side bands of the PSD will not overlap.

The previous analysis is focussed on the frequency domain and corresponds with a continuous

time interpretation of the waveform. However in a digital system it is often more convenient to

quantize the entire system at the rising edges of the output square wave clock. In this light the

clock jitter is defined. It describes the process of time error between the expected rising edge of

an ideal clock and the actual clock transitions. Figure 2.5 shows this concept. The ideal clock

has a fixed period T0. Because of phase noise, the set of subsequent time intervals between clock

transitions ,{T1, T2, ..., Tn, ...} ,deviates from the expected period T0. The standard deviation


Ideal clock

jittered clock

��(n)

T0

T1 T2

Figure 2.5: Real clock transitions vs. ideal clock

of this timing error �t is defined as the clock-jitter. The value is directly related to phase noise.

Of course the clock jitter does not contain any spectral information. But, in case of an open

loop oscillator, it can be shown [3] that if the integrated white noise with power spectrum

N0

f2

is dominant, the clock jitter is given by

�2t =N0

f30. (2.8)

With f0 equal to the oscillation frequency.

One last note is about the fact that phase analysis in this thesis is done with normalised phase.

The output �out(t) represents normalised phase while in equation (2.6) however, the function

�(t) describes phase in the classical sense. To interpret the output spectrum of the phase as

oscillator phase noise, it should be multiplied with 2⇡ to compensate the normalisation.

2.2.2 TDC noise

Figure 1.6 shows the fractional part of the output phase at the reference clock transitions.

Because of the finite resolution of the TDC, a quantisation error is injected in the system here.

This minimal time step will be converted to a phase quantisation error. A full integer phase


step of 1 corresponds to a time interval TDCO, the period of the current DCO-waveform. If

subsequent quantisation errors are uncorrelated, the quantisation can be modelled as white

noise. All power equally spread from 0 to the nyquist frequency, with single-sided spectral

density equal to

L =�2�TDC

fref(2.9)

The TDC time resolution TTDCis divided by the DCO period TDCO to end up with the phase

quantisation error in the phase domain, expressed in normalised phase.

�� =�t

TDCO(2.10)

The phase noise is expected to be uniformly distributed over the interval [–��/2 ��/2]. The

standard deviation of this process if given by:

�2� =�2

�

12(2.11)

In this thesis, the phase quantisation of the TDC will be around1

40corresponding to a time

error of around 10 ps. This leads to a single sided power spectrum, when using a reference

frequency of 50MHz, of

L = 10 log10

(2⇡)2

�2�12fref

!= –110 dBc (2.12)

As noted in figure 2.3 this quantisation phase noise is added at the input of the system, the

transfer function to the output is equal to HADPLL(z). Meaning the e↵ect of TDC phase noise

on the output noise spectrum is

�out,TDC = LTDCHADPLL = L H(z)

z – 1 + H(z)(2.13)

The phase noise is constant and equal to LTDC up to the loop bandwidth. After which it starts

decreasing.

2.2.3 Tuning resolution phase noise

A second source of phase noise is the finite resolution of the oscillator. As figure 2.3 shows, this

noise is also added at the input of the oscillator but after the loop filter. This means the tuning


noise is directly related to TDC quantisation noise, as both can be converted to the input. One

can write

�in = �TDC +�tuneH(z)

(2.14)

In the case of the proportional filter this would mean that the total input noise equals

�TDC + �tune/↵.

Often, to increase the frequency resolution, the oscillator tuning signal is oversampled and

the oscillator is tuned at a higher clock-rate. This technique is similar to the tuning of the

fractional-N PLL. It will lower the quantisation noise but introduces fractional spurs. This

oversampling is often used in combination with ⌃�-modulation to spread out the phase noise

to higher frequencies, where they will be filtered out by the ADPLL low pass characteristics.

Since introducing oversampling means using another clock domain, the analysis will be done in

section 2.3, where the oversampling clock domain will also be included. For now tuning will

be assumed to happen in the reference clock domain without any sort of oversampling or ⌃�

modulation.

A practical tuning step for a DCO with oscillation frequency around 2.4GHz will be around

20 kHz in this thesis. In the case of a reference signal 50MHz the result is

�tune =fref2500

(2.15)

This can also be converted to phase noise finding

Ltune = 10 log10

(2⇡)2

�2�12fref

!= –155( dBc) (2.16)

2.2.4 DCO phase noise

The last source of phase noise it the noise added by the oscillator itself. Contrary to the

previous two noise sources this is not caused by the digital operation of quantisation but it is

a fully analog phenomenon caused by voltage noise in the active devices. While for di↵erent

types of oscillators, principles behind phase noise are very di↵erent, results are similar. In all

cases noise in the output phase spectrum is caused by the integration of noise sources in the

transistors. White noise is the most common noise source and causes a typical 20 dB per decade

slope in the phase noise spectrum. However for short channel transistors 1/f-noise is dominant


Noise floor

1f2

1f3

f

S�out

Figure 2.6: Di↵erent noise regions in oscillators

for low frequencies, causing a higher slope of 30 dB per decade in the output spectrum after

integration. Finally white noise sources at the output give rise to a minimal noise level on all

frequencies known as the noise floor. Figure 2.6 gives a typical output spectrum for an open

loop oscillator.

In this primary analysis however, only frequencies upto fref are considered, assuming the higher

frequency content will be neglectable. In a multirate analysis, frequencies upto fDCO will be

considered. However technically this is still a subsampling operation that will introduce spectral

folding since the oscillator phase noise is an analog property.However spectral content above the

oscillator frequency can be safely neglected, also since it is so far out of band.

A ring oscillator has typically higher phase noise levels than an LC-oscillator for the same power

consumption. Since this thesis uses a ring oscillator, it might be considered to use the full

freedom of the digital loop filter design to shape the DCO noise contribution in the output

spectrum. Since the DCO noise is added at the output, the transfer function is di↵erent from

the HADPLL transfer function, controlling the e↵ect of TDC and tuning noise.

Hnoise,DCO(z) =�out(z)

�DCO(z)=

z – 1

z – 1 + H(z)(2.17)

This results in a High pass transfer function, suppressing frequencies lower than the loop band-

width. Figure 2.7 shows this high pass characteristic of an ADPLL, for a proportional loop filter

H(z) = 0.1, corresponding to the input transfer function of figure 2.2.

The benefit of the ADPLl here is that there is more freedom in optimising the DCO noise. In

a classical PLL a small bandwidth is needed to suppress the high frequency components in the

phase detector. Now it is possible to design the loop for a higher bandwidth and suppress more

higher frequency phase noise. It might also be a good idea to not use a proportional loop filter


0.0001 0.001 0.01 0.1 0.5−45

−40

−35

−30

−25

−20

−15

−10

−5

0

5

f (fr ef)

Magnitude(d

B)

Figure 2.7: Transfer function for the DCO noise contribution to the output phase noise spectrum

H(z), but to add an integrating part. Since this results in a steeper slope than 40 dB per decade,

resulting in decreasing DCO phase noise for in band frequencies and complete suppression for

1/f noise. The integrated phase noise with its 20 dB per decade slope, is mostly the dominant

source of output phase noise and it will be the only one taken into account for DCO noise.

2.2.5 Noise contributions

Figure 2.8 shows the output noise PSD for di↵erent noise sources. The loop filter is designed

as a simple proportional filter with H(z) = 0.1. The resulting ADPLL transfer function has a

bandwidth of around 1MHz. The following realistic values were chosen for the di↵erent noise

sources

• LTDC(f) = –110 dBc

• Ltune = –155 dBc

• LDCO(f) =N0

f2N0 = 100

In open loop, the output noise of the oscillator has a value of –100 dBc at a 1MHz o↵set. This

would be a realistic noise level for a ring oscillator.


104

105

106

107

−200

−190

−180

−170

−160

−150

−140

−130

−120

−110

−100

−90

f (Hz)

Magnitude(d

Bc)

TDC noisetuning noiseDCO noiseTotal noise

Figure 2.8: Sampled output phase noise for di↵erent noise sources, proportional loop filter with

bandwidth ⇡ 1MHz( ↵=0.1 )

When optimizing the loop to limit the DCO noise, it is better to choose a higher loop bandwidth.

Furthermore the loop filter H(z) is given an integrating part resulting in the following transfer

function

H(z) = ↵+�

z – 1=

↵z + � – ↵

z – 1. (2.18)

This leads to a closed loop response, using (2.3), of

HADPLL(z) =↵z + (� – ↵)

(z – 1)2 + ↵z + � – ↵=

↵z + (� – ↵)

z2 + (↵ – 2)z + (1 + � – ↵). (2.19)

Which has the following zero and poles

z1 =↵ – �

↵

p1,2 =1

2

✓(2 – ↵)±

q↵2 + 2↵ – 4�

◆.

(2.20)

According to (2.17) the transfer function of the DCO phase noise becomes

Hnoise,DCO(z) =z2 – 2z + 1

z2 + (↵ – 2)z + (1 – ↵+ �). (2.21)

This has a double zero at z = 1, and the following poles,

z1,2 = 1

p1,2 =1

2

✓(2 – ↵)±

q↵2 + 2↵ – 4�

◆.

(2.22)

2.3 Multirate ADPLL analysis 19

A double zero at z = 1 for HnoiseDC0means that for low frequencies, the frequency response will

decrease with 40 dB per decade. The poles are the same for HADPLL and Hnoise,DCO, to avoid

unwanted resonance peaks it is better to choose those poles real. Resulting in the condition that

↵ < –1 –p1 + 4� or ↵ > –1 +

p1 + 4� (2.23)

The chosen values for demonstration purposes for a wide bandwidth PLL are ↵ = 0.8 and

� = 0.1. Figure 2.9 shows the plot of the loop filter H(z) itself. Figure 2.10 shows the two noise

transfer functions. Finally figure 2.11 shows the output noise for the integrating loop filter with

104

105

106

107

−5

0

5

10

15

20

25

30

35

40

f (Hz)

Magnitude

Figure 2.9: Magnitude plot of an integrating

loop filter: H(z) = 0.80.1

z – 1

104

105

106

107

−40

−30

−20

−10

0

10

20

f (Hz)

Magnitude

HADPLL

Hnoise,DCO

Figure 2.10: Magnitude of the noise transfer

function for a type II ADPLL

the previously specified noise values.

2.3 Multirate ADPLL analysis

In the previous section, all noise sources where assumed to be sampled at the reference clock

and the output spectrum only gave spectral information upto fref . While this might be true

for the TDC and tuning noise, which are digital by nature, the DCO noise contains spectral

content at higher frequencies. Also, a PSD for frequencies from 0 to fref is not enough for noise

analysis, information about the spectral content upto the oscillator frequency fDCO is desired.

[4] describes a way to perform a full multirate analysis of the ADPLL using a time-variant

analysis. In this section will be started from the same basic ideas to convert the signals clocked

at reference to the higher DCO frequency. However the analysis itself will be done di↵erently,

trying to give a more intuitive approach, using time-invariant methods.


104

105

106

107

−180

−170

−160

−150

−140

−130

−120

−110

−100

−90

−80

f (Hz)

Magnitude(d

Bc)


Figure 2.11: Sampled output phase noise for di↵erent noise sources,type 2 loop filter, ↵ = 0.8

and � = 0.1

2.3.1 Multirate block diagram

The block diagram in figure 2.12 shows the conversions between the di↵erent clock domains. A

fixed relation N is assumed between the reference frequency and the variable DCO frequency.

This is the case if the ADPLL is locked to a fixed frequency. N can be fractional, but to perform

up and down sampling N is considered integer. Technically, when N is fractional and can be

written as NNND

, upsampling by N should be represented by integer upsampling by NN followed

by downsampling by ND. But this will not be done in this analysis.

The phase error �� is processed in the reference clock domain, and filtered trough the loop

filter H(z). Next this phase error has to be converted to the higher frequency used by the ⌃�

modulator for dithering the DCO. The way this is implemented in the block diagram is by

upsampling to the DCO-frequency using the factor N. Subsequently placing a zero-hold-filter

and sampling back down with a factor M. When no ⌃� modulation is used, M = N and this

conversion block can be omitted. The zero hold filter has the e↵ect that the upsampled signal

remains constant over a length N.. The key is to make sure all blocks work with signals in the

highest clock domain, e.g. the DCO clock. In figure 2.13 the blocks are replaced so that the loop

is now modelled completely at fDCO. All input noise signals are also converted to the higher

frequency. Placing an upsampling block " N from behind a transfer function H(z) to the front,

means this transfer function should be converted to one that operates at fDCO. Meaning the z

that was defined with respect to a frequencyfDCO

Nnow has to be replaced by zN.


H(z) HN(z)�ref +-

"N

#N

�TDC

#M HSTF

HNTF�tune

"M HM HDCO

�dco

�out++

++

Figure 2.12: Multirate block diagram of the ADPLL

H(zN) HN(z)�in +-

#"N #"M HSTF(zM)

�tune,shaped

HM(z) HDCO(z)

�dco

�out++

Figure 2.13: Multirate block diagram of the ADPLL with blocks replaced for full operation in

DCO-clock domain

The behaviour of all the blocks will now be analysed to find the correct transfer functions. A first

important building block is the down conversion immediately followed by a down conversion.

Upsampling

Upsampling here means the conversion of a signal x(n), with sampling time T, to a signal y(k)

with sampling time T/N. x(n) is a discrete signal with all the energy concentrated at the time

instances nT. Meaning y(k) will have zero amplitude in all other time instances. Resulting in

the following y(k),

y(nN) = x(n)

y(k) = 0 , k 6= nN(2.24)

The power spectrum of y(k) is related to x(n), but not exactly the same. By specifying the

signal to be zero at certain time steps, the total signal power decreases and this power is spread

out over a higher frequency band.

X(f) =+1X

n=0

x(n)e–2⇡jfnTs

Y(f) =+1X

n=0

x(n)e–2⇡jfnTs

(2.25)


f

SXX

1

2Ts

1

f

SYY

1

2Ts

1

N2

N

2Ts

Figure 2.14: The e↵ect of upsampling on the power spectra with N = 3

The frequency spectra of both signals are equal, but the nyquist frequency of Y(f) is N times

higher than the one of X(f). Meaning the power spectrum of y(k) will be periodic and a factor1

N2 lower in magnitude. If SYY is defined as the power spectrum of y(k) (with sampling time

Ts/N), the following relation with SXXf is found

) SYY(f) =1

N2SXX(f), (2.26)

with power on frequencies from [–N

Ts

N

Ts]. Figure 2.14 demonstrates this e↵ect schematically.

Real signals are assumed so that the frequency spectrum is also symmetric with respect to f = 0.

Downsampling

Downsampling is the exact opposite operation of converting a signal from one clock domain to

another one with a lower sampling rate. If we take x(n) to be a signal with the highest sampling

rate Ts and y(k) a signal with lower sampling rate NTs then their relation is

y(k) = x(kN). (2.27)

Contrary to the case of upsampling, downsampling means the nyquist frequency gets lower and

spectral content may be lost. It is at the downsampling blocks in diagram 2.12 that aliasing may

occur. To analyse the relation between transfer functions Y and X, it is easier to consider the

operation downsampling followed by upsampling. This is actually the important operation in

the block diagram. Figure 2.15 shows the behaviour of this operation. This important down-up

sampling will be denoted by the star operation x⇤(n). The behaviour of the star operator is equal

to the multiplication in the time domain with a Dirac-series �N(n) : {1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0}

with 1 pulse every N samples. In the frequency domain, this means X⇤(f) equals the convolution


#" Nx = {x0, x1, x2, x3, x4, x5, x6, ...} x⇤ = {x0, 0, 0, x3, 0, 0, x6, ...}

Figure 2.15: Down-up conversion

of the Dirac-sequence spectrum and X(f). �N(n) is periodic, so it has a discrete time fourier

series �N(l):

�N(l) =N–1X

n=0

�N(n)e(2⇡jl nN) =

1

N. (2.28)

This means that the continuous spectrum �N(f) consists out of a series of Diracs:

�N(f) =1

N

N–1X

l=0

�(f – fsl

N) (2.29)

Finally resulting in the following spectrum for X⇤

X⇤(f) =1

N

N–1X

n=0

X⇣f +

n

Nfs⌘

(2.30)

This can also be represented directly in the z-domain:

X⇤(z) =1

N

N–1X

n=0

X⇣z e2⇡jfTs

nN

⌘(2.31)

The spectrum of the signal y(n), is then

Y(f) =1

N

N–1X

n=0

X

✓f +

fsNn

◆(2.32)

With fs =1

Ts, the highest sampling rate. It is clear that when the spectral content of X is

limited to a bandwidthfsN

(as an anti-aliasing filter would become), there is no aliasing and

Y(f) =X(f)

N.

2.3.2 Multirate transfer funtions

The system in figure 2.13 can further simplified to result in the schematic of figure 2.16 if it is

assumed that the up-down conversion with M of the ⌃� modulator can be approximated by a

factor1

M. However in the continuation, it will be assumed that M = N, and ⌃� modulation

will not be taken into account. The transfer function HLG then equals


�in+

-#"N

�Q

�outHLG(z)

Figure 2.16: Simplification of the multirate model

HLG = H(zN)HN(z)1

MHSTF(z

M)HM(z)HDCO(z) (2.33)

The zero hold filter has an impulse response where the first N samples equal 1 and all the other

0. Simply using the definition of z-transformation leads to the following transfer function

HN(z) =+1X

n=0

xN(n)z–n

=N–1X

n=0

z–n

=1 – z–N

1 – z–1.

(2.34)

To calculate the transfer function HLG, a system is used without ⌃� modulation by taking

H(z)�ref +-

#N

�TDC

�tune

"N HN HDCO

�dco

�out+

+

++

Figure 2.17: Block diagram of the multirate ADPLL without ⌃�-modulation

M = N. This means the signal shaping function HSTF and noise shaping function HNTF and

HM(z) equal 1. Figure 2.17 shows the diagram for the situation without ⌃�. This simplifies

HLG(z) to

HLG(z) = H(zN)HN(z)HDCO(z). (2.35)


106

107

108

109

−80

−60

−40

−20

0

20

40

60

80

f (Hz)

Magnitude(d

B)

Figure 2.18: Magnitude bode plot of the multirate open loop transfer function HLG(z)

The transfer functions of these di↵erent blocks, and the used numerical values are given by:

H(zN) = ↵+�

zN – 1

HN(z) =1 – z–N

1 – z–1

HDCO(z) =1/N

z – 1

fref = 50MHz

fDCO = 2.45GHz

=) N = 49

↵ = 0.8

� = 0.1

(2.36)

The normalised DCO transfer function still behaves as an integrator, however since the integra-

tion is now monitored at a rate N times faster than the reference clock, it takes N timesteps for

the output phase to rise with the tuning word, hence a factor 1/N is included in the transfer

function. Finally this results in

HLG(z) =1

N

↵zN + (� – 1)�zN – zN–1

�(z – 1)

. (2.37)

Figure 2.18 shows the magnitude of the transfer function for the previously specified values

from (2.36), clearly showing the spectral folding e↵ects for frequency larger than 50MHz.

The frequency spectra of the input and output noise sources �in and �Q can now be written in

function of the previously defined noise sources. �tune is now referred with respect to the output


instead of the input in the previous section because of simpler calculations.

�in(z) = [�TDC]"N

�Q(z) = �DCO + [�tune]"NHN(z)HDCO(z)(2.38)

Using the star-operator, and looking at figure 2.16 ,the output phase noise can be written as

�out = (�in – �out)⇤HLG(z) + �Q. (2.39)

Next the star-operation ⇤ is applied on both sides of the equation. The star-operation is clearly

a linear operation, so this results in

�⇤out =

✓(�in – �out)

⇤HLG(z)

◆⇤+ �⇤

Q. (2.40)

To solve this the following property of the star-operator is used:

✓F(z)⇤.G(z)

◆⇤= F(z)⇤.G(z)⇤ (2.41)

This property can be proven by directly applying equation (2.31). Using this on the output

phase equation leads to

�⇤out =

H⇤LG

1 + H⇤LG

�⇤in +

1

1 + H⇤LG

�⇤Q

(2.39) =) �out =HLG

1 + H⇤LG

(�in – �Q)⇤ + �Q

(2.42)

The result of this analysis is shown in figure 2.19. It shows the output phase noise for the

di↵erent noise sources. For frequencies under fref the phase noise approximates the results of

the single rate system very accurately.


104

105

106

107

108

109

−180

−170

−160

−150

−140

−130

−120

−110

−100

f (Hz)

Magnitude(d

Bc)


Figure 2.19: Phase noise in the multirate system

29

Chapter 3

Design of a DCO

Now that the ADPLL principles are explained and explored,a good circuit implementation is

searched that matches the behaviour of the ideal building blocks as good as possible. The first

building block is the most important one, namely the DCO. Of course without a controllable

oscillator any PLL is pretty useless. In this chapter there will be a quick look at the di↵erent

oscillator types that are used in current day loops. After which the actual circuit implementation

of a ring-oscillator will be discussed in 65 nm CMOS.

3.1 Digital controlled oscillator

As discussed in the previous sections, the tuning is controlled by a digital word. This word could

be either binary weighted or thermometer encoded or whatever format the designer has chosen.

The oscillator has to be designed as a fully analog system, meaning this digital control word

somehow has to be converted to analog quantities. Basically there are two possible ways one

could interpret this. The first way is to use a standard VCO and convert the digital control word

into an analog control signal with a DAC, as shown in figure 3.1. At first glance this might seem

the most intuitive implementation. However, converting the signal to an analog voltage might

require large capacitances, which was one of the reasons in the first place to remove the analog

phase detector in a classical-PLL and choose for a ADPLL. Furthermore, this extra conversion

at this critical point in the loop can only inject more noise and make the system less predictable.

Another approach is to use the digital bits directly to switch on or o↵ discrete components in

30 CHAPTER 3. DESIGN OF A DCO

DACDTW[1:N] VC VCO

Figure 3.1: Using a DAC to generate a control voltage for a standard analog VCO

the DCO itself. Technically this also a DAC, but it is integrated directly in the DCO. Normally

in standard VCO’s, the tuning voltage controls another property, like current or capacitance,

that changes the frequency. For example, in an LC-oscillator the tuning voltage controls the

capacitance of a varactor. In a relaxation oscillator and ring oscillator it can both control the

capacitance or the current. In a DCO, one could try to change one of these properties directly

with the tuning bits, e.g. by using a switch to add extra capacitances or switch o↵ fixed current

sources. This will have better properties than an analog conversion since there are only two

possible states. A popular approach in LC-oscillator still concerns varactors but switches every

varactor between only a low and a high state. This particular approach will be discussed a bit

more further on.

3.2 LC oscillators

Most communications applications nowadays make use of the LC-oscillator. So does design of

Staszwski and many others with similar approaches [1]. A lot of research has been performed

on this topic and very stable and low noise oscillators can be designed. It’s frequency is given

by

f0 =1

2⇡pLC

(3.1)

Assuming the inductance L is rather fixed, especially on chip, a popular tuning method of this

type of oscillator is changing the value of the capacitance C by varactors. A varactor essentially is

a diode of which the value can be changed by applying a di↵erent backwards voltage. A popular

method is using a pmos transistor as varactor.[1, p.-31] In traditional CMOS the capacitance has

a rather linear relation with the applied voltage. In deep submicron CMOS the transition from

maximum to minimal value becomes less gradual. This means this type of varactor becomes

less attractive for standard VCO’s, but remain or even become more useful for digital tuning,

since they behave more like a switch. LC-oscillators might be the preferred choice for for

design on PCB, on chip it poses quite some design challenges. The largest problem being the

implementation of the inductor. Since ADPLL’s are being researched for applications in small

3.3 Ring oscillator 31

VoL C –gm

Figure 3.2: LC oscillator

on-chip systems, large discrete inductors are the last thing one wants. It is possible to integrate

inductors on chip, but these require long conducting paths and take up a lot of chip area.

Furthermore, parasitic couplings cause the inductor to behave less than ideally. This results in

many di�culties ilayouting an inductor on chip. A final concern is the fact that the inductance

does not scale well with new technologies, meaning the surface area becomes relatively larger

and the layout process have to be restarted for every new technology step. Therefore, in this

thesis it was chosen to go for a more digital approach that is better integrable with the digital

control logic in deep submicron.

3.3 Ring oscillator

3.3.1 Basic principle

The basic concept of a ring oscillator is fairly easy to understand. Figure 3.3 shows how an odd

number (N) of inverters is put in series. Clearly this is an unstable system. The number of cells

has to be odd in this case, otherwise a stable state exists. At first it is simply assumed that every

inverter has a certain TD before the output is changed as a reaction on a new input. If this is

the case there is always at least one inverter switching it’s output state. For a correct oscillator

operation it is always desired that there is exactly one inverter switching. When a certain cell

has switched, the next cell will begin switching, this way the active cell travels around the ring.

Every state will thus switch between 0 and 1. When the switching cell has travelled around the

ring 2N times, the state at a certain point will be back in it’s original position. This leads to

the following simple equation for the ring oscillator frequency,

f0 =1

2NTD. (3.2)

For ideal digital inverters the output is a nice square wave switching from 0 to VDD. Ring

oscillators have the benefit of very wide tuning ranges with rather linear response to input,


Figure 3.3: Standard single-ended ring oscillator

compared to LC-oscillator. The tuning design should go a bit easier. However in general they

exhibit more phase noise for the same power consumption.

When simply connecting 3 standard inverters back to back one would be lucky to get any

oscillation at all. While the basic principle of ring oscillator is very easy, designing a good

tunable oscillator with low phase noise is quite a challenge. A lot of research has been done and

is still being performed on this topic.

A first issue with this simple structure is the fact that inverters can be in a metastable state

between the high and low level. During switching, the voltage does not drop with a very steep

slope, but there is gradual transition from high to low. For example in the case of a single

ended inverter, the very important switching delay will be a function of the drive current of the

transistors and the capacitive load. While the drive current can be a very complex function of

the input voltage and time, depending on the type of oscillator used, the dependence of TD on

the capacitance should be proportional for all types. Figure 3.4 shows an inverter with an ideal

voltage step VDD to 0 at the input. The pmos is completely in cut-o↵ while the nmos is in

saturation and behaves as a resistor Ron. The output voltage is then given by

Vout = VDD

✓1 – exp

✓–t

RonCload

◆◆. (3.3)

If the output is assumed to have switched when the voltage reaches the threshold voltage VT,p

of a pmos inverter then the delay time becomes,

TD = ln

✓VDD

VDD – VT,p

◆RonCload. (3.4)

However, before Vout reaches VT,p the nmos will already start conducting current. Transistor

are most certainly not perfect switches. Meaning the TD of a second pair will already be

di↵erent. This means, when the input is not a perfect step, the output voltage will behave

di↵erent and will not have an exponential characteristic. The ideal square wave output is thus

far removed from reality. The good thing however is that, since all elements are connected in

a ring, the voltage transitions will converge to a steady state waveform and all delay times of


Vin

Vout

VDD

ron

Cload

Figure 3.4: Switching of an ideal inverter

Figure 3.5: Ring oscillators with di↵erantial delay cells

the di↵erent elements will be equal. It is also possible that a certain cell starts switching again

in the opposite direction before the output is even close to it’s final value. This decreases the

e↵ective switching time TD and makes the entire system less predictable. Especially when the

output waveform is exponential is this problematic, because it decreases very slowly in voltage

near the end of transition.

3.3.2 Di↵erential ring oscillators

A good improvement is the use of a di↵erential ring oscillator. These configuration will also

allow the use of an even number of stages, using a wire inversion, as figure 3.5 shows. All signals

are defined di↵erentially in this structure A first possibility to implement this at circuit level is

a fully di↵erential cell, which is basically a di↵erential pair. It is shown in figure 3.6. Only when

the input voltage di↵erence is small will both transistor act in their linear operation area and

will the cell behave as an amplifier with gain gm. When the input voltage di↵erence becomes

larger, one transistor will cut-o↵ while the other one conducts the full current. The slew-rate

will determine the delay time.


VDD

Vin+ Vin–

Vout+Vout–

Figure 3.6: Fully di↵erential delay cell

Vin+

Vin– Vout+

Vout–

Figure 3.7: Latch structure concept of a pseudo-di↵erential delay cell

A second implementation is the so called pseudo-di↵erential delay-cell. Signals are still defined

di↵erentially, but the switching threshold of each input line is defined independently with re-

spect to the supply voltage.This while in the fully di↵erential case, switching occurs when the

di↵erential inputs cross each other’s levels and equal 0. Figure 3.7 will clarify this principle.

The design itself is based on a latch structure for master-slave flip-flops. The cross-coupled

inverters result in positive feedback and will ensure a 180� phase di↵erence between the two

output sides. When the input signal at one of the terminals crosses the switching threshold of

the input inverter, the corresponding output voltage will start to change. At some point this

will switch the feedback inverters and force the other output line to the complementary value.

During operation there will be a certain time period when two inverters, feeding the same output

line try to impose a di↵erent output. When this happens there will be short circuit during some

time. Therefore it is important that the strength of every inverter is carefully tuned. Smaller

transistorW

Lresults in higher on resistance and lower currents. The input inverters have to be

the strongest. If the feedback inverters would be a lot stronger than the input cells, the output

would never change, as is the case in latch cells. Using a series of these pseudo-di↵erential cells

in a ring oscillator will ensure that both input lines change their value during the same time


Vin+ Vin–Vout+

Vout–

VDD VDD

ItuneVtune

NA+ NA-

PA+ PB+ PA-PB-

Figure 3.8: Circuit implementation of a pseudo-di↵erential delay-cell

period. The full configuration of figure 3.7 however is only a concept, and not the circuit that

was finally implemented. Instead of full inverters for inverters with both n- and pmos transistors

only a pmos transistors is used. This means a low output level on one of the lines can force the

other line to a high level, but not opposite. Figure 3.8 shows the final implementation. Note

that the nmos source is not connected to ground, but to the tuning circuit. This will limit the

available current for the cell and determine the frequency.

3.3.3 Design choices

The delay cell of figure 3.8 is implemented in Cadence, using the 65 nm technology. In the

particular design in this work on oscillator was needed to oscillate at a frequency of 2.4 to

2.5GHz. An even number of cells was chosen, since it might be useful to also have access to the

waveform in quadrature. As a first proof on concept design a low number of cells was chosen,

i.e. N = 4. When taking a center frequency of 2.45GHz, using equation (3.2), the desired delay

time is 51 ps. This is certainly no problem in the 65 nm CMOS technology. The design is of

course symmetrical, positive and negative side are equal. The nmos transistor is chosen to be

relatively stronger than the pmos. This is because the tuning circuit will change the current


trough this nmos. All transistor lengths are chosen minimal. To design the cell, transistors are

modelled as behaving like resisors in the one state. However designing the the ring oscillator is

a very iterative process, relying heavily on simulations to fine-tune the transistors. The choice

of design cell and its sizing has a great influence on the design of the delay cell itself. Eventually

minimal length transistor were chosen, this to limit the load capacitances as much as possible.

Table 3.1: Transistor sizing of the delay cell in figure 3.8

Transistor Name WL

NA 6.5

PA 2

PB 3.3

Scaling is based on the fact that the width is inversely proportional with the on resistance. It is

repeated that this is still a very simulation intensive tuning. Waveforms are di�cult to predict.

3.4 Tuning of the ring frequency

As mentioned before the delay of a cell depends on the current trough the transistors and the

load capacitance. So there are two possibilities to tune a cell. In LC oscillators the capacitance

is tuned, which leads to a minimum capacitance di↵erence, dependant on the technology used.

The ring oscillator enables the designer to choose to limit the available current for charging the

load. In this thesis this will be the used strategy. To general idea is as follows: The drive current

of the nmos transistors, required to discharge the load, in figure 3.8 is limited, is done by placing

a tunable current source under the delay cell. When a cell is not switching it uses no current.

There will only be two cells switching at the same time if the design is well performed. So if the

current from the tuning circuit can’t be interrupted, the tuning circuit has to be connected to

all cells together, shown in figure 3.9. Only the current through the nmos will be limited. The

pmos transistors are designed much smaller. The e↵ect can be explained as follows, imagine

that Vin+ in figure 3.8 becomes high and Vin– low. A current I+ will discharge the load at the

negative output trough transistor NA+, while a current I– will start charging the load at the

possitive output. By design of the cell I– < I+. Note that a part of the current I+ will not

discharge the load, but will come directly from the supply voltage trough PB+. If the design

is well performed, the output Vout– will cross the pmos threshold voltage after some time and

activate PB–, to speed up the slope of Vout+. In the configuration the nmos is dominant for

3.4 Tuning of the ring frequency 37

VDD

TuningDCW

Figure 3.9: Layout of the tuning circuit in a di↵erential ring oscillator

the tuning, meaning the falling output edge comes first. It is this falling edge that will force

the rising edge to start rising faster as well. The big advantage of di↵erential ring oscillators is

that because of the symmetry, the voltage waveform will always be the same at every point of

the ring. An easy definition of the delay time can than be the time between zero-crossing at the

input of a cell and output. Where the zero crossing is the point where the positive and negative

signals are equal.

Idealy the shape of the waveform should be linear slopes. As if an ideal current source would

charge and discharge the capacitor. In reality it can not be assumed that the tuning current is

used completely to charge the load, i.e. this current will be divided over two cells when another

cell starts switching while the previous cell has not reached it’s final value. But this unrealistic

assumption can lead to some guidelines for the desired tuning current. Its value can be estimated

based on the used transistor sizes.

TD ⇡ ItuneVDD

2Cload(3.5)

For example, when the load capacitance is 5 fF and the required delay time is 51 ps, the required

current is around 60µA. Again this a very crude result, for this type of design an iterative

process is required. Based on time analysis simulations, transistor sizes and tuning current have

to be optimised. The load capacitance of a delay cell consists out of the input transistors of the

next delay cell, and the input transistor of the bu↵er.

Figure 3.10 shows the basic tuning circuit. The capacitor and resistor model the imperfections

in the current sources, such as the parasitic capacitances and a high but finite output resistance.


Ring

Vtune

ItuneC

R

Figure 3.10: The tuning circuit of the ring os-

cillator

�Vtune

�ItuneCR

Rring

Vring

Figure 3.11: Small signal model of the tuning

circuit

For the current source to function, the voltage Vtune must be higher than the saturation voltage

of this current source. This voltage will depend on the sizing of the nmos transistors used and

raises the low-voltage of the output wave. An interesting phenomenon is that this tuning voltage

remains rather constant for changing current values. It could even be interpreted as if the tuning

cell feels the ring oscillator as a diode, having a rather constant forward polarised voltage. With

the help of simulation this value was chosen to be around 0.3 V . This is a good compromise

between current source headroom and voltage swing.

On this constant a varying AC-part is superposed. This AC-part is a result of the fact that the

cells are switching at a frequency 2Nf0, resulting in a AC-term with frequency around 20GHz.

A first order small signal is shown in figure 3.11. The ring oscillator is here replaced by a

small signal resistor. This means raising the current by �I is equivalent with lowering the

tuning voltage by �I ·R. Changing the supply voltage is also one of the techniques to tune the

oscillator, but note that they are in fact completely equivalent. The AC-term Vring also causes

an extra current in the tuning circuit given by

Iring =sC

1 + sCRringVring, (3.6)

ignoring the current source resistance R. Or equivalently, an extra AC-term is introduced on

the voltage �Vtune.

�Vtune =Vring

1 + sRringC(3.7)

3.4.1 Concept of Banks

To tune the oscillator over the complete frequency range with a certain discrete frequency step

a high number of bits might be needed. If someone wants to cover the entire bluetooth band


of 80MHz with a frequency resolution of 1 kHz, this would result in upto 17 binary weighted

elements. Since matching elements on chip is mostly possible upto 8 bits, a solution has to be

found to use elements that are not perfectly matched together. In the work of Staszewski, a

method using di↵erent banks is described. Each bank has a range of 8 bits and is internally

matched. Di↵erent banks however do not have to be matched with respect to each other [1].

The use of three banks is described. Every bank consists out of discrete varactors that have two

possible capacitance values. The first bank is to account for PVT, or variation due to Process,

Supply Voltage or Temperature deviations. It has a very wide tuning range with a crude tuning

step, used at start-up to find the center of the bluetooth band. Because of variations in the

process the transistor properties might not be well defined. Also when temperature changes,

oscillation frequency might change drastically. Once the center of the band is found, the 8 bits

used for tuning the PVT bank are locked and the second bank starts being used. This has a

resolution of about 0.5MHz and a total range of 118MHz. It will be used to find the correct

communications channel. Once this is found the loop switches to the third and final bank,

the tracking bank. Here the actual frequency modulation within the channel is tracked with a

resolution of 23 kHz and range of 1.5MHz.

In this thesis however, since it is the current that is tuned, a slightly di↵erent method will be

attempted. Instead of a separate bank it should be possible to change the value of the fixed

current source I0. This can be done by an analog tuning voltage. This tuning may be very

inaccurate. Once the frequency is in the desired range the voltage can be locked and the current

source is kept constant for the rest of the ADPLL operation. In this work, only a fixed current

source is used, it is assumed to be tuned to the correct value. The margin for error during

PVT range is very large, depending on the designed range of the acquisition bank. Meaning the

actual implementation should not pose many additional demands.

The concept of banks is not completely abandoned in this work, and two separate tuning banks

will be created, each with 8 bit tuning. The first bank, or acquisition bank will be designed for

a resolution of 1MHz and related range of 256MHz. 1MHz tuning will allow the loop to get

very close to desired bluetooth band. A second finer bank is then implemented, likewise with 8

bits resolution. A range of 2MHz will be more than su�cient to cover an entire channel. With

8 bits resolution, a frequency step op 25 kHz is found.

If ⌃�-modulation is used, it should be applied on the smallest current sources, switching them

on and o↵ at a higher rate. For now these 25 kHz will we taken as the lowest frequency step of

this DCO.


�Itune

Imin2Imin4Imin

tune2 tune1 tune0

I0

Figure 3.12: Principle of switched current sources for oscillator tuning

3.4.2 Circuit implementation

To design an tunable current source and control it with a digital control word, a fixed current

source I0 will be designed, after which an array of other fixed current sources is designed to be

switched on or o↵ by digital switches controlled by the tuning word. Figure 3.12 demonstrates

this principle. The lowest possible frequency should be the one with the minimal amount of

current, or the frequency that is obtained when only the fixed current source I0 is running and

all other sources are cut-o↵. The application in mind is bluetooth, with a minimal frequency

of 2.4GHz. Therefore a slightly lower frequency will be chosen than 2.4GHz to have some

margin. A stated above the acquisition has a tuning range of 256MHz, so a good value would

be 2.32GHz. Using simulations to optimise the used current source, a value of 102µA is obtained.

This is quite a bit higher than the expected 60µA, indicating the inaccuracy of this formula.

Figure 3.13 shows an a plot of the actual current going trough the nmos transistor of a cell.

It’s value clearly reaches a peak around 110µA, but most of the time the current is lower, as

the tuning current is divided over multiple cells. However when considering the mean current

delivered to a cell from the moment of onset of conduction until the current is 0 again, this value

is closer to the theoretical value. However it is still to far-fetched to use this fact directly as

a design rule. Tuning via simulation stays necessary. Note that this peak is a bit higher than

the 102µA delivered by the tuning circuitry. There will be some current flowing from other

cells due to parasitic capacitances. However this small di↵erence will be ignored. A value of the

minimal current sources still has to be chosen. At first there will be tried to find an analytical

approximation of this value. After this, again simulations will be used to fine-tune the result. If

a current of 102µA results in a frequency of 2.4GHz, and a completely linear relation between


2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3−20

0

20

40

60

80

100

120

time (ns)

curren

t(µA)

Figure 3.13: Current through the nmos of a single delay cell

current and frequency is assumed, a value of 42 nAMHz is found. After implementing this the

frequency step is too small. Tuning results in a minimal current source of 100 nA.

The array of 8 binary weighted current sources is than constructed following the principle of

figure 3.12. The current source itself is a single nmos transistor. All 8 current sources have the

same bias voltage, coming from a mutual bias control circuit. But the width of every transistor

is weighted with a binary scaling factor. If, due to process variations, the required current is

much di↵erent from this predefined value of 1MHz, it should still be possible to tune the bias

current source to a better value. This is an advantage over the use of discrete capacitors where

the value is fixed. The circuit implementation of the tuning section is shown in figure 3.14.

The tracking bank is implemented in an equivalent way. For a minimal current source, a first

value of100 nA

40is attempted. This is 1/40 of the minimal current of the acquisition bank. If

the oscillator frequency is locally linear, what it should be, a value of 2 nA should result in

25 kHz resolution. Simulation confirms this. The bias voltage for the tracking current sources

is generated by a separate bias circuit, completely independent

3.4.3 Designing the switches

The switches are themselves implemented with nmos transistors and will show imperfections.

The idea is to interrupt the current path of the current source. When the switch is turned on,


�Itune

tune2 tune1 tune0

W = W0W = 2W0W = 4W0

Vbias Vbias VbiasVbias

Imin

W = W0

Figure 3.14: Circuit implementation of the current tuning, including bias

Ron

Vbias

Cpar

Vbias

Cpar

VGS VGS

Figure 3.15: Model of the switch in on (left) and o↵( right) state

the nmos transistor will have a finite on-resistance (figure 3.15 ).This means the voltage VGS

will depend on the value of this resistor and the current trough the source, it’s value is

VGS = Vbias – 2nIminRon (3.8)

If the current gets higher the bias voltage drops which results in a lower e↵ective current trough

the transistor. When turning the switch o↵, the voltage at the source will rise until the current

source cuts o↵. The current will charge the capacitance until it’s charged enough to lower VGS

su�ciently. This capacitance is the parasitic capacitance of both the switch and the current

source, Meaning it’s total value will scale with the larger current sources. A problem arises

however because when the current trough the source decreases, charging the capacitor will go

slower, and a low current will keep going through the source a rather long time. When one

of the larger current sources switches o↵, this remaining current might still be larger than the

smaller current sources. To solve this problem it is needed to charge the capacitor very rapidly

when the switch turns o↵. The implemented solution is shown in figure 3.16. A pmos is added


tune

Vtune

Vtune

Vbias

Figure 3.16: Using a pmos switch to quickly charge the parasitic capacitance

that is connected to the same tuning line. When the nmos turns o↵, this pmos will switch on

and rapidly charge the capacitor. It is best not to charge this capacitor higher than the drain

voltage of the current source ( this is a constant voltage, see previous section). Otherwise a large

current peak in the opposite direction might occur when the switch turns on again. Because

of the binary coding it can still happen that a lot of switches have to change state for only a

small current change. For example switching from to 10000000 to 1111111 can result in spikes

because of a small mismatch in time need to switch on and o↵. The largest current source needs

some more time to turn o↵ while all other sources switch immediately . Resulting in current

spikes. This results in a very short increase in frequency before the frequency decreases to it’s

final value. The phenomenon only happens during frequency decrease

The length of the current source transistor was not chosen minimal. This to improve output

resistance and also because minimal length transistors do not behave well as current source. The

length L = 200 nm. However the width was chosen minimal: W = 120 nm. The nmos switch

was initially taken minimal, but as mentioned above, when a large current has to flow trough

the switch, voltage over the transistor increases and the current source decreases in current.

Therefore the switch is scaled together with the current. Resulting in in W = 16microm for the

largest current. The scaling of the pmos transistor is not that important. It should not add too

much capacitance however. W was chosen to equal 400 nm.


WL =3 W

L =3

VDD

WL =17

WL =17

Vin+ Vin–

Vout+Vout–

Figure 3.17: Level shifter output bu↵er

3.5 Output bu↵ering

Because of the tuning circuit the low voltage of a delay cell is raised to 0.3V. However in

subsequent digital blocks, a full switch to 0 is required. This raised voltage VLow is not capable

of turning an nmos transistor completely o↵ and could short-circuit the system. For this reason

a level shifter output bu↵er is designed, the design shown in figure 3.17. It is similar to the used

delay cell, using the cross coupled transistors. But here the input signal is not connected directly

to the nmos. Figure 3.17 shows the desig Furthermore, the frequency is highly dependant on

the load capacitance. However if delay cells are sampled by flipflops this might change the

capacitance, changing the frequency. Therefore the bu↵er has to e↵ectivally shield the ring

oscillator from the rest of the circuit. After the level shifter an array of 3 inverters is placed.

Keeping the load capacitance constant.

3.6 Simulation verifications

Figure 3.18 shows an plot of the waveform in the time domain. The rising edge starts switching

first, but the falling edge will be faster due to the feedback. Voltage swing is between 0.3V and

1.2V. To test the e↵ective tuning of the DCO, the input bits are toggled trough all possible

3.7 DCO phase noise 45

2.2 2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.60

0.2

0.4

0.6

0.8

1

1.2

1.4

time (ns)

Voltage(V

)

Output Cell 4Output Cell 3+

+

-

-

Figure 3.18: Di↵erential output of two sequential delay cells

0 0.5 1 1.5 2 2.5 32350

2400

2450

2500

2550

2600

2650

time (µs)

DCO

freq

uen

cy(M

Hz)

Figure 3.19: Changing frequency of the DCO over the full range by changing the coarse input

states in order. The e↵ective frequency is determined by monitoring the time di↵erence between

subsequent clock edges. Inverting these times leads to the e↵ective output frequency. Figure

3.19 shows the frequency changing over the entire range in steps of 1MHz. The frequency spikes

seen in the graph are glitches in the simulator and have nothing to do with the phenomenon

discussed above. Decreasing frequency steps are not shown in the graph. Figure 3.20 shows a

smaller portion of the range.

3.7 DCO phase noise

Estimating noise source in ring oscillators is not straightforward. A lot of designs rely on

simulation data to estimate the phase noise. Transistors in the ring oscillator can not be modelled


0.52 0.54 0.56 0.58 0.6 0.62 0.64

2400

2405

2410

2415

2420

2425

2430

2435

2440

2445

time (µs)

DCO

freq

uen

cy(M

Hz)

Figure 3.20: Detail of the DCO tuning, showing coarse frequency resolution

in their linear range, making it hard to calculate transistor noise sources. [3] describes some

relationships between the parameters and the phase noise. Assuming that most noise sources

are white noise that are integrated to an 1/f2 output spectrum, [3] states that the phase noise

is inversely proportional to the drive current and the supply voltage. Unfortunately, DCO

phase noise is very high. Some other designs in [3] or [10] mention ring oscillators with similar

noise performances. These are however not suitable for communication purposes. With careful

design, accounting for phase noise in every step of the design, it should be possible to achieve

communication specs with a ring oscillator. But at the cost of higher current [3]. The simulated

phase noise is shown in figure 3.21. It has a value of –100 dB at a frequency of 10MHz. And

the expected slope of 20 dBc per decade.

3.7 DCO phase noise 47

105

106

107

108

109

−180

−160

−140

−120

−100

−80

−60

frequency (Hz)

PSD

(dBc)

Figure 3.21: Open loop output phase noise of the DCO

49

Chapter 4

TDC implementation in a ring

oscillator

Another very important analog intensive part is the Time To Digital converter or TDC. This

is a part of the phase detector, determining what the phase di↵erence is between the reference

clock and the output variable clock. At every rising edge of the reference clock, the counter

knows how many times the variable clock has ticked, or what the integer part of the variable

phase �V is. Only integer phase detection will however not be enough for adequate phase noise

levels. It is necessary to estimate the the fractional part of the phase di↵erence. This is done by

measuring the time di↵erence between the rising edges of the variable clock and the reference

clock.

4.1 Basic TDC

The goal of the TDC is to measure the time di↵erence Td between the rising edge of signal A

and B from figure 4.1. The result should be outputted in a digital format, hence time to digital

converter. The basic principle is to delay the signal A using a delay cell with delay TD, or the

resolution time of one delay element. Then the signal B is used to sample this delayed version

of A. If the output of the sampler equals 1, it means the delayed signal A has already switched

and the time di↵erence is larger than TD. If the output is 0 however it means the delayed signal

A has not yet switched, while the signal A itself has. This means the time di↵erence between

50 CHAPTER 4. TDC IMPLEMENTATION IN A RING OSCILLATOR

A

B

Td

Figure 4.1: Time di↵erence between two signals

the two signals is less than TD. By using a whole array of N delay cells, a time di↵erence upto

NTD can be calculated, with a resolution Tr of TD. The output of the samplers is a digital

thermometer coded word that can be converted to the required output by the digital logic.

In the case of ADPLL, the necessary time di↵erence is the one between the rising edge of the

variable clock fDCO and the reference clock fref . This method is the one used in Staszewski’s

design [1]. The maximal resolution of TDC depends on the minimal time delay of an inverter in

a certain technology, this is a value around 20 ps. However, the better the resolution becomes,

the larger the array of elements has to be to cover a certain time range. The required number

DQ

C

TD TD TD TD

DQ

C

DQ

C

DQ

C

A A1 A2 A3 A4

Q1 Q2 Q3 Q4

B

Figure 4.2: Layout of a simple TDC delay line

4.2 Vernier delay line 51

DQ

C

TD TD TD TD

DQ

C

DQ

C

DQ

C

TS TS TS TS

A A1 A2 A3 A4

B B1 B2 B3 B4

Q1 Q2 Q3 Q4

Figure 4.3: Layout of a Vernier delay line

N of elements, given a time span of Tmax is given by

N =Tmax

Tr(4.1)

In the case of the ADPLL, the maximum time di↵erence between the variable and reference

clock is one complete clock period of the variable clock. At a minimal bluetooth frequency of

2.4GHz, this equals 416 ps. If delay cells are designed for a resolution of 20 ps this results in a

required array with length 21. Using such a long array has some downsides. The time delay of

an inverter is not perfect. There will be some uncertainty on this value. Using a long array will

accumulate this error towards the end, meaning the later delay cells insert a larger quantisation

error. Then the quantisation error will increase, degrading the performance of the entire system.

Short lines seem better but this means a smaller time di↵erence can be measured for the same

resolution.

4.2 Vernier delay line

A similar technique, used to get a time resolution higher than the resolution time of a single

inverter, is the so called Vernier Delay line, shown in figure 4.3. Instead of sampling the delayed

versions of A with the signal B as clock, the signal B is now itself delayed by an inverter chain

with delay TS [7]. If the pulse at A comes earlier than the transistion at B, the delay TS has to

be smaller than TD. The signal A is delayed with an inverter chain with delay TD. The delayed

signal An, after a delay of n cells, is now sampled with the delayed signal Bn. Figure 4.4 shows

this principle. A Vernier delay line will measure the time it takes for pulse B to catch up with an

earlier pule A. The output of the flipflops is also thermometer coded. For example, in the case


of figure 4.4, the clock B has catched up with the signal A after the sixth delay. The ouput bit

format would be :“11111000...”. The resolution of a Vernier delay line can now be calculated.

Call n the number of the element where B has catched up with A, it is the number outputted in

thermometer format by the flipflops. Looking at figure 4.4 this leads to the following equations:

nTD > nTS +Td

(n – 1)TD < (n – 1)TS +Td

=) (n – 1)(TD – TS) < Td < n(TD – TS)

(4.2)

This means the resolution of of the Vernier delay cell equals the delay di↵erence of the two cells

used. The Vernier line su↵ers the same problems as the normal TDC. The higher the resolution

becomes, the longer the needed delay chain becomes to cover a certain range. An additional

problem with a vernier line is however that the total delay of the system increases as well. It

takes a time NTS before all flipflops have there final value. This means the system has to wait

this long before it can process the information. Depending on the application this might not

be acceptable. In practise, when both a high resolution and a long range are required, two

TDC’s might be used. A first one has a long range and a very coarse resolution. A second

TDC will than narrow down the time di↵erence. The second one has a fine resolution and a

range comparable to the resolution of the first TDC [8]. The method used in this work has some

similarities to this concept.

4.3 Implementation in a ring oscillator

4.3.1 Coarse fractional phase estimation

In the case of an ADPLL, a TDC is used to estimate the time di↵erence between the rising

edge of the variable output clock and the reference clock. This di↵erence has to be interpreted

as a phase di↵erence. Because of the use of a ring oscillator, di↵erent phase-flanks are already

available. The oscillator discussed in chapter 3 will be used. By sampling the output of every

delay cell, a phase resolution of 18 can be obtained. The di↵erential delay elements are simplified

to single non-inverting delay cells, the wire inversion is represented by the fact that the input of

the first cell is opposite to the output of the last cell. Since di↵erential delay cells are used, this

is in fact an accurate representation, by simple wire inversion of certain outputs this behaviour

is obtained. At the instance the variable output clock tranistions to 1, the fractional output

4.3 Implementation in a ring oscillator 53

Td

A B

A1 B1

TD TS

A2 B2

A3 B3

A4 B4

A5 B5

B6 A6

t

Figure 4.4: Propagation of signal and clock signal in the Vernier delay line


D3 D0 D1 D2 D3

C

DQQ0

C

DQ Q1

C

DQ Q2

C

DQ Q3

fDCO

fref

Figure 4.5: Model for coarse phase detection in the ring

Binary output fractional phase

1111 08

0111 18

0011 28

0001 38

0000 48

1000 58

1100 68

1110 78

Table 4.1: Conversion between sampler output and fractional phase part

phase = 0. This transition means the delay cell with index 3 has just switched from 0 to1. The

outputs of all other cells is also 1. A delay TD later, cell 0 will switch from 1 to 0. When this

has happened the fractional part of the output phase equals 18 . Another delay TD later the

second cell will switch to 0 and so one. By sampling every output of the output DCO clock, the

fractional phase can be determined with a resolution of 18 . The oscillator itself behaves as a delay

line of a TDC structure. Figure 4.6 shows what happens in the time domain during sampling.

Depending on the location of the reference clock rising edge, 8 di↵erent sampler outputs are

possible .

4.3.2 Fine fractional phase estimation

A phase quantisation of 1/8 is still too coarse in many applications. As a solution for finer

tuning, in this thesis a variation of the Vernier delay line will be used, where one of the delay


t

D3 = fDCO

t

t

t

D0

D1

D2

Rising edge refernce clock

�frac

Figure 4.6: Sampling the ring phase


t

D3 = fDCO

t

t

t

D0

D1

D2

Last switched edge

�frac

Nex switching edge

TD

�fine�coarse

Figure 4.7: Di↵erence between the coarse and fine fractional phase part

lines is the oscillator itself. The information from the coarse phase detection provides the digital

control logic with the knowledge which cell is switching at the rising edge of the reference clock.

The situation is presented in figure 4.7. To increase the phase information further, a method

is needed to estimate the time di↵erence between the last switched edge within the ring, and

the reference clock. In the example of figure 4.7, the coarse phase detection has detected that

the last clock transition was a rising edge of D0. Now the fine phase estimator will try to

determine the time di↵erence between this rising edge of D0 and the reference clock. This will

be implemented using a Vernier delay line. The last switched output in the ring represents the

signal A from figure 4.4, the reference clock is the sampling clock or the signal B. This last

clock transition is already connected to a delay array, namely the ring itself, with delay time

TD. There are 4 subsequent cells before the clock transition is back at it’s starting point. In a

first design, a 4 stage Vernier line will be used. Each delay element in the ring is sampled with

the delayed clock. 4 Delay cells are designed with delay time TS, delaying the reference clock.

The output of the Delay line is thermometer coded and has 5 possible outputs. Ranging from

“0000” to “1111”. The timing range of TD between two subsequent transitions in the ring has

to be divided into 5 equal part, meaning a time resolution of 15TD is required. In the previous

section it is shown that the frequency resolution of a Vernier line equals TD – TS so this leads


to the following requirement for TS:

(TD – TS) =TD

5

=) TS =4

5TD

(4.3)

However, the delay TD is not fixed. For a bluetooth application for example with frequency

between 2.4 and 2.5GHz, the value of TD varies between 50 ps and 52 ps. However if the center

value of 51 ps is used, this leads to

TS = 40.8 ps.

In an ideal case TS should be made tunable together with the ring tuning, but since only a small

tuning range is used relative to the frequency, one could opt to take TS fixed and accept a small

error when fDCO deviates from its center value. Because the array is short, error propagation is

not that much of an issue.

Unfortunately, when the reference clock rising edge occurs, any of the 4 delay cells can be the

the one switching. So any of the 4 cells can have to be the one at the start of the Vernier delay

line. For now, the only solution to e↵ectively take care of this problem is to sample every cell

output with every delay of the clock, schematically shown in figure 4.8. TDCik in the figure

means the k’th bit of the Vernier line output with Di as input signal. The performed algorithm

to determine the actual fractional phase error is then as follows:

• Use the 4 bits Q to determine what cell has just switched latest. This determines the

coarse phase error �coarse as stated in table 4.1. E.g. if the detected output pattern is

“0011”, this means the second cell has just switched form 1 to 0 and the third cell is now

in the process of switching. The coarse fractional phase is2

8.

• If cell i has just switched, select the i’th Vernier line to determine the fine fractional phase.

For example, using the previous case, the second cell has switched, so a multiplexer selects

the second Vernier line.

• Convert the 4 bits from the selected delay line from thermometer coding to the desired

digital format in units of 1/5, using table 4.2. If there is an ambiguity, use the actual bit

level, element i has switched to, to determine the correct fine fractional part. E.g. If the

output of the second delay line is “0000”, the fractional phase might either be0

5or

4

5.

Because the the second delay element switched from 1 to 0, an output of 0000 means the

delayed clock pulse did not overtake the delayed signal after the fourth delay. The fine

fractional part equals4

5.


D3 D0 D1 D2 D3

C

DQ

Q0

C

DQ

Q1

C

DQ

Q2

C

DQ

Q3

fDCO

fref

C

DQ

TDC00

C

DQ TDC01

C

DQ TDC02

C

DQ TDC03

TDC13

TDC23

TDC33

C1 C2 C3 C4fref TS TS TS TS

C

DQ

TDC10

C

DQ

C

DQ

C

DQ

C

DQ

TDC20

C

DQ

C

DQ

C

DQ

C

DQ

TDC30

C

DQ

C

DQ

C

DQ

D0

D0

D0

D0

D1

D1

D1

D1

D2

D2

D2

D2

D3

D3

D3

D3

C1 C2 C3 C4

C1 C2 C3 C4

C1 C2 C3 C4

C1 C2 C3 C4

TDC11

TDC21

TDC31

TDC12

TDC22

TDC32

Figure 4.8: Full TDC implementation with Vernier lines


Binary output fine fractional phase

0000/1111 05

0001/1110 15

0011/1100 25

0111/1000 35

1111/0000 45

Table 4.2: Conversion between Vernier line output and the fine fractional phase part

• Add the coarse and the fine phase to end up with the actual fractional phase. E.g.2

8+

4

40=

14

40

It is clear that two di↵erent Vernier outputs result in the same phase. This is because the phase

represents the time di↵erence between a transition of a delay element in the ring and the rising

edge of the reference clock. This transition can be either positive or negative however. But only

in the two extreme cases is there an ambiguity that can be solved by knowing the transition

direction.

61

Chapter 5

Digital implementation

Finally in this chapter the digital control logic is discussed. It converts the information from

the phase detector and the Frequency Control Word to the digital tuning words for the DCO.

In the previous sections, digital words where assumed to represent integer number without any

resolution or finite range. O↵ course in a practical implementation all numbers are represented

by a finite number of bits. E↵ects of possible rounding and saturation/overflow will have to

be investigated. The actual digital design was made in verilog, which allows for mixed signal

analysis together with the analog blocks in Cadence.

5.1 Clock retiming

In [1] and other references (e.g. [9]), the principle of clock retiming is used. This is because the

ADPLL is a multirate system with two clock domains that are not synchronous. This means

care has to be taken to avoid metastability. Metastability occurs when a value is sampled at

the moment it is in an undefined logical area. In this case in can take a very long time for the

output of this block to reach a legal value itself, theoretically infinitely long. Clock retiming

means that the reference clock is resampled so that is coincides with the next rising edge of

the variable clock fDCO, the principle is shown in figure 5.1. However this mechanism is itself

vulnerable for metastability issues. In this work however, it will be attempted to avoid clock

resampling. In other works, the possibility to avoid clock retiming in di↵erent ways has also

been discussed [11]. At instances where metastability may occur special care will have to be

62 CHAPTER 5. DIGITAL IMPLEMENTATION

fDCO

fref

fretime

Figure 5.1: Principle of reference clock retiming

taken to avoid this. When clock retiming is used, an issue that can arise is the fact that the

system is clocked with a non uniform clock. Also according to [11] this can cause spurs in the

output phase noise due to coupling on chip. In thesis, the reference clock will be delayed a

certain fixed time before it triggers the digital logic. This way, input signals coming from the

analog parts of the design should have enough time to reach there final value, especially when it

is made sure that metastability is avoided there too. This delayed clock used in the system will

be denoted as fsys. Anyway, if would appear that metastability is an issue, the clock retiming

can be added to this circuit, all other blocks would remain the same.

5.2 Phase acquisition

The frequency control in the ADPLL is simply done by generating a FCW, or Frequency Control

Word and applying this to the digital block. Generating the reference phase �ref is done by

accumulating FCW. The output frequency is between 2.4 and 2.5GHz. With the reference

frequency of 50MHz, this means FCW can take a value between 48 and 50. An o↵set of 47 is

introduced. This means FCW can take a value between 1 and 3, and less bits are required. 4

bits will be used for the integer part of FCW (2 would su�ce). Of course, the most important

part is the fractional tuning of the output frequency. For this an additional 15 fractional bits

are used. Leading to a possible frequency resolution of

50MHz · 2–15 = 1.5 kHz. (5.1)

Which is higher than the frequency resolution of the used DCO. A standard accumulator accu-

mulates this FCW every fsys, generating the signal �ref . Phase is a continuously rising function.

5.2 Phase acquisition 63

This is not possible with actual digital words. Therefore a limited number of integer bits is

chosen. 8 in this case. This allows the reference phase to have a value between 0 and 255. The

accumulator will act as a modulo operator, when it reaches the maximal value it rolls over to

the minimal. This leads to the following equation for the reference phase:

�ref(n) = mod(�ref(n – 1) + FCW, 219). (5.2)

The variable phase �dco is a bit more complicated because it consists out of a an integer part

and a fractional part. This fractional part is itself composed out of a coarse and a fine part.

Only the integer part is accumulated. This is because the exact number of integer variable clock

transitions is known exactly, only the current fractional part between the current reference flank

and the previous variable transition is needed. The integer phase word PHI is accumulated by

a counter clocked by the variable clock fdco

PHI, internal(k) = PHI, internal(k – 1) + 1. (5.3)

This internal value is not o↵ered to the digital control logic, only when fref triggers will an

output value be generated. If between times k=N and k=N+1 the reference clock becomes high,

the value PHI, internal(N) is exported as value. However this will not happen at the rising edge

of fref , but at the next rising edge of the variable clock. The reference clock will only toggle an

internal variable telling the counter to output its current value and reset the internal counter.

It is here that metastability can occur, but the use of this one internal variable should improve

the situation. When rising edge of fref and fdco coincides it is possible that the internal variable

is in an undefined state at the time the counter tries to decide if it should count the rising DCO

edge, or reset and output its current value. However the problem lies only with this one bit

variable. There will never be a situation when the counter value has to be outputted before all

values have reached a stable state. With good circuit design it should be possible to always force

this internal bit in to a defined state, during coinciding flanks its precise value does not matter.

The counter will either decide the variable clock phase comes first or the other way around.

Figure 5.2 showes a state model of the digital counter. It also mentiones the output state, which

will be used later to solve mismatch between the integer counter and fractional TDC. The delay

between fsys and fref must be high enough to make sure PHI is stable at the moment the digital

logic is triggered by fsys. There might still be a mismatch between the integer phase counter

and the fractional TDC. When the reference clock is very close to a rising edge of the DCO it

is possible that the edge is counted by the counter, while the TDC registers the the clock to

come after the DCO pulse. The counter and TDC function independent of each other so there

is no way to avoid this due to small mismatches. In that case the fractional phase error will


Start counter at P int = 0

Wait for clock transistion

state int=0, update=0

Rising edge fdco

falling edge fdcoRising edge fref

Is update =1?

yes no

P int++Output=P int

P int=1OutputState=state int

state int=0

Is update =1?

yes

state int=1

update=1

no

Figure 5.2: State model of the integer phase counter

5.3 Phase error 65

be 3940 , while it should be equal to 0. That is why the counter outputs the clock state. This

state was the clock level registered by the counter when the reference clack transitioned. If it

is 0, the last DCO transition was not yet counted, if it is 1, it was. If the clock state equals 1

while the fractional part equals 39, a mismatch is detected and a correction block can change

the fractional phase to 0.

At the rising edge of fsys the integer part of the variable DCO phase is updated:

�dco(n) = �dco(n – 1) + PHI(n) (5.4)

PHI is also an 8 bit integer word.

5.3 Phase error

Once the reference and variable phase are updated at the rate of fsys, a large part of the rest of

the system can be completely combinatorial. The fractional phase error is only bu↵ered at fref ,

no accumulation. The phase error can now be calculated, it is given by

��(n) = �ref(n) – PHI(n) – �frac(n). (5.5)

Up to now the phase noise was expressed as a value representing 1/40 of the phase. This value

represents the upper bound of the possible interval, to minimize the quantisation error, the phase

error should be quantised to the value in the middle of the interval. Or the current value should

be subtracted with 1/80. The fractional phase will also be converted to a fixed point decimal

bit pattern with 15 fractional bits. This will introduce a very small rounding error. Both �ref

and PHI are unsigned cyclic numbers. The phase error however is a signed, fixed number. If

these two unsigned numbers are subtracted, and the result is interpreted as a two complement

signed number, this result is the corresponding phase error. It ranges from –128 to 127. This is

thus the maximal range of the phase error.

Next the phase error is filtered. This might either be just a multiplication with a constant

parameter, resulting in a type I PLL. Or an integrating filter might be used, resulting in a type

II loop. For a good implementation it would be best that the multiplicative factors are a power

of 2. In that case division can be performed by a simple bit shift, saving a lot of hardware

and proccesing power. The filtered phase error is the input for a normalised DCO called the

normalised tuning word (NTW). This means the NTW has to be divided by the DCO gain


KDCO. In the acquisition mode, this is about 1 MHz, meaning KDCO = 50. Eventually this

scaled NTW, called the OTW, is truncated, leaving only the 8 most significant bits. This is the

coarse tuning word and forms the output of the digital block, closing the loop.

5.4 Switching state

In the acquisition mode, the output frequency will track the desired frequency band. When it

reaches this frequency it will oscillate around it. If the OTW remains equal, or oscillates around

the same value, the ADPLL has to switch to tracking mode. There are di↵erent possibilities

to implement it, called gear shifting [1, p.142]. All modes have in common that the acquisition

tuning word is locked. Only the tracking tuning word will change from now on. One possibility

is the so called zero-phase restart. During mode shifting, this resets the input phase �ref and PHI

and at the same time changes the filter coe�cients. In this work was not chosen to implement

this method, but a method based on Autonomous gear shifting. This does not modify the value

of the accumulated phases. The principle is as follows. The fixed acquisition NTW is converted

back to a (filtered) phase error. The actual phase error is now subtracted by this value. What

remains is the information that was lost when the bits of NTW where punctuated. This new

phase error can now be filtered by a di↵erent loop constant, resulting in the tracking NTW,

that has to be scaled by the KDCO of the oscillator in tracking mode. In this case KDCO in the

tracking mode is50MHz

20 kHz= 2500

67

Chapter 6

Experimental results and conclusion

In this chapter result will be discussed that were obtained by simulating the previously dis-

cussed design. Results will be compared with theoretical phase noise analysis from chapter 2.

This will validate the correctness of the theoretical analysis and show remaining non-idealities.

Simulations will be done for a few di↵erent values of the loop filter. At first simulations will be

done without DCO phase noise to investigate the e↵ect of the loop on TDC quantisation noise.

Finally a simulation included DCO phase noise in performed.

6.1 PLL tracking

When a digital control word FCW is applied to the digital logic, the ADPLL output frequency

has to evolve towards this value. The validate this fact, a proportional loop filter ↵ = 0.5 is first

selected. Figure 6.1 shows the ADPLL output frequency in this case. The FCW is chosen equal

to72090

215= 2.2

Added with the o↵set of 47 the FCW represents a value of 49.2. With the reference frequency of

50MHz, this has to result in a desired output frequency of 2.46GHz. As the figure demonstrates,

the loop quickly tracks the desired frequency due to the high bandwidth. When the output is

close enough to the target frequency, the ADPLL goes into tracking mode. On figure 6.2 a detail

is shown of the output frequency during tracking mode Both figures immediately show the short

strong spurs that might occur during switching. This due to unideal switching in the tuning

circuit.

68 CHAPTER 6. EXPERIMENTAL RESULTS AND CONCLUSION

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 12440

2460

2480

2500

2520

2540

2560

2580

2600

2620

time (µs)

DCO

freq

uen

cy(M

Hz)

Figure 6.1: Instantanious output frequency of the ADPLL

0.5 0.55 0.6 0.65 0.7

2458.5

2459

2459.5

2460

2460.5

2461

2461.5

2462

2462.5

2463

time (µs)

DCO

freq

uen

cy(M

Hz)

Figure 6.2: Detail of the output frequency during tracking mode

6.2 Phase noise 69

2 2.2 2.4 2.6 2.8 3−0.015

−0.01

−0.005

0

0.005

0.01

0.015

0.02

time (µs))

Phase

dev

iation

Figure 6.3: Phase error in the output phase

6.2 Phase noise

To plot the phase noise spectrum, the information of output clock transitions has to be converted

to phase noise information. A module in the simulation test bench registers the time instances

of DCO clock transitions and writes these to a file. During lock, the output should ideally be

constant in frequency and these time instances have to form a linear rising function. The index

of a time instance represents the phase. However when phase noise is present these times will

not be on a straight line. The clock transistions of an ideal oscillator will be estimated by fitting

the best curve through the found times. This line has a slope 1fdco

. When the timestep at index

i is divided by this slope, the actual phase at time i is found. By substracting this value with

the ideal phase at index i (which is i) the phase error is found.

6.2.1 Proportional filter ↵=0.5

For the case of proportional loop filter this output phase error is plotted in figure 6.3. There

appears to be an oscillating behaviour in the output phase error, caused by the TDC resolution.

In analytical calculation, TDC noise was assumed to be completely random, but when the output

frequency is constant there appears to be some correlation between subsequent TDC quantisation

errors. This periodic disturbance should be seen as spurs in the output phase spectrum with


106

107

108

109

−180

−170

−160

−150

−140

−130

−120

−110

−100

−90

−80

−70

frequency (Hz)

PSD

(dBc)

SimulatedAnalytical

Figure 6.4: PSD of the phase noise for a proportional loop ↵ = 0.5

a frequency around 20MHz. This spectrum is shown in figure 6.4. When compared with the

theoretical phase noise, using the analysis from chapter 2, it appears that the simulated curve

is a few dBc above the theoretical result. An explanation could be that the TDC is not perfect

and the quantisation error is higher than the 1/40. The spurs at multiples of 20MHz are also

not modelled by this analysis.

6.2.2 Proportional filter ↵=1/256

An often used proprotional faction is 2–8. It results in a lot of TDC-noise suppression. When

a very good oscillator is used with low phase noise, this is indeed a good method to suppress

the TDC noise and reach very low phase noise levels for high demanding communication system

such as GSM. Figure 6.5 compares the simulation with the theoretical curve. The curves have

the same slope, and TDC phase noise is indeed suppressed a lot. However the di↵erence between

the two values is a lot higher than in the previous case. There also is a phase noise floor of

around –160 dBc. This might be caused by the fact that the time instances of the DCO clock

have a finite resolution in the simulation. This would introduce an output phase quantisation

error that can be modelled as white noise. Because of the high suppression however, spurs

have nearly disappeared. This might indicate that using a very high bandwidth and focus on

suppressing DCO noise might not be the ideal option. High suppression of TDC noise might

also be necessary to suppress spurs.

6.2 Phase noise 71

106

107

108

109

−180

−170

−160

−150

−140

−130

−120

−110

−100

−90

−80

−70

frequency (Hz)

PSD

(dBc)

SimulatedAnalytical

Figure 6.5: PSD of the phase noise for a proportional loop ↵ = 2–8

6.2.3 Type II loop

Finally the e↵ect of an integrating filter is examined in simulation. The used loop filter is

H(z) = 0.8 +0.1

z – 1. (6.1)

The resulting shaping of TDC noise is shown in figure 6.6. The result is similar as in figure 6.4,

and again there is the same o↵set between the two curves. Again spurs are present and not well

suppressed.

6.2.4 DCO noise

The biggest advantage of the type II loop is that it limits DCO phase noise at low frequencies.

As stated before, the actual noise performance of the DCO is disastrous. When extracting the

noise level and use it to model the DCO noise source, it completely dominates other noise sources

as shown in figure 6.7. The used DCO phase noise used in the model is

LDCO(f) =N0

f2

N0 = 60dBc(6.2)

This results in open loop DCO phase noise of –80 dBc at an o↵set 10MHz. The theoretical

total phase noise is now compared with the simulated value in figure 6.7. With the correct


106

107

108

109

−160

−150

−140

−130

−120

−110

−100

−90

−80

−70

frequency (Hz)

PSD

(dBc)

SimulatedAnalytical

Figure 6.6: Phase error PSD

noise level, the e↵ect of the ADPLL loop on output noise is nicely modelled. But as expected,

even with such a high bandwidth, there is a peak of 80 dBc. The oscillator is not suited for

communication purposes. Because of the integrating loop filter, phase noise starts to decrease

for lower frequency o↵sets, this behaviour is also clearly observed in the simulation.

6.3 Conclusions and further work

In this thesis, theoretical multirate models were developed.Experimental verification confirms

there validity, as injected TDC quantisation noise is indeed shaped as expected. DCO phase

noise is also shaped but has a very high value. However the theoretical model is correct and

predicts the DCO noise shaping. The used ring oscillator should be completely redesigned,

optimised for low phase noise, determined by the application. The behaviour of the integrated

TDC within the ring is quite good. However the simulated result is a few dB higher, what could

indicate that the TDC is less accurate than modelled. But indeed timing mismatches would

have this e↵ect. The TDC resolution budget is not yet depleted however. Choosing a ring with

more stages can only bring down the quantisation error.

As a general conclusion, the introduced design behaves as modelled, but more work is needed

in further optimising the analog blocks, before an actual prototype can be developed.

6.3 Conclusions and further work 73

104

105

106

107

108

109

−180

−160

−140

−120

−100

−80

−60

frequency(Hz)

PSD

(dBc)


Figure 6.7: Theoretical phase error for the type II loop, with actual DCO phase noise

106

107

108

109

−160

−150

−140

−130

−120

−110

−100

−90

−80

−70

frequency (Hz)

PSD

(dBc)

SimulatedAnalytical

Figure 6.8: Total phase noise, including DCO noise for a type II loop

BIBLIOGRAPHY 75

Bibliography

[1] Robert Bogdan Staszwski and Poras T. Balsara, All-Digital frequency synthesizer in deep-

submicron CMOS Wiley, New Jersey, 1st edition, 2006.

[2] John A. McNeills’c and David S.Ricketts, The designer’s guide to jitter in ring oscillators

Springer, New York, 2009.

[3] Asas A. Abidi, “Phase Noise and Jitter in CMOS Ring Oscillators”, IEEE journal of solid-

state circuits,vol.41, NO.8, p. 1803,1815. August 2006.

[4] Ioannis L. Syllaios and Poras T. Balsara, “Linear Time-Variant Modeling and Analysis”,

IEEE transactions on circuits and systems,vol.59, NO.11, p. 2495,2505. November 2012.

[5] Maarten Lietaert, “Chipontwerp van een gemengd analoog-digitale PLL voor frequentiesyn-

these”[dutch], M.S. thesis. ELIS,UGent,Gent.

2013

[6] Pieter Rombouts, “Geadvanceerd analoog ontwerp[dutch].

Ugent,2013.

[7] G.S. Jovanovic and M.K. Stojcev, “Vernier’s Delay Line Time–to–Digital Converter”, SCI-

ENTIFIC PUBLICATIONS OF THE STATE UNIVERSITY OF NOVI PAZAR, Faculty of

Electronic Engineering, Nis, Serbia, May 2009.

[8] Hongjin Kim, SoYoung Kim and Kang-Yoon Lee, “Low power FSK transmitter using all-

digital PLL for IEEE 802.15.4g application”, Analog Integr Circ Sig Process,vol.47,p. 599,612.

January 2013.

[9] Robert Bogdan Staszewski et al, “Spur-Free Multirate All Digital PLL for Mobile Phones in

65 nm CMOS”, IEEE journal of solid-state circuits,vol.46,p. 2904,2919. December 2011.

76 BIBLIOGRAPHY

[10] Prashanth Muppala, Saiyu Ren and George Yu-Heng Lee, “Design of high-frequency wide-

range all digital phase locked loop in 90 nm CMOS”, Analog Integrated Circ SIg Pro-

cess,vol.75,p.133,145. 2013.

[11] S. Mendel, “A phase-Domain All-Digital Phase-Locked Loop Architecture Without Refer-

ence Clock Retiming”, Circuits and Systems II,vol.56,no.11,p.860,864. November 2009.

[12] Ali Hajimiri and Thomas H. Lee, “A General Theory of Phase Noise in Electrical Oscilla-

tors”, IEEE journal of solid-state circuits,vol.33,no.2,p.179,194. February 1998.

[13] S. Mendel, “State-of-the-Art and Future Directions of High-Performance All-Digital

Frequency Synthesis in Nanometer CMOS”, IEEE transactions on circuits and sys-

tems,vol.58,no.7,p.1497,1510. July 2011.

LIST OF FIGURES 77

List of Figures

1.1 Basic principle of a frequency synthesiser . . . . . . . . . . . . . . . . . . . . . . 3

1.2 N-fractional PLL for frequency synthesis . . . . . . . . . . . . . . . . . . . . . . 3

1.3 PSD and charge pump used in many modern PLL’s . . . . . . . . . . . . . . . . 4

1.4 General schematic layout of the ADPLL . . . . . . . . . . . . . . . . . . . . . . 5

1.5 Relationship between DCO output and output phase . . . . . . . . . . . . . . . 6

1.6 Principle of fractional phase sampling at reference clock . . . . . . . . . . . . . . 6

2.1 ADPLL model in the phase domain . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Loop magnitude response for ↵ = 0.1 . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 The ADPLL in the phase domain including the main noise sources, all sampled

at the reference frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Comparison between the power spectra of a single frequency waveform. Both

with (right) and without (left) phase noise . . . . . . . . . . . . . . . . . . . . . 12

2.5 Real clock transitions vs. ideal clock . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.6 Di↵erent noise regions in oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.7 Transfer function for the DCO noise contribution to the output phase noise spec-

trum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

78 LIST OF FIGURES

2.8 Sampled output phase noise for di↵erent noise sources, proportional loop filter

with bandwidth ⇡ 1MHz( ↵=0.1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.9 Magnitude plot of an integrating loop filter: H(z) = 0.80.1

z – 1. . . . . . . . . . . 19

2.10 Magnitude of the noise transfer function for a type II ADPLL . . . . . . . . . . 19

2.11 Sampled output phase noise for di↵erent noise sources,type 2 loop filter, ↵ = 0.8

and � = 0.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.12 Multirate block diagram of the ADPLL . . . . . . . . . . . . . . . . . . . . . . . 21

2.13 Multirate block diagram of the ADPLL with blocks replaced for full operation in

DCO-clock domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.14 The e↵ect of upsampling on the power spectra with N = 3 . . . . . . . . . . . . 22

2.15 Down-up conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.16 Simplification of the multirate model . . . . . . . . . . . . . . . . . . . . . . . . 24

2.17 Block diagram of the multirate ADPLL without ⌃�-modulation . . . . . . . . . 24

2.18 Magnitude bode plot of the multirate open loop transfer function HLG(z) . . . . 25

2.19 Phase noise in the multirate system . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.1 Using a DAC to generate a control voltage for a standard analog VCO . . . . . 30

3.2 LC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.3 Standard single-ended ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.4 Switching of an ideal inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.5 Ring oscillators with di↵erantial delay cells . . . . . . . . . . . . . . . . . . . . . 33

3.6 Fully di↵erential delay cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.7 Latch structure concept of a pseudo-di↵erential delay cell . . . . . . . . . . . . . 34

LIST OF FIGURES 79

3.8 Circuit implementation of a pseudo-di↵erential delay-cell . . . . . . . . . . . . . 35

3.9 Layout of the tuning circuit in a di↵erential ring oscillator . . . . . . . . . . . . . 37

3.10 The tuning circuit of the ring oscillator . . . . . . . . . . . . . . . . . . . . . . . 38

3.11 Small signal model of the tuning circuit . . . . . . . . . . . . . . . . . . . . . . . 38

3.12 Principle of switched current sources for oscillator tuning . . . . . . . . . . . . . 40

3.13 Current through the nmos of a single delay cell . . . . . . . . . . . . . . . . . . . 41

3.14 Circuit implementation of the current tuning, including bias . . . . . . . . . . . . 42

3.15 Model of the switch in on (left) and o↵( right) state . . . . . . . . . . . . . . . . 42

3.16 Using a pmos switch to quickly charge the parasitic capacitance . . . . . . . . . . 43

3.17 Level shifter output bu↵er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.18 Di↵erential output of two sequential delay cells . . . . . . . . . . . . . . . . . . . 45

3.19 Changing frequency of the DCO over the full range by changing the coarse input 45

3.20 Detail of the DCO tuning, showing coarse frequency resolution . . . . . . . . . . 46

3.21 Open loop output phase noise of the DCO . . . . . . . . . . . . . . . . . . . . . . 47

4.1 Time di↵erence between two signals . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.2 Layout of a simple TDC delay line . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.3 Layout of a Vernier delay line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.4 Propagation of signal and clock signal in the Vernier delay line . . . . . . . . . . 53

4.5 Model for coarse phase detection in the ring . . . . . . . . . . . . . . . . . . . . . 54

4.6 Sampling the ring phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.7 Di↵erence between the coarse and fine fractional phase part . . . . . . . . . . . . 56

80 LIST OF FIGURES

4.8 Full TDC implementation with Vernier lines . . . . . . . . . . . . . . . . . . . . . 58

5.1 Principle of reference clock retiming . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.2 State model of the integer phase counter . . . . . . . . . . . . . . . . . . . . . . . 64

6.1 Instantanious output frequency of the ADPLL . . . . . . . . . . . . . . . . . . . 68

6.2 Detail of the output frequency during tracking mode . . . . . . . . . . . . . . . . 68

6.3 Phase error in the output phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.4 PSD of the phase noise for a proportional loop ↵ = 0.5 . . . . . . . . . . . . . . . 70

6.5 PSD of the phase noise for a proportional loop ↵ = 2–8 . . . . . . . . . . . . . . . 71

6.6 Phase error PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.7 Theoretical phase error for the type II loop, with actual DCO phase noise . . . . 73

6.8 Total phase noise, including DCO noise for a type II loop . . . . . . . . . . . . . 73

LIST OF TABLES 81

List of Tables

1.1 Bluetooth specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3.1 Transistor sizing of the delay cell in figure 3.8 . . . . . . . . . . . . . . . . . . . 36

4.1 Conversion between sampler output and fractional phase part . . . . . . . . . . . 54

4.2 Conversion between Vernier line output and the fine fractional phase part . . . . 59

integrated circuit design of a mixed analog digital pll

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