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Lecture 7 Interconnections 1: wire resistance, capacitance, and inductance Prof. José Luís Güntzel [email protected] Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering

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Page 1: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

Lecture 7 Interconnections 1: wire resistance, capacitance,

and inductance

Prof. José Luís Güntzel [email protected]

Integrated Circuits & Systems INE 5442

Federal University of Santa Catarina Center for Technology

Computer Science & Electronics Engineering

Page 2: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

Interconnections

Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.2

Introduction As CMOS technology scales down   Transistors become smaller:

  chips become denser   gate delays reduce

  Mean wire length increases   Wire parasitic effects do not scale with the same

factor as transistors:   Capacitances   Resistances   Inductances

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Interconnections

Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.3

Consequences of Parasitics As CMOS technology scales to deep submicron,

wire parasitics:   Increase contribution to propagation delay   Increase contribution on energy dissipation and the

power distribution   Introduces extra noise, affecting circuit reliability

Page 4: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

Interconnections

Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.4

Wire Delay vs. Gate Delay

Source: E.B. Friedman, 1st NOC Workshop, DATE 2006.

Wire delays became dominant over gate delays in 0.35µm technologies

Page 5: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

Interconnections

Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.5

Wire Geometry

substrate

dielectric

Current flow

W

L

H

tdi

S

  Line pitch = W+S   Aspect Ratio: AR= H/W

  Old processes: AR <<1   Submicron processes: AR ~2

Page 6: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

Interconnections

Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.6

A First Glance

Transistor

Via

M1 M2 M3

M4

M5

M6

Isolation

Page 7: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

Interconnections

Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.7

schematics physical

Source: Rabaey; Chandrakasan; Nikolic, 2003

A First Glance

Page 8: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

Interconnections

Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.8

Wire Models All-inclusive model Capacitance-only

Source: Rabaey; Chandrakasan; Nikolic, 2003

Page 9: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

Interconnections

Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.9

Wire Models - Simplifying All-inclusive model Capacitance-only

  Inductive effects can be ignored if resistance of wire is substantial enough (e.g., long aluminum wires with small cross section)

  A capacitance-only model can be used when wires are short, the cross section of the wire is large, or the interconnect material has low resistivity

  Interwire capacitance can be ignored when the separation between neighboring wire is large, or when the wires only run together for a short distance

Page 10: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

Interconnections

Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.10

Layer Stack

  AMS 0.35µm has 3 metal layers   M1 used for intra-cell routing   M2 and M3 used for local and global routing (each one in

one direction)

  Contemporary (submicron) technologies have 6 to10 metal layers:

  M1: thin, narrow, used for high density cells   Mid layers: thicker and wider (density vs. speed)   Top layers: thickest, used for VDD, Gnd, Clock

Page 11: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.11

Wire Lenght

  Some global signals, such as clocks, are distributed all over the chip and may be significantly long

  For die sizes between 1 cm and 2 cm, wires can reach a length of 10 cm

Page 12: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.12

Wire Resistance Material property

Height (thickness)

Defined by manufacturer

Defined by the designer

Ohm’s law

R I

+ V -

Current flow

W

L

H

: sheet resistance, in Ω/ (ohms per square)

R1 R2

Obs.:

=

Page 13: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

Interconnections

Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.13

Wire Resistance

Source: Rabaey; Chandrakasan; Nikolic, 2003

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Interconnections

Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.14

Wire Resistance

Ex: Poly-resistor

L W

Polysilicon

P substrate

Metal Metal

: sheet resistance

: head resistance

Top view

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Interconnections

Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.15

Wire Resistance

Source: Rabaey; Chandrakasan; Nikolic, 2003

Sheet resistance values for a typical 0.25µm CMOS process

Page 16: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.16

Wire Resistance

Consider an aluminum wire with L=10cm and W=1µm, routed on the first aluminum layer. Assuming a sheet resistance of 0.075Ω/ , calculate its total resistance.

Rwire= 0.075 Ω/ x (0.1 x 106 µm) / (1 µm) = 7.5 kΩ

Consider that this wire were in poly, instead, which sheet resistance is175 Ω/ . Which would be the wire resistance under such circumstances?

Rwire= 175 Ω/ x (0.1 x 106 µm) / (1 µm) = 17.5 MΩ

Source: Rabaey; Chandrakasan; Nikolic, 2003

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Interconnections

Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.17

Wire Resistance

Silicides: WSi 2, TiSi 2 , PtSi 2 and TaSi Conductivity: 8-10 times better than Poly

n +

SiO2

Polysilicon Silicide

n +

MOS Transistor with Polycide Gate

Source: Rabaey; Chandrakasan; Nikolic, 2003

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.18

Simulation

Why using circuit simulators?  Designs can be quickly evaluated without (sometimes

very expensive) fabrication.  After design has been evaluated you can prototype it

before mass production.

A circuit simulator computes the response of the circuit to a particular stimulus. The simulator formulates the circuit equations and then numerically solves them.

Page 19: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.19

Simulation

Types of analyses:

 DC/DC sweep: Both stimuli and responses do not vary with time

 Transient: Responses vary with time

 AC/Noise: also called small-signal analysis, it computes the sinusoidal steady-state response

Page 20: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.20

Simulation What are the input data?

 Device Type (R, C, L, current sources, voltage sources, diodes, transistors)

 Device models/parameters/ dimensions

 How devices are connected

 Some circuit simulators:

 SPICE, PSPICE, HSPICE (Synopsys), Spectre (cadence), Smash, SpiceOpus (free!),….

SpiceOpus Page: http://www.spiceopus.si/

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.21

Simulation Use SpiceOpus to determine the (dc) I-V characteristic of a 1 kΩ resistor.

* this is resistortest.cir file v0 1 0 dc 10V r1 1 0 1k .end

r1

I

V0 + -

Node 1

Node 0

SpiceOpus (c) 1 -> source resistortest.cir SpiceOpus (c) 2 -> dc v0 -1V 1V 2mV SpiceOpus (c) 3 -> setplot dc1 SpiceOpus (c) 4 -> plot i(v0) xlabel v(1) ylabel current[A] SpiceOpus (c) 5 -> plot -1000*i(v0) xlabel v(1)[V] ylabel current[mA]

V=RI

R I

+ V -

Step 1: Create File resistortest.cir in the notepad

Step 2: run SpiceOpus with the following commands

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.22

Simulation

r1= 1 kΩ

I

V0 + -

Node 1

Node 0

Page 23: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.23

Simulation

SpiceOpus (c) 5 -> source currentdivider.cir SpiceOpus (c) 6 -> dc v0 -1 1 5m SpiceOpus (c) 7 -> setplot dc SpiceOpus (c) 8 -> plot 1000*i(v1) xlabel v(3)[V] ylabel current[mA]

r1= r2 =1 kΩ

I V0 +

- r1 r2

r3

r3= 0.5 kΩ 1V ≥ V0≥ -1V

Use SpiceOpus to determine the (dc) I-V characteristic of the circuit below

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.24

Wire Capacitance

Source: Rabaey; Chandrakasan; Nikolic, 2003

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.25

Wire Capacitance The parallel plate capacitor

Charge separation in a parallel-plate capacitor causes an internal electric field. A polarized dielectric spacer (orange) reduces the electric field and increases the capacitance.

Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV

The electric field (force) E between the plates of a parallel plate capacitor is uniform and given by E=V/d

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.26

Wire Capacitance

c int =εditdiWL

substrate

dielectric

Current flow

W

L

H

tdi

Electrical-field lines

In ICs, dielectric is SiO2: • εdi = εox= 3.9 x ε0 • tdi = tox • Cox = εo/tox [fF/μm2] is a technology parameter, defined by the Foundry

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.27

Wire Capacitance Permittivity

: permittivity of free space

Source: Rabaey; Chandrakasan; Nikolic, 2003

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.28

Wire Capacitance Fringing Capacitances

capacitance/unit length

w=W-H/2

tdi substrate

W

H thick oxide

cfringe

cfringe

cpp

cpp

Source: Rabaey; Chandrakasan; Nikolic, 2003

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.29

Wire Capacitance Fringing vs. Parallel Plate

Source: Rabaey; Chandrakasan; Nikolic, 2003

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.30

Wire Capacitance Interwire Capacitances

Source: Rabaey; Chandrakasan; Nikolic, 2003

Crosstalk: a signal can affect another nearby signal.

Substrate noise coupling

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.31

Wire Capacitance Wire Area and Fringe Capacitances for Typical 0.25 µm CMOS Process

Source: Rabaey; Chandrakasan; Nikolic, 2003

aF/µm2 aF/µm

Top

plat

e of

the

capa

cito

r

Bottom plate of the capacitor

Area cap. Fringe cap.

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.32

Wire Capacitance Interwire Capacitances per unit wire length for different interconnect layers (0.25 µm CMOS Process)

Source: Rabaey; Chandrakasan; Nikolic, 2003

Capacitances expressed in aF/µm. Assuming minimally spaced wires.

Layer Poly Al1 Al2 Al3 Al4 Al5 capacitance 40 95 85 85 85 115

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.33

Wire Capacitance Example: Consider an aluminum wire with L=10cm and W=1µm, routed on the first aluminum layer. Calculate its total capacitance by using capacitance values given in slide 7.24.

Answer: Total (ground) cap. = area (parallel plate) cap. + fringing cap. Area cap. = 0.1 x 106 µm2 x 30 aF/µm2 = 3 pF Fringing cap. = 2x (0.1 x 106 µm) x 40 aF/µm = 8 pF

Total cap. = 11 pF

Page 34: Integrated Circuits & Systemsguntzel/ine5442/slides/CSI-lecture-7-interconnectio… · Interconnections Lecture 7 – 2012/2 Prof. José Luís Güntze l INE/CTC/UFSC Integrated Circuits

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.34

Wire Capacitance Example: Suppose now that a second wire is routed alongside the first one, separated by the minimum allowed distance. Determine the couple capacitance by using couple capacitance data given in slide 7.25.

Answer: Cint = (0.1 x 106 µm) x 95 aF/µm = 9.5 pF

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.35

Wire Capacitance Example Cont. Interesting to notice that moving the wire to Al4 would lead to the following results: Area cap. = 0.1 x 106 µm2 x 6.5 aF/µm2 = 0.65 pF Fringing cap. = 2x (0.1 x 106 µm) x 14 aF/µm = 2.8 pF

Total (ground) cap. = 3.45 pF Cint = (0.1 x 106 µm) x 85 aF/µm = 8.5 pF

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Lecture 7 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 7.36

References

Rabaey J.; Chandrakasan A.; Nikolic B. “Digital Integrated Circuits: a design perspective.”, 2nd Edition, Prentice Hall, USA, 2003.