integrated circuits & systems - ufscguntzel/ine5442/slides/csi-lecture-6...lecture 6 cmos...

Lecture 6 CMOS Fabrication Process & Design Rules

Prof. José Luís Güntzel [email protected]

Integrated Circuits & Systems INE 5442

Federal University of Santa Catarina Center for Technology

Computer Science & Electronics Engineering

CMOS Fabrication Process & Design Rules

Lecture 6 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 6.2

N-channel (or NMOS) transistor

P-channel (or PMOS) transistor

Polysilicon (poly)

N well

Layout for CMOS Inverter (typical P substrate 0.35 µm tech.)

Active areas

P implant (drain & source)

N implant (drain & source)




NMOS transistor PMOS transistor

Polysilicon (poly)

N well

Layout for CMOS Inverter

P implant (drain & source)


Active area & P implant (well contact)

Active area & P implant

(substrate contact)

Active areas





Polysilicon

Metal 1

Contact holes

Layout for CMOS Inverter

Metal 2

Via 1

Gnd Vdd

Gnd Vdd





Layout for CMOS Inverter To study the CMOS process steps, we will disregard substrate and well contacts

Poly

N well P implant

(drain & source)


Gnd Vdd




NMOS transistor PMOS transistor Layout vs. AA’ Cross on Fabricated Structure

N well Field oxide

Transistor gate (poly)

P substrate

N implant

Transistor gate (poly)

Field oxide Field oxide

Gate (thin) oxide

Gate (thin) oxide P implant

Metal 1 Metal 2

A A’

Isolation oxide

N.B.: oxide = SiO2




N Well Creation

P substrate

Silicon oxide (SiO2)

Thickness of substrate is between 0.5 and 1.0 mm

A thin layer (“film”) of oxide (SiO2), typically with 10nm, is deposited through dry oxidation (which is slow, but allows for a good thickness control)




N Well Creation

P substrate


Silicon nitride (Si3N4)

A thicker layer (“film”) of “sacrificial” silicon nitride (Si3N4) is deposited through Plasma CVD (Chemical Vapor Deposition)




N Well Creation

P substrate



Photolithography using N well mask: 1. Spin deposition of photoresist (~1µm) 2. Wafer is put in oven to dry photoresist 3. Wafer surface is exposed to UV light through N well optical mask

Optical mask with N well pattern (Negative) photoresist

UV light

“N well layer” (pattern)

A A’




N Well Creation

P substrate



Photolithography using N well mask: 4. Unexposed photoresist is removed by using organic solvent 5. Wafer is “soft baked” at low temperature to hard remaining photoresist

Remaining photoresist




N Well Creation

P substrate



Nitride is selectively removed by plasma etching (photoresist serves as coat)





N Well Creation

P substrate




Nitride is selectively removed by plasma etching (photoresist serves as coat)




N Well Creation

P substrate



Remaining photoresist is removed with a mixture of acids




N Well Creation

P substrate



N well is formed by ion implantation: • Nitride is used as protecting coat

• Ions traverse oxide film

Ion implantation (N-type dopant)




N Well Creation

P substrate



N well is formed by ion implantation: • Nitride is used as protecting coat • Ions traverse oxide film

N well





N Well Creation

P substrate



N well

Nitride is selectively removed by plasma etching




N Well Creation

P substrate

N well

Oxide is removed by using Hydrofluoric acid (HF) The wafer is cleaned (SDR - spin, rinse and dry with nitrogen)




Field Oxide Growth

P substrate

N well

There are two types of regions ion wafer surface: • Active area (where transistors are)

• Field area (must isolate transistors)




Field Oxide Growth

P substrate

N well



After oxide and nitride deposition (similar to N well creation step), photolithography is performed with an optical mask containing the negative of active area pattern.

optical mask with negative pattern of active area

UV light

“Active area” layer (pattern)

A A’




Field Oxide Growth

P substrate

N well



Wet oxidation is used to grow a thick layer of oxide, that will serve as isolation between transistors




Field Oxide Growth

P substrate

N well



Wet oxidation is used to grow a thick layer of oxide (with a few hundreds of nanometers), that will serve as isolation between transistors




Field Oxide Growth

P substrate

N well

Nitride is selectively removed by plasma etching Oxide is removed by using Hydrofluoric acid (HF) The wafer is cleaned (SDR - spin, rinse and dry with nitrogen)

“Field oxide”




Field Oxide Growth

P substrate

N well

Nitride is selectively removed by plasma etching Oxide is removed by using Hydrofluoric acid (HF) The wafer is cleaned (SDR - spin, rinse and dry with nitrogen)




Gate Oxide Formation

P substrate

N well

Wafer surface is submitted to dry oxidation to grow a thin film of oxide (~100 Angstrom), referred to as “gate oxide”

“Gate oxide”




Polysilicon Deposition

P substrate

N well

Poly is deposited by CVD process using silane gas





P substrate

N well

Transistor gate pattern pattern is “printed” on wafer surface by using photolithography.

optical mask with negative pattern of poly

UV light

“Poly” layer (pattern)

A A’





P substrate

N well

UV light

“Poly” layer (pattern)

Transistor gate pattern pattern is “printed” on wafer surface by using photolithography.

A A’





P substrate

N well

Non-exposed poly is selectively removed by etching. The photoresist serves as coating.





P substrate

N well

Non-exposed poly is selectively removed by etching





P substrate

N well

Non-exposed thin oxide is selectively removed by etching




PMOS Transistor Drain and Source Creation

P substrate

N well

P implant pattern is “printed” on wafer surface by using photolithography.

Optical mask with P implant pattern

UV light

“P implant” layer (pattern)

A A’





P substrate

N well

P implant pattern is “printed” on wafer surface by using photolithography.

Optical mask with P implant pattern

UV light

“P implant” layer (pattern)

A A’





P substrate

N well

P-type dopants are implanted through ion implantation. Photoresist serves as coating

Ion implantation (P-type dopant)





P substrate

N well





NMOS Transistor Drain and Source Creation

P substrate

N well

N implant pattern is “printed” on wafer surface by using photolithography.

“N implant” layer (pattern)

Optical mask with N implant pattern

UV light A A’





P substrate

N well

N implant pattern is “printed” on wafer surface by using photolithography.

“N implant” layer (pattern)

Optical mask with N implant pattern

UV light A A’





P substrate

N well

N-type dopants are implanted through ion implantation Photoresist serves as coating






P substrate

N well





Isolation Oxide Deposition

P substrate

N well

A thick film of oxide is deposited through CVD




Contact Wholes Opening

P substrate

N well

Contact holes are “printed” on wafer surface by using photolithography.

“Contact” layer (pattern)

Optical mask with contacts pattern

UV light A A’





P substrate

N well

Contact holes are “printed” on wafer surface by using photolithography.

“Contact” layer (pattern)

Optical mask with contacts pattern

UV light A A’





P substrate

N well

Contact holes are dug on isolation oxide through etching





P substrate

N well

Remaining photoresist is removed





P substrate

N well




Metal 1 Deposition

P substrate

N well

Metal 1 is deposited through sputtering




Metal 1 Deposition

P substrate

N well

Undesired metal 1 is removed, leaving only desired connections

“Metal 1” layer (pattern)

Optical mask with metal 1 pattern

UV light A A’




Metal 1 Deposition

P substrate

N well

Undesired metal 1 is removed, leaving only desired connections

“Metal 1” layer (pattern)

Optical mask with metal 1 pattern

A A’ UV light




Metal 1 Deposition

P substrate

N well

Undesired metal 1 is removed through etching




Metal 1 Deposition

P substrate

N well

Photoresist is removed




P substrate

N well

Isolation Oxide Deposition

Another thick film of oxide is deposited through CVD to isolate metal 1 from metal 2




P substrate

N well

Similarly to metal 1 deposition

Metal 2 Deposition




NMOS transistor PMOS transistor Layout vs. AA’ Cross on Fabricated Structure

N well

P substrate

A A’




Conexões em cobre 0,11µm IBM

Fonte: Rabaey; Chandrakasan; Nikolic, 2003

Metal Layers in a Contemporary Technology




Dual-Well Trench-Isolated CMOS Process (Current)

Source: Rabaey; Chandrakasan; Nikolic, 2003

Epitaxial layer: Single-crystal film grown on silicon surface with controlled impurities, that can have fewer defects than native wafer surface.




Final Result




CMOS Process Layers Layer Color

N Well Gray Active Area Green N+ implant (N+ select) Yellow P+ implant (P+ select) Orange Polysilicon Red Metal 1 Medium blue Metal 2 Light blue Contact to drain/source Black Contract to polysilicon Black Via Light Gray

Colors may vary according to Foundry/technology/layout editor




W

L

1

1: mínima extensão da porta (poli) fora da área ativa

2: mínima extensão do implante fora da área ativa

2

L

1

W

2

3

4

3: mínima distância entre implante N e implante P

4: mínima distância entre implante N (área ativa) e poço N

Fonte: Fernanda Kastensmidt, EMicro2005




1: mínima largura de metal 1 2: mínima distância entre metal 1 3: mínima largura de metal 2 4: mínima distância entre metal 2 5: mínima largura do contado 6: mínima extensão de metal 1

para fora do contato 7: mínima distância entre contatos 8: mínima largura de via 9: mínima extensão de metal 2

para fora da via 10: mínima extensão de metal 1

para fora da via

1

2

3

4

5 6

7

8 9

10

Fonte: Fernanda Kastensmidt, EMicro2005




A

A B

B

Conectando Transistores em Série




A

A B

B





A B

X Y

X=Y se A=1 E B=1

A B

X Y





A A B B

X

Y

Conectando Transistores em Paralelo




X

A B

X

Y A B

X

Y

Problema: capacitância da “difusão” é muito grande!





Solução: usar metal para conexões, sempre que possível!

X=Y se A=1 OU B=1

A B

X

Y A B

X

Y





Dois Transistores em Série em Tecnol. 350nm

0,4µm

Lmin = 0.35µm

minimum contact spacing =0,4µm

0,45µm

0,4µm b

b

0,4µm

Lmin = 0.35µm

0,45µm

0,4µm

0,4µm a

b

b

0,4µm a

0,4µm

0,4µm

a=0,3µm (minimum diffusion contact to gate spacing) b=0,15µm (minimum diffusion enclosure to contact)

Two transistors in series with wider chanels (asuming typical 0.35 µm CMOS Design Rules)




in out

A Typical 350nm CMOS Inverter

0,4µm

0,4µm b

b

0,4µm

0,4µm

0,4µm b

b

Vdd

Gnd

PMOS: W=Wmin=0.35µm L=1.5 µm

NMOS: W=Wmin=0.35µm L=0.7 µm

in out

a=0,3µm (minimum diffusion contact to gate spacing)

b=0,15µm (minimum diffusion enclosure to contact)




in out

V DD

GND

in out

Another Inverter Layout

Polysilicon to connect PMOS to NMOS gate

Metal 1 to connect PMOS and NMOS drains

A given layout for a logic gate is referred to as “cell”




A

S

V DD

GND

B

A S

B

A B

Vdd

2-Input NAND Cell




A

V DD

GND

B

S

A

S

B

A

B

Vdd

2-Input NOR Cell




Standard Cells

in

Out

V DD

GND

A

V DD

GND

B

S

A

S

V DD

GND

B

Circuit layout is assembled by using pre-designed cell layouts made available in a library (“cell library”)

inversor nor2 nand2 ...




Standard Cell-Based Circuit Structure

Cells laid out in strips

VCC

GND

cells

roteamento sobre os transistores, em M2, M3, ...




Standard Cell-Based Circuit Structure




References

1.  RABAEY, J; CHANDRAKASAN, A.; NIKOLIC, B. Digital Integrated Circuits: a design perspective. 2nd Edition. Prentice Hall, 2003. ISBN: 0-13-090996-3.

2.  JAEGER, Richard C. “Introduction to Microelectronic Fabrication” 2nd Edition. (Modular Series on Solid State Devices, Vol V), Prentice Hall, 2002.

3.  REIS, Ricardo.(Organizador.) Concepção de Circuitos Integrados. Porto Alegre: Sagra-Luzzatto/UFRGS, 2002. 2a edição. Cap. 3. ISBN 85-241-0625-5

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