integrated dual-output converter

0278-0046 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. Seehttp://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI10.1109/TIE.2014.2327599, IEEE Transactions on Industrial Electronics

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Abstract— This paper presents a family of single-input-multi-

output (SIMO) dc-dc converter topologies which can provide one

step-up and multiple step-down outputs. These topologies are

synthesized by replacing the control switch of a boost converter

topology with series-connected switches and using the additional

switch nodes to generate step-down dc outputs. Compared to

separate converters, these topologies utilize lower number of

switches and are more reliable due to their inherent shoot-

through protection. Analysis shows that the topologies exhibit

similar dynamic behavior as individual buck and boost

converters. Hence, the control system methodology is same as

that of separate converters, with each output being precisely

regulated. The behavior of these converters has been illustrated

in this paper using the integrated dual-output converter (IDOC),

which has a step-up and a step-down output. The steady-state

characteristics and dynamic behavior of the converter have been

studied. An analog closed loop control system for the converter

has been described for regulation of both the outputs. The

operating principles have been experimentally validated using a

120 W prototype. Results show that the proposed converter has

very good cross-regulation to step load change as well as dynamic

reference change in either output. The measured efficiencies of

the IDOC prototype are around 90%.

Index Terms— DC-DC power converters, Integrated Dual-

Output Converter (IDOC), Single-Input-Multi-Output (SIMO).

I. INTRODUCTION

OWER converter architectures having multiple dc ports

(input/output) are used in a wide variety of applications.

Typical examples include hybrid electric vehicles [1], dc-

based nanogrids [2-4], LED drivers [5-6], stand-by power

supplies [7], bias supplies [8], etc. Single-input-multi-output

(SIMO) dc-dc converter stages have been utilized in many of

these applications. Fig. 1 (a) shows a representative system,

where three distinct outputs (one step-up output, vo1, and two

step-down outputs, vo2 and vo3) are obtained from a single dc

input using three separate power converters. In general, an N-

output system requires 2N number of switches for a high

efficiency synchronous implementation. For efficient

Manuscript received October 18, 2013; revised January 15, 2014, and

March 8, 2014; accepted March 22, 2014. Copyright © 2014 IEEE. Personal use of this material is permitted.

However, permission to use this material for any other purposes must be

obtained from the IEEE by sending a request to [email protected]. This work was supported by the Department of Science and Technology,

Government of India, under Grant SR/S3/EECE/0187/2012. This paper was

presented in part at the International Symposium on Industrial Electronics 2013, Taiwan.

The authors are with the Department of Electrical Engineering, Indian

Institute of Technology Kanpur, Uttar Pradesh 208016, India (email: [email protected]; [email protected]; [email protected]; [email protected]).

operation of systems using multiple outputs, there should be

proper coordination of control between each of the converters

for power flow management [9-10]. This is generally

accomplished by cooperative coordination between the

feedback control systems of the converters. Fig. 1 (b) shows

the system where a single integrated architecture is used to

interface the different outputs. These converters, denoted as

integrated multi-output converters (IMOC) in this paper,

utilize reduced number of switches ((N + 1) switches for N

outputs) compared to separate converters. The use of lower

number of switches reduces the cost of the switch and its

associated drivers. Also, due to its integrated architecture, all

the outputs of the system are regulated using the same set of

switches, and hence, the coordination control is easier.

The concept of SIMO has been reported in [11-27]. A class

of SIMO converters, discussed in [11-19], use one input to

create a high frequency ac which is coupled to multiple

secondary windings for multiple outputs (step-up or step-down

depending upon the turns‟ ratio). Due to magnetic coupling

associated between the outputs, precise regulation of each of

the outputs is difficult. For this purpose, different post-

regulation schemes have been utilized on the secondary side,

such as linear regulators, synchronous switch post-regulators

(SSPR) [13-15], etc. Various other isolated multi-output dc-dc

converter topologies have been reported in literature. In [16],

multiple full-bridge dc-dc converters have been integrated into

a single topology by having each converter share a common

leg. Special-connected two transformer (SCTT)-based designs

have been reported in [17-18], which provide better cross

regulation at all load conditions, and uses complementary

pulse width modulation. Resonant converter-based isolated

multi-output dc-dc converter [19] has also been proposed,

which have ZVS and ZCS for all its switches. In general,

isolated converters comprise of more circuit components, and

Integrated Dual-Output Converter

Olive Ray, Student Member, IEEE, Anil Prasad Josyula, Student Member, IEEE, Santanu Mishra,

Senior Member, IEEE, and Avinash Joshi

P

(a) (b)

Fig. 1. Schematic of power converter architectures with three dc outputs. (a) Separate dc-dc converters realizing the three outputs, and (b)

Integrated single-stage architecture interfacing the three outputs.




require complex control systems. The involvement of

magnetic elements in a multi-output architecture makes the

system bulkier. Also, in order to achieve improved

efficiencies, most of these topologies utilize synchronous

switches as well as soft switching. Hence, these topologies are

considered when galvanic isolation between the different ports

is necessary.

Different non-isolated SIMO converter designs have been

reported in literature, which include use of cascaded dc-dc

stages [20], time-multiplexed and current-channelized multi-

output converters [21], etc. Among the non-isolated designs,

the number of circuit elements used in cascaded stages is

more, but the outputs can be precisely regulated using simple

control systems. In contrast, multiplexed converters [21-26]

use reduced circuit components, but the control systems are

associated with various constraints due to time multiplexing,

operating modes, cross-regulation, etc [25]. A single-switch

coupled inductor based dual-output dc-dc converter has been

proposed in [27], which can provide two different dc outputs

from a single dc input.

The paper presents a non-isolated SIMO dc-dc architecture

which can provide a step-up and multiple step-down outputs

from a single dc input. The topology has been realized by

replacing the control switch of a boost converter topology by

series connected switches and using the resulting switch nodes

to synthesize additional outputs using low-pass filter

networks. The step-up as well as step-down gains achieved

are same as separate boost and buck converters, respectively.

However, compared to separate converters (Fig. 1 (a)), the

proposed structure uses lower number of switching elements.

Also, the converter has continuous currents both at the input as

well as the step-down output. Hence, compared to a

conventional buck or buck-boost converter, the input filter

requirement is lower. The complementary switching operation

need not have dead-time protection due to inherent protection

provided by the circuit topology. The control system is exactly

similar to those implemented for conventional buck and boost

converter, and hence, can be easily extended to this design for

precise regulation of each output.

Present day power electronic systems require multiple dc

outputs at different voltage levels. Auxiliary circuits are often

present in addition to the main power stage, and they should

be powered at low voltages, e.g., fuel cell system [28]. The

proposed converter can provide a step-up output, which forms

the main power stage, along with an auxiliary step-down

output. Some potential application areas of the converter are

solar-battery chargers, dc nanogrids, bias supplies, etc.

The paper is organized as follows: The next section

describes the proposed circuit modification principle for the

synthesis of the family of integrated multi-output dc-dc

converter (IMOC) topologies from a conventional boost

converter. The paper studies the integrated dual-output

converter (IDOC), which has two dc outputs - a step-up and a

step-down. The steady state characterization and dynamic

behavior of the IDOC have been shown in Section III. This is

followed by the description of a suitable control strategy in

Section IV. A comparison of the proposed converter with

conventional designs has been shown in Section V. The

converter behavior has been verified using a 120 W laboratory

prototype and is shown in Section VI. Section VII provides a

brief discussion on other possible IMOC topologies and their

PWM control. Section VIII concludes the paper.

II. PROPOSED CIRCUIT MODIFICATION PRINCIPLE FOR

SYNTHESIS OF INTEGRATED MULTI-OUTPUT CONVERTERS

Fig. 2 (a) shows the schematic of a conventional boost

converter with the single control switch Sa. The switch node

voltage vsn corresponding to gate signal GSa is shown in Fig. 2

(b). The switch node voltage is equal to zero when the switch

Sa is turned on and is clamped to the boost

output voltage (vo) when the switch is off (neglecting diode

drop) . Fig. 2 (c) shows the boost

converter circuit when the switch Sa is replaced by two series-

connected switches S1 and S2. For boost operation (Da

interval), both the switches need to be turned on at the same

time. The interval of Fig. 2 (b) can be achieved by turning

off either S1 or S2 or both in Fig. 2 (c), and the switch node

voltage vsn1 equals to vo. If during this interval ( ), switches

S1 and S2 are switched in a complementary manner, the switch

node vsn2 can be used as a buck output with input voltage equal

(a) (c)

(b) (d) (e)

Fig. 2. Principle of circuit modification for the synthesis of single-input-multi-output (SIMO) dc-dc converters. (a) Conventional boost converter, (b)

switch node waveforms corresponding to the gate control signal GSa, (c) boost converter switch Sa is replaced by the series connected switches S1 and S2, (d) integrated dual-output converter (IDOC) obtained by using the proposed circuit modification shown in Fig. 2 (c), and (e) the circuit modification

principle has been extended to obtain integrated multi-output dc-dc converters (IMOC).




to vo. The resulting circuit has been shown in Fig. 2 (d), where

inductor L2 and capacitor C2 form the low pass filter. Thus the

proposed modification results in boost converter as well as the

buck converter being integrated in a single topology. Hence, in

this paper this converter is regarded as integrated dual-output

converter (IDOC) and the behavioral characteristic of the

converter has been studied. The same set of switches S1 and S2

are used to regulate both the outputs. The proposed circuit

modification principle can be extended to achieve multiple dc

outputs by replacing the boost converter control switch Sa with

N-number of series connected switches and filter networks.

Fig. 2 (e) shows the schematic of the multi-output converter.

This concept leads to the use of only (N + 1) switches for N-

outputs, compared to 2N switches when individual converters

are used. A similar circuit modification has been proposed in

[29] to generate hybrid (simultaneous dc and ac) outputs from

a boost converter.

Since both step-up as well as step-down operations are

accomplished using only the two switches S1 and S2, the major

challenges pertaining to the IDOC are: (a) its ability to

regulate each of the individual outputs precisely. This requires

defining two control variables (duty ratios D1 and D2) for the

purpose of controlling both outputs, (b) to have better cross-

regulation behavior due to changes in the other output, and (c)

to devise a suitable control system to coordinate the power

flow between the different outputs. These issues will be

addressed in the next section.

III. ANALYSIS OF IDOC

A. Switching Intervals

The schematic of the proposed IDOC, having dual dc

outputs, has been shown in Fig. 2 (d). The paper considers

continuous conduction mode of operation (CCM) and unless

stated, all the subsequent analysis in this work would consider

this assumption. The converter has been implemented using

two bidirectional switches S1 and S2. These two switches

would result in four possible operating states, three of which

are distinct and thus results in three different switching

intervals of the converter. These intervals are discussed in the

following subsections.

1) Interval I (t1~t2): Both S1 & S2 are on [Fig. 3 (a)]

Switching interval I is equivalent to the control switch Sa

(Fig. 2 (a)) of a conventional boost converter being turned

„on‟. The diode D is reverse biased during this interval. The

inductor current iL1 builds up, while the buck inductor current

iL2 freewheels through the switch S2. With respect to the

waveforms shown in Fig. 4 and considering the dc loads Ro1

and Ro2 at the step-up and step-down terminals respectively,

for a time D1.Ts, (where Ts = switching period), (1)-(4) shows

the expressions for the different inductor currents and the

capacitor voltages. This time-duration for Interval I operation

is defined by duty ratio D1. (1)

(2)

(3)

(4)

2) Interval II (t0~t1 and t2~t3): S1 is on & S2 is off [Fig. 3 (b)]

During this interval, the inductor current iL1 is distributed into

two components- one is flowing through the diode D and the

other portion is equal to the buck inductor current iL2. The

step-down converter draws energy from the source during this

interval. Unlike conventional boost converter, the diode

current iD is equal to the difference between the inductor

currents iL1 and iL2, and hence its magnitude decides whether

the converter operates in CCM. The switch node voltage (va)

is equal to the step-up output voltage vo1. The time duration for

Interval II operation is defined to have a duty cycle of D2.

During this interval, (referring to Fig. 4),

Fig. 4. Typical waveforms of the switch node voltages, the inductor and

the diode currents. The duty cycles D1 and D2 (corresponding to the gate

signals GS1 and GS2, respectively) for the purpose of controlling the dual

outputs have also been shown.

(a) (b) (c)

Fig. 3. Equivalent circuit of IDOC at different operating intervals. When a switch is „on‟, it is shown as a short, while an open denotes a switch being

„off‟. The figure shows equivalent circuits during: (a) interval I (Duty is D1), (b) interval II (Duty is D2), and (c) interval III.




(5)

(6)

(7)

(8)

3) Interval III (t3~t4): S1 is off & S2 is on (or Both S1 & S2 are

off) [Fig. 3 (c)]

In this interval, the inductor current iL2 freewheels through the

switch S2 or through its anti-parallel diode (if S2 is not being

gated). This interval is thus analogous to freewheel period

associated with conventional buck converters, either the lower

switch conducts in synchronous switching scheme or the diode

conducts. The diode D conducts the inductor current iL1.

Hence, both the inductors give out their energy to their

respective outputs.

During this interval, (9)

(10)

(11)

(12)

Fig. 4 shows typical waveforms of the inductor currents iL1,

iL2, and the switch node voltages va and vb at different

operating modes. The switching strategy makes the converter

to operate in the interval sequence (III), (II), (I), (II), (III)

during each period. It is important to note that Mode III in Fig.

4 shows GS1 and GS2 being turned off. The waveforms would

be same if during Mode III, GS2 is switched on, thus resulting

in synchronous switching operation.

B. Steady State Behavior

1) Voltage conversion ratio

For the purpose of analysis, small ripple approximation for the

inductor currents and capacitor voltages has been assumed.

Thus the expressions for the voltage conversions can be

derived from equations (1)-(12), as follows:

For the inductor L1,

Hence, (13)

Similarly, for inductor L2,

Hence, (14)

Thus,

(15)

From equations (13) and (15), it can be seen that the two dc

outputs of the IDOC can be regulated using the two control

variables D1 and D2. These duty cycles are defined as the time

duration for intervals I and II, respectively. The step-up output

depends upon the interval when both the switches are turned

„on‟ simultaneously (dependent upon duty D1) while, the step-

down output is regulated solely using the switch Q1, when Q2

is „off‟ (dependent upon both D1 and D2). The step-up output

voltage, thus, effectively acts as input to the step-down

operation. Fig. 5 shows the step-down gain-surface with the

variation of duty cycles D1 and D2.

2) Range of output voltages

The duty cycles that control both step-up as well as the step-

down voltages have been described in the previous section and

illustrated in Fig. 4. Because they share the same switching

period, the duty cycles D1 and D2 should satisfy (16).

(16)

For any particular value of the duty cycle D1, the step-down

gain varies within the range:

(17)

Thus, the IDOC can provide step-down output ranges varying

from zero to the input voltage. Compared to a conventional

buck converter, the IDOC can provide wide step-down outputs

at acceptable duty ratios of switches. This is because the step-

down output depends upon both D1 and D2, instead of only

one duty cycle as in the case of a buck converter. This

characteristic has been verified in the experimental section.

Similarly, the step-up gain varies between:

(18)

Thus, the IDOC preserves the qualities of both buck as well as

boost converters in an integrated architecture.

3) Input Current Expression

Assuming the input current to be iin (=iL1) and the output

currents io1 and io2, the power balance equation for the IDOC,

neglecting any loss component, can be written as:

or, (19)

Step-down

component

Step-up

component

Fig. 5. Theoretical step-down gain surface of IDOC with variation of

duty cycles D1 and D2. Here, the X-coordinates correspond to D2 and Y

coordinates correspond to D1.




Thus, compared to conventional boost converters, the input

current for the IDOC is higher, due to the additional power

drawn by the step-down load. Typical inductor current

waveforms have been shown in Fig. 4.

C. Boundary between CCM and DCM

During light load conditions, the diode current of a

conventional boost converter becomes zero. This results in

discontinuous conduction mode (DCM) of operation [30].

This phenomenon of DCM occurs in the IDOC during interval

III, and its analysis is similar to that of a conventional boost

converter. In addition to this DCM, the diode current of the

IDOC can also become zero during interval II. This condition,

referred to as pseudo-DCM in this paper, occurs for a

particular relationship between the step-up and step-down

loads as presented in the following discussion.

Fig. 3 (b) shows that the current iL1 distributes into iD and iL2

during interval II. The IDOC operates in CCM operation as

long as iL1 ≥ iL2.The following analysis is carried out

considering the switching strategy when the ripple in iL2 is

higher. This occurs when the IDOC operates in an interval

sequence of (I), (II), (III) during each switching period. The

condition for CCM operation, derived below, would always

hold true if any other PWM scheme is used, e.g., interval II is

divided in two parts as shown in Fig. 4. Considering the values

of iL1 and iL2 to be and (superscript „23‟ refers to the

change of intervals), when there is a transition from interval II

to III, the condition for CCM operation can be written as

follows.

(20)

It is to be noted that is the maximum value of iL2 during

a switching interval. The relation between the inductor

currents and shown in relation (20) can be rewritten as

shown in (21), where the expression for the inductor currents

are substituted.

(21)

Relation (21) can be simplified using relations (13), (15) and

(19), considering IL1 (=Iin) and IL2 to be the average values of

currents in the inductors L1 and L2, as shown in relation (22).

(22)

Relation (22) shows that for a given value of Ro2, there is a

maximum value of Ro1, below which the converter operates in

CCM.

D. Pseudo-DCM condition of IDOC

The pseudo-DCM condition occurs within switching

interval II of the IDOC, and unlike conventional DCM of a

boost converter, the input inductor current (iL1) remains non-

zero during this condition, and hence it is called as pseudo-

DCM. As shown in the equivalent circuit, for this condition

(Fig. 6), the switch S2 and the diode D are non-conducting for

a time Db.Ts. The inductor waveforms have been shown in

Fig. 7. The interval II thus comprises of two distinct regions:

(a) when the diode current is non-zero (equal to Da.Ts), and (b)

when diode current is zero (equal to Db.Ts) (such

that ). During pseudo-DCM both the inductor

currents iL1 and iL2 rise with the same slope (as given by (23)),

and the switch node voltage is a function of the inductor

values (va,pDCM and vb,pDCM as shown in (24)) as well as the

input and step-down output voltages.

(23)

(24)

Based on (23) and (24), and using volt-sec. balance, the input-

output relations for both the outputs of the IDOC can be

derived as given by relations (25) and (26).

(25)

(26)

where, ,

and (27)

From (25) and (26), we conclude that the output voltage

expressions during pseudo-DCM are also dependent upon the

ratio of inductances as well as the loads. The operation of the

IDOC during this mode has been validated in the experimental

section. Also, the transition from CCM to pseudo-DCM is

smooth because, putting Db = 0 and Da = D2 in relations (25)

and (26), make them equal to (13) and (15), respectively.

Fig. 7. Inductor currents (iL1 and iL2) as well as diode current (iD)

waveforms during pseudo-DCM (shaded region within Interval

II).

Fig. 6. Equivalent circuit of IDOC during Pseudo-DCM.




E. Component Selection: Semiconductor stress

The IDOC requires one less switch compared to two

separate converters. This reduction in the number of switches

increase as the number of outputs increase. The equations

governing the design of passive components of the IDOC are

dependent upon the allowable ripple content of the state

variables. The design equations are similar to those associated

with conventional buck and boost converters [30]. However,

for the IDOC, both the switches and the diode should be rated

for the step-up output voltage (vo1). This is because the

effective input voltage for the step-down output equals to the

step-up output voltage. Since, IDOC is a dual-output converter

also having a step-up output; the switches should be rated for

the output voltage (vo1) as in a boost converter. Also,

compared to a buck converter, for the same ripple

specifications, inductor L2 would have higher value. The

switches S1 and S2 conduct higher current compared to

conventional converters because, in the IDOC, the input

current magnitude is greater than conventional boost

converter, as shown in relation (19). The switch current

stresses for each interval have been shown in Table 2. A

comparison of the proposed IDOC with conventional buck as

well as boost converters have been done in Section V. A

design example has been presented in the next Section with its

experimental validation shown in section VI.

IV. CONVERTER DYNAMICS AND CONTROL

A. Design Specifications

The operation of the IDOC in continuous conduction mode

has been validated using a laboratory prototype. TABLE 1

shows the input-output specifications for the design example.

Based upon these specifications, the design of closed loop

control system for the purpose of regulation of both the

outputs has been described in the following subsections.

B. State-Space Analysis

The state-space model for the IDOC can be derived by

considering the averaged inductor voltages and the capacitor

currents in each switching period [30]. Equation (28) shows

the state-space equations for the IDOC.

(28)

The expressions for system matrix [A] and the input matrices

[B1] and [B2] are provided in APPENDIX A. The small signal

model for the IDOC considering ideal elements has been

shown in Fig. 8. However, for the purpose of deriving the

compensator, the influence of non-idealities has also been

incorporated. The step-up output of IDOC is regulated using

the duty cycle D1, while the step-down output is regulated by

D2, while keeping D1 constant. The position of poles and zeros

of the plant models of separate buck as well as boost

converters are similar to that of the IDOC. Thus, the design of

compensators for buck as well as boost converters can be

easily extended to the IDOC. This simplifies the controller

design methodology, which is implemented in this work using

analog control.

C. PWM control strategy

In this paper, a simple control scheme has been described,

which directly utilizes the control structure of conventional

buck as well as boost converters with minimum changes.

Alternate control architectures, resulting in higher efficiencies

are possible; but they would require different PWM control

structures compared to those used for separate converters. One

possible scheme is to use synchronous switching (S2 is turned

on during Interval III). For the IDOC, the modulating signals

(vGS1_mod and vGS2_mod) are compared to the same carrier, with

switch S1 being provided with a PWM signal of duty (D1 +

D2) and S2 being provided with a signal of duty D1. The main

constraint regarding the control is given by relation (16). Fig.

9 shows the reference control signals and the corresponding

duty cycles for the IDOC. The generalized control architecture

for N-output IMOC is shown in Fig. 10. where, the

compensators used to control individual converters can be

directly used, and the error amplifier (EA) output of the

bottom-most switch (vGSn_mod) controls the topmost dc output

(vo1). Due to the integrated structure, the EA reference of each

higher stage is the sum of the EA output of the bottom stage

and the present stage EA value. The controller implementation

for the IDOC is shown in Fig. 11. Since, D1 and D2 of IDOC

can be regulated separately (whenever relation (16) is

satisfied) we can have independent control of step-up as well

as the step-down outputs.

Fig. 9. Reference control signals for PWM generation in IDOC.

Fig. 8. Small signal model for the IDOC.

TABLE 1. DESIGN EXAMPLE SPECIFICATIONS FOR THE IDOC Parameter Attributes

Input Voltage (Vin) 12 V

Step-up Output Voltage (Vo1) 18 V

Step-down Output Voltage (Vo2) 6 V

Step-Up dc Load (Io1) 5 A

Step-Down dc Load (Io2) 5 A

Switching Frequency 100 kHz




D. Controller design

Based upon the state-space model, the control to output

transfer functions for regulating both the outputs can be

derived. The step-up output voltage is regulated by the duty

ratio D1 and hence, the control-to-output transfer function

involves the ratio , keeping D2 constant. Similarly, for the

regulation of the step-down output, the control-to-output

transfer function involves the ratio , keeping D1 constant .

For the design example considered, the plant transfer functions

are shown in equations (29) and (30).

(29)

(30)

where, the constant values have been given in APPENDIX B.

Fig. 12 shows the bode plots for the plant, compensator, and

the open-loop gains for both the outputs. In both the cases,

type-3 compensator has been used for regulation. The

compensator values have been shown in Fig. 11.

V. COMPARATIVE ANALYSIS

A. Topological comparison with buck and boost converter

This section shows a comparison of the IDOC with two

separate dedicated buck and boost converters. For the purpose

of comparison, it has been assumed that the buck and the

boost converters are connected to the same input supply as the

IDOC and generate output voltages at the same level as the

IDOC. TABLE 2 shows the comparison between the

converters. The buck converter is assumed to have the switch

Sbuck and diode Dbuck. The boost converter has a controllable

switch Sboost and diode Dboost.

TABLE 2: COMPARISON OF IDOC WITH TWO DEDICATED BUCK AND

BOOST CONVERTER TOPOLOGIES.

Dedicated converter

IDOC Buck Boost

No. of switches 2 2 3

Operation

(Switch

Voltage

and

Current)

Interval I Invalid State vsw_boost = 0

isw_boost = iL

vsw1 = vsw2 = 0

isw1 = iL1

isw1 = iL1 - iL2

Interval II

vsw_buck = 0 vd_buck = vin

isw_buck = iin

id_buck = 0

vsw_boost = vout

isw_boost = 0

vsw1 = 0

vsw2 = vo1

isw1 = iL2

isw2 = 0

Interval III

vsw_buck = vin

vd_buck = 0

isw_buck = 0 id_buck = iin

vsw_boost = vout

isw_boost = 0

vsw1 = vo1

vsw2 = 0

isw1 = 0

iD2 = iL2

Input current discontinuous continuous continuous

Output current continuous discontinuous

Continuous

(step-down)

Discontinuous

(step-up)

(a)

(b)

Fig. 12. Bode plots for plant, compensator, and open-loop gain for (a) Step-up output (Eqn. 29), and (b) step-down output (Eqn. 30).

Fig. 11. Control system schematic for a regulated IDOC.

Fig. 10. Generalized PWM control schematic for N-output IMOC obtained

using the control structures for individual converters.




B. Advantages of the IDOC topology

The advantages of the IDOC can be listed as follows:

The proposed IDOC has lesser Bill-of-Materials

compared to two dedicated buck and boost converters. In

general, for N output IMOC, we require (N + 1) switches

which includes N switches and only a single diode.

The input current of the IDOC is continuous. Thus,

compared to a conventional buck converter, both the

currents at the input as well as the output are continuous.

Thus, the input filter requirements for the converter are

reduced.

The IDOC has higher reliability due to its inherent fault-

tolerant capability. Unlike conventional buck converter

switches, switches S1 and S2 of IDOC can be turned „on‟

at the same time (Mode I operation). Thus this topology

can have synchronous switching with inherent shoot-

through protection.

Conventional buck converters cannot achieve very high or

very low gains, as these results in extremely high or low

duty cycle operation. Higher order converters are often

used for this purpose [31], with higher component count.

The IDOC has a wider step-down voltage range, which

ranges from zero to input voltage (vin), and which can be

achieved at acceptable values of duty ratios. This is

because, though the duty cycle D2 for step-down

conversion may be very low, the effective duty cycle of

the controlling switch S1 is the sum of D1 and D2, which

has acceptable operating values.

The two outputs of the IDOC can be regulated separately

using separate feedback control systems. The control

system designed for conventional buck as well as boost

converters are extendable to the IDOC.

Since two controlled switches control both step-up as well

as step-down outputs in an integrated architecture,

coordination control for power flow management in the

two ports are easier.

C. Efficiency analysis

The IMOC architecture utilizes the same set of switches to

realize different dc outputs and hence, the associated

conduction losses are higher than separate converters. The

slope of the efficiency curve for the IMOC is lesser than that

of separate converters, and with the number of stages the slope

of IMOC efficiency curve decreases. This is due to the fact

that the rate of rise of conduction losses is more than that of

separate converters. Hence, for a particular load specification,

beyond a certain number of output stages, from system

efficiency point of view, using separate dc-dc stages may

overshadow the advantages of IMOC.

VI. VERIFICATION

The behavior of the IDOC has been verified using a 120 W

laboratory prototype. The switching frequency of operation for

the converter is 100 kHz. The design specifications for

designing the prototype have been shown in TABLE 1. TABLE

3 lists the parameter values of the prototype. The components

used have been listed in TABLE 4 and the compensator

parameters have been shown in Fig. 11.

A. Steady State operation

The proposed converter generates step-up as well as step-

down voltages at its two output ports. Fig. 13 (a) shows that

for input voltage of 12 V, the converter generates step-up

output of 17.6 V dc and a step-down output of 5.9 V dc. The

duty cycles of the control signals D1 and D2 are 0.33 and 0.33,

respectively. The operating point for the step-down operation

is shown in the gain curve of Fig. 5. For duty cycles D1 = 0.33

and D2 = 0.2, the step-up and step-down output voltages are 18

V and 3.6 V, respectively. Fig. 13 (b) shows the inductor

current iL2, switch node voltages va and vb for the above

condition. The step-up and the step-down loads (Ro1 and Ro2)

used for the above cases are 5 Ω and 3 Ω, respectively. It has

to be noted that the relation for CCM operation derived in (22)

is satisfied, where, for Ro2 = 3 Ω, the maximum value of Ro1

required is 9 Ω, using the implemented prototype parameters.

Fig. 14 shows the behavior of the IDOC during pseudo-DCM.

The results show that for duty cycles D1 = 0.2 and D2 = 0.45,

the IDOC provides a step-up and a step-down outputs of 19.2

V and 5.27 V, respectively from a 12 V input due to the

presence of the loads Ro1 = 2 Ω and Ro2 = 15 Ω. The duty ratio

of pseudo-DCM is 0.3. The switch node voltage during

pseudo-DCM (va,pDCM) is 8 V, which validates (24).

TABLE 3. PARAMETERS OF THE IDOC Component Attributes

Inductor ( L1) 15 μH, DCR = 2.6 mΩ, 20 A

Inductor ( L2) 10 μH, DCR = 2.3 mΩ, 19 A

Capacitor (C1)

550 μF (electrolytic)

and 200 μF (ceramic)

ESR = 50 mΩ

Capacitor (C2)

220 μF (electrolytic)

and 400 μF (ceramic)

ESR = 50 mΩ

Fig. 14. Pseudo-DCM behavior of the IDOC. (slopes m1, m2, and m3

have been defined in Fig. 7).

(a) (b)

Fig. 13. Verification of steady state behavior of IDOC. (a) Input voltage vin

(Ch. 1), inductor current iL1 (Ch. 4), step-up vo1 (Ch. 3) and step-down vo2 (Ch.

2) voltages for D1 = D2 = 0.33. (b) Input voltage vin (Ch. 4), switch node voltages va (Ch. 3), vb (Ch. 1), and inductor current iL2 (Ch. 1) for D1 = 0.33

and D2 = 0.2.




B. Wide range of step-down gains

The proposed converter can be used to achieve a wide range

of step-down gains ranging from zero to the input voltage. Fig.

15(a) shows that for an input voltage of 12 V dc, a step-down

voltage of 1.2 V dc has been achieved at duty cycles D1 and

D2 equal to 0.335 and 0.065, respectively. Fig. 15(b) shows

that for an input voltage of 12 V dc, the output voltage at the

step-down port is 12 V dc, when D1 and D2 are 0.4 and 0.6

respectively. Thus, a wide range of gain has been achieved at

acceptable operating duty cycle values of the switches.

C. Verification of Gain curve

Fig. 16(a) shows the variation of the step-up gain with duty

cycle D2 (D1 is constant). The input voltage for the above case

is 12 V dc. Fig. 16(b) shows the variation of step-down gain

when the duty ratio D1 remains fixed and D2 varies.

D. Voltage Regulation

The behavior of the closed loop control system has been

verified with respect to the cross-regulation as well as the

voltage regulation behavior of the converter. Fig. 17 shows a

comparison between the simulation model for the plant

transfer functions and their corresponding frequency response

analyzer outputs for the laboratory prototype. For the

simulation model non-idealities have been considered as listed

in TABLE 3. However, to reduce the dependence of circuit

parameters on frequency, for measuring the step-down transfer

function, only ceramic capacitors of 400 μF have been used.

Fig. 18 (a) shows that when the step-down port of the IDOC

is subjected to a step-up load change of 5 A, the implemented

control system can precisely regulate both the outputs to their

predetermined values. The step-down output voltage settles to

its set-point in about 120 μs. There is a dip of about 175 mV

for this load step event. For these experiments, only voltage

mode control has been used.

Fig. 18 (b) shows that the step-down output (vo2) follows

the reference from 4 V to 6 V. The step-up output is regulated

to its predefined value of 18 V during this event. These results

validate the operation of the proposed control system proposed

in Fig. 11.

Fig. 19 shows the measured efficiencies of the experimental

prototype when the step-up load is fixed at 6 A, and the step-

down load varies from 1 A to 5 A. The PWM scheme

described in Fig. 9 has been used during experimentation.

Investigation shows that when Ro1 = 3 Ω and Ro2 = 3 Ω, the

Fig 19. Measured Efficiency of the experimental prototype when step-

up load is fixed and step-down load varies.

(a) (b)

Fig. 18. Verification of Controller behavior of IDOC. (a) Cross regulation:

For a 5 A step change in the step-down load, both the output voltages are

well regulated. (b) Reference Change: the step-up output voltage is regulated to its desired value even when there is a 2 V change of set-point in the step-

down output.

(a) (b)

Fig. 17. Comparison of plant control-to-output transfer functions for IDOC. (a) step-up, and (b) step-down plant transfer functions. Parameters as per

Table 3. (C2 is all ceramic). For the plant model Equations (29) and (30) have

been used.

TABLE 4. COMPONENT LIST Component Manufacturer

Switches Q1 – Q2

IRFS4410 (International

Rectifier)

D 60EPU04 (Vishay)

Gate Driver FOD 3120 (Fairchild

Semiconductor)

Inductor L1 SER2918H-153 (Coilcraft)

L2 VER2923-153 (Coilcraft)

(a) (b)

Fig. 16. Variation of (a) step-up voltage, (b) step-down voltage with D2 (D1 is constant).

(a) (b)

Fig. 15. IDOC operation with wide range of step-down gains. (a) Low step-

down output (Ch. 2) for D1 = 0.335 and D2 = 0.065 alongside the node voltage vb (Ch. 4). (b) High step-down output (Ch. 2) and input current iL1 (Ch. 4) for

D1 = 0.4 and D2 = 0.6. The input voltage (Ch.1) and step-up voltage (Ch. 3)

are also shown at these conditions.




estimated share of the different losses are: Diode (=85%),

switch S1 (=3.68%), switch S2 (=8.8%), inductor L1 (=2.42%),

and inductor L2 and others (=0.1%) Fig. 20 shows the

photograph of the laboratory prototype.

VII. TOPOLOGY EXTENSION

The IDOC topology shown in Fig. 2 (d) is based upon a

conventional boost converter, and hence, strictly speaking, the

step-up load cannot be zero. Fig. 21(a) shows the IDOC

topology where the function of the diode D is implemented

using the controllable switch SD. This modification would

allow zero loads at the step-up output, since there is a

possibility of energy transfer from step-up to the step-down

port. But the presence of three switches would require a

modification in the control system. Fig. 21(b) shows the gate

control signals GS1, GS2, and GSD and the corresponding

outputs of the three-switch-based IDOC, when D1 = 0.33 and

D2 = 0.33 with no load at the step-up port. The switch SD is

gated at all non shoot-through intervals; its switching is

complementary to Interval I. The output voltages at step-up

and step-down ports in this case are about 18 V dc and 6 V dc,

respectively. Hence, this circuit modification allows operation

with a wider range of step-up loads; even up to zero step-up

load conditions.

Fig. 22 shows the application of integrated multi-output

converter synthesis approach to higher order boost topologies.

In this case, the single switch-controlled Quadratic Boost

converter [31] has been modified to provide dual dc outputs.

The control scheme for the converter is same as that shown in

Fig. 9.

VIII. CONCLUSION

This paper proposed a multi-port dual output dc-dc

converter topology with simultaneous step-down as well as

step-up outputs. In contrast to a conventional buck converter,

the proposed converter has continuous input as well as the

step-down output current. Analysis and characterization of the

different modes of operation of the converter is done. It has

been established that the analog control system design

associated with conventional converters can be extended to the

IDOC. The merits of the converter with respect to shoot-

through protection, lesser Bill-of-Material and wider output

ranges have been discussed. The converter behavior has been

verified using an experimental prototype.

APPENDIX

A. System matrix and Input matrices of Eqn. (28):

,

rL1, rL2 = DCR of inductors L1 and L2.

rC1, rC2 = ESR of capacitors C1 and C2.

B. Plant Transfer function coefficients: (Eqn. 29 and 30)

α13 =-8.148E3, α 12 =9.324E8, α 11 =5.046E12, α 10 =1.520E17,

α 23 = -1.45E-11, α 22 =2.744E9, α 21 =1.307E13,α 10 =1.05E17,

β3 = 1.27E4, β 2 = 2.365E8, β 1 = 9.818E11, β 0 = 5.827E15.

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Olive Ray (S‟12) received the B.E.E. degree from

Jadavpur University, Kolkata, India, in 2009, the

M.Tech. degree from Indian Institute of Technology Kanpur, Kanpur, India, in 2011, both in electrical

engineering. Presently he is working towards the

Ph.D. degree in the Department of Electrical Engineering at Indian Institute of Technology

Kanpur.

His Research interests include hybrid power

converter topology modeling and control, dc-based

distribution systems, and digital control in power electronics.

Anil Prasad Josyula (S‟13) received the B.Tech.

degree in electrical engineering from K. L. University, Andhra Pradesh, India in 2011, the

M.Tech. degree in Electrical Engineering from

Indian Institute of Technology Kanpur, Kanpur, India in 2013. He is currently working as a

Development Manager in Tata Motors Engineering

Research Centre, Pune, India from 2013.

His research interests include analysis and control of

power electronic converters.

Santanu Mishra (S‟00-M‟04-SM‟12) received the

B.Tech. degree in electrical engineering from the

College of Engineering and Technology, Bhubaneswar, in 1998, the M.Tech. degree in

energy systems engineering from the Indian Institute

of Technology Madras, Chennai, India, in 2000, and the Ph.D. degree from the Department of Electrical

and Computer Engineering, University of Florida,

Gainesville, FL, in 2006.

He worked as a Senior and Staff Application

Engineer with the International Rectifier Corporation from 2004 to 2008. Currently, he is an Associate Professor at Indian Institute of Technology

Kanpur, Kanpur, India. His research interests include renewable power

conversion, high frequency power converters, and converter modeling and control.

Avinash Joshi received the Ph.D. degree in

electrical engineering from the University of Toronto, Toronto,ON, Canada, in 1979.

He is currently a Professor of electrical engineering

at the Indian Institute of Technology Kanpur, Kanpur, India. From 1970 to 1973, he was with the

General Electric Company of India Ltd., Calcutta,

India. His research interests include power electronics, circuits, digital electronics, and

microprocessor systems.

integrated dual-output converter

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