integrated microsystems lab. ee372 vlsi system designe. yoon ic fabrication/process lecture 5...

Integrated Microsystems Lab.

EE372 VLSI SYSTEM DESIGN E. Yoon

IC Fabrication/ProcessLECTURE 5

Problem(Design Specification)

Fab chipDesign

Patterning Process by which layers of integrated circuit are put together. Forms basis of our understanding of the design rules.Process Parameters: Capacitances, Resistances, VTO

if ignored, reduced performance.Geometric Constraints: Wire size, Spacing if ignored, circuit doesn’t work!(Design rules)



How do we transfer patterns to the surface of a silicon wafer? Separate pattern for each layer makes a Mask for each pattern. Use photo lithography to transfer to wafer.

1. Oxidation - expose Si wafer to O2 in furnace.

Si + O2 -> SiO2

SiSi

SiO2

Si3N4

44%



2. Lithography

SiO2

PR

UV light Mask

Si

Organic solvent (developer) Breaks down



3. Etching

exposed resist faster

etchantDissolves SiO2

but not resist



4. Ion Implantation (I/I)

5. Diffusion



NM

OS

Pro

cess

seq

uenc

e



P-w

ell P

+P

+N

+N

+

P-w

ell

N-s

ub

Bet

ter

PM

OS

N-w

ell P

+P

+N

+N

+

N-w

ell

Bet

ter

NM

OS

CM

OS

Pro

cess

es

P+

P+

N+

N+

N-w

ell

Bot

h N

-, P

-MO

S o

ptim

ized

Tw

in-T

ub

P-w

ell

N+

EP

I



N-W

ell C

MO

S P

roce

ss



MO

S P

RO

CE

SS

ING

TE

CH

NO

LOG

Y



Advanced CMOS Process Flow

p-type substrate

Pad oxideNitride

p-type substrate

Pad oxideNitridePhotoresist Photoresist

Grow Pad Oxide. Deposit CVD Nitride

RIE Shallow Trench in Silicon



p-type substrate

Shallow trench isolation

Grow Pad Oxide. Deposit Thick CVD Oxide

CMP Planarization

p-type substrate

Nitride

CVD oxide



Well Lithography and Implant (also channel doping)

Grow Gate Oxide and Deposit Polysilicon Film

p-type substrate

STI STIp-doping n-dopingSTI

n-well

p-type substrate


n-well

polysilicon

Gate oxide



Gate Lithography

Source-Drain Lithography and Implant

p-type substrate


n-well

Poly Poly

PR PR

p-type substrate

STIp-doping n-doping

STI

n-well

p+ poly

STI

n+ poly

n+ n+ p+ p+



Oxide Spacer Formation by CVD and RIE

Self-Aligned Silicide Process

p-type substrate


STI

n-well

STI n+ n+ p+ p+

n+ poly p+ poly

Oxide spacer

p-type substrate


STI

n-well

STI n+ n+ p+ p+

Oxide spacer

n+ poly p+ poly

Silicide Silicide



Why CMOS is superior to NMOS? (in VLSI)

1. Logic level 0/5V depending on ratio, poor noise margins2. Transmission time tI tf tI > tf

3. Transmission Gate pass both logic well only pass “0”, well pass “1” will have VT drop4. Power Dissipation zero in standby when output “0”, power dissipating5. Precharging Scheme Both n p are available only can charge to VDD- VT

for precharging bus to unless use boostrapping VDD / VSS

6. Power Supply May vary from 1.5~15V Fixed VIH/VIL, a fixed per- dependent on VDD

centage of VDD

7. Packing density less dense, 2N device Denser, N+1 device for N inputs for N input8. Load/Drive ratio 1:1 or 2:1 optimize ratio 4:19. Layout more regular irregular

CMOS NMOS

Comparison Table



Well Spacing and Separation Rules

Transistor Rules

NMOS PMOS



Well / substrate contacts

n-well

P+

P+

P+

integrated microsystems lab. ee372 vlsi system designe. yoon ic fabrication/process lecture 5...

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