integrating ddr3 signal integrity and timing analysis · integrating ddr3 signal integrity and...

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Signal Integrity Software, Inc.DDR3 Timing / Signal Integrity © SiSoft, 2008

Integrating DDR3 Signal Integrity

and Timing Analysis

Todd Westerhoff

Signal Integrity Software

6 Clock Tower Place, Suite 250

Maynard, MA 01754

[email protected]

January 17, 2008

2DDR3 Timing / Signal Integrity © SiSoft, 2008

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Toll Free Number: +1 (888) 8245783

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“Integrating DDR3 Timing

and Signal Integrity Analysis”

will begin at 12:30 EDT / 9:30 PDT

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Agenda

• High Speed Design

• Integrating Signal Integrity & Timing Analysis

• Limiting Factors for DDR2

• What’s New in DDR3

• DDR3 Signal Integrity

• DDR3 Timing Analysis

• New Quantum-SI Features for DDR3

• Quantum-SI DDR3 Design Kits


The High Speed Design Problem

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System Timing Closure

System Timing Analysis

DQ

DQS

Datasheet

Memory

DQ

DQS

Datasheet

Controller

Signal Integrity Analysis

Controller Interconnect Memory





DQ

DQS

6



Coupled Signal Integrity Analysis


SS S

DQ

DQS



Coupled Signal/Power Integrity Analysis


SS S

DQ

DQS

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System Timing Closure



DQ

DQS

Datasheet

Memory

DQ

DQS

Datasheet

Controller

Interface between SI and Timing analysis


VmeasVmeas

Vin_DC_Low

Vin_AC_Low

Vin_DC_High

Vin_AC_High

Vref

Normalizing Interconnect Delays

• Start times are based on driver timing specs

– Standard load and voltage levels

– IBIS Vref, Cref, Rref, Vmeas

• Stop times are based on receiver (setup/hold) timing specs

– Measured at defined voltage levels and slew rates

• Input slew rate at the receiver may affect device setup / hold requirements

VTT

Driver Standard Load

System Net being Analyzed

“Start” Time “Stop” Times

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Output Skew

Setup / Hold

Interconnect Skew

Integration Error

Crosstalk

Jitter

Integration Error

• Occurs when timing budget elements are based on different assumptions

– Calculated margins can be optimistic or pessimistic

• The error’s magnitude should

be compared to the data unit

interval and timing marginsBit Time

Timing Margin

Output Skew

Setup / Hold

Crosstalk

Jitter

Interconnect Skew


Integration Error - Example

Datasheet Timing Spec

Integration Error

175mV

@1.5V/ns

{

∆∆∆∆T = 117ps

} ∆∆∆∆tDS = 59ps

SI View (Spec)

Max Delay (Setup)

Min Delay (Hold)

1V/ns

Actual Analysis

Min, Max Delay1.5V/ns

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Quantum-SI Interconnect Delays

• Interconnect delays normalized

– Driver reference load

– Receiver setup & hold specs

– Receiver slew rate derating

• Every edge of every signal analyzed

• Normalized interconnect delays used for system timing analysis

• Automated process, driven from datasheet specifications

– Datasheet specifications added to simulation models using |SiSoft IBIS model extensions


DDR2 - Against the Wall at 800 MT/s

• Address / Command / Control

– Unbuffered signals drive multiple loads / slots with reflections at each branch point

– No timing margin left

• Data

– Simultaneous DQ switching increases controller noise

• Die-level power collapse

• Shared return paths

• Crosstalk

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What’s New with DDR3

(JEDEC JESD79-3)

• Faster, lower voltage

– 800 – 1600 MT/s

– SSTL 1.5V I/O

• New DIMM routing

• New On-Die Termination (ODT) values and configuration

• Dynamic device behavior

– Write leveling

– Read leveling

– Dynamic ODT

• New signal integrity requirement

– Time beyond VAC (tVAC)


Time Beyond VAC (TVAC)

• Signals must remain above / below VIH/IL(ac) for a specified time to ensure a valid transition

• This time period, TVAC, is slew rate dependent

• Signals must satisfy the TVAC

requirement even if setup time is negative (signal has not reached VIH/IL(ac) before clock transition)

• Quantum-SI uses |SiSoft TVAC to specify TVAC parameters

Ref: JESD79-3A, Page 162, Figure 101

Ref: JESD79-3A, Page 161, Table 71

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...

“Fly By” ADDCMD / CTRL / CLK

• End-terminated daisy-chain topology for ADDCMD/CTRL and CK/CK# signals

• Address valid windows at memory inputs are larger, but staggered in time

CLK, CLK_N

ADDRCMD / CTRL

Controller


CLK Signal at 1333 MT/s (667 MHz)

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Data Write @ 1333 MT/s

DQS

DQ

Memory setup/hold requirement

Controller DQS/DQ skew

Crosstalk


DDR3 Signal Integrity / Timing Analysis

CLKADDRL3DQ DQS

L2DQ DQS

L1DQ DQS

L0DQ DQS

CLK

ADDR

DQS

DQ

CLK

ADDR

DQS

DQ

CLK

ADDR

DQS

DQ

CLK

ADDR

DQS

DQ

WRITE

READSETUP / HOLD

OUTPUT TIMING

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CK / DQS Relationship

• Rising edge of CK has required relationship to both edges of DQS

• CK/DQS relationship must be maintained at each SDRAM (lane)

Ref: JESD79-3A, Page 63, Figure 38

Ref: JESD79-3A, Page 151, Table 67


CK/CK# to DQS (and therefore DQ)

• Must maintain CK/DQS relationship at each SDRAM

CLK, CLK#

ADDR

Controller

DQS, DQS#

DQ<0:N>

DQS, DQS#

DQ<0:N>

CLK

ADDR

DQS

DQ

CLK

ADDR

DQS

DQ

Matched length routing

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CK/CK# to DQS (and therefore DQ)

• Must adjust DQS timing for each lane to maintain CK/DQS relationship at SDRAM

• DQ shifts must follow DQS shifts

• Controllers can adjust DQ/DQS output timing to simplify PCB routing

CLK, CLK#

ADDR

Controller

DQS, DQS#

DQ<0:N>

DQS, DQS#

DQ<0:N>

CLK

ADDR

DQS

DQ

CLK

ADDR

DQS

DQ

Matched length routing


DQS / CLK Analysis

CLKADDRL3DQ DQS

L2DQ DQS

L1DQ DQS

L0DQ DQS

CLK

ADDR

DQS

DQ

CLK

ADDR

DQS

DQ

CLK

ADDR

DQS

DQ

CLK

ADDR

DQS

DQ

SETUP / HOLD

OUTPUT TIMING

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Adjusting DQ / DQS Timing

• Write Leveling

– Controllers adjust CLK/DQS/DQ skew on a per-lane basis

• Read Leveling

– Controllers compensate for DQ/DQS read skew on a per-lane basis

• Controllers may implement “training” algorithms to optimize CLK/DQS/DQ timing automatically

– DDR3 memory devices can report on alignment of received CK/DQS signals

– Corrects for PCB skew, device process and temperature


Quantum-SI DDR3 Support

• Controller timing models

– Programmable timing

– Dynamic timing

• Per-lane SI and timing analysis

• Automated interconnect delay extraction

• Automated analysis of TVAC requirement

– |SiSoft TVAC

# DQS Output timing with automatic

# write-leveling. This models controllers

# with auto-calibration (i.e. CLK to DQS

# output timing is set automatically by the

# controller following a training cycle)

#

MIN_TAP_INCREMENT = -(NUM_TAPS/2)

MAX_TAP_INCREMENT = NUM_TAPS/2)

TAP_GRANULARITY = DLL_STEP

TRAINED_DELAY_SKEW DDR_0_DQS0 MIN_TAP_INCREMENT MAX_TAP_INCREMENT TAP_GRANULARITY


DELAY_SKEW R DDR_0_CLK *TO DDR_0_DQS0 DQS0_SKEW_RMIN DQS0_SKEW_RMAX DQS0_SKEW_FMIN DQS0_SKEW_FMAX

DELAY_SKEW F DDR_0_CLK *TO DDR_0_DQS0 DQS0_SKEW_RMIN DQS0_SKEW_RMAX DQS0_SKEW_FMIN DQS0_SKEW_FMAX



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Programmable Timing Model

# DQS Output timing with user-set write-leveling:

# This models controllers without auto-calibration

# (i.e. CLK to DQS output timing is set by firmware)

#

# Offset can vary from 0 to 4 * CK_PERIOD.

# Granularity is one DLL_STEP.

#

# These settings are a starting point. Actual

# settings should be set based on specific

# populations being analyzed.

#

DQS0_WRITE_LEVEL = CK_PERIOD + (67 * DLL_STEP)









• Clock file parameters

– DQ_BIT_TIME

– CK_PERIOD

• User-programmable timing parameters:

– CLK_ADJUST

– DQ_PRELAUNCH

– ADDRCMD_PRELAUNCH

– CTRL_PRELAUNCH

– DLL_STEP

– DQS<0:17>_WRITE_LEVEL

– DQS<0:17>_SKEW<F,R>MIN

– DQS<0:17>_SKEW<F,R>MAX


Programmable Timing Model Flow

• Initial SI/Timing analysis establishes total available (setup + hold) margin

• Timing model is edited to balance timing margins

• Timing analysis is rerun

• Process is repeated as needed

Inspect report,

adjust timing

settings

SI / Timing

Analysis

Timing Analysis

OK

?

Adjust

controller

settings

Margins

Established

No

Yes

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Dynamic Timing Model

# DQS Output timing with automatic

# write-leveling. This models controllers

# with auto-calibration (i.e. CLK to DQS

# output timing is set automatically by the

# controller following a training cycle)

#

MIN_TAP_INCREMENT = -(NUM_TAPS/2)

MAX_TAP_INCREMENT = NUM_TAPS/2)

TAP_GRANULARITY = DLL_STEP







• Clock file parameters

– DQ_BIT_TIME

– CK_PERIOD

• Timing model establishes controller tap setting limits and granularity

– MIN_TAP_INCREMENT

– MAX_TAP_INCREMENT

– TAP_GRANULARITY


Dynamic Timing Model Flow

• Timing models define controller min/max tap settings and granularity

• SI analysis provides normalized interconnect delays for all transactions

• Timing analyzer determines optimum offset delays

• Timing analyzer determines best available tap settings

• Output report lists optimized tap setting and resulting timing margins

Compute

optimum

offsets

SI / Timing

Analysis

Compute

controller

settings

SI/Timing report

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Controller Tap Setting Report

Untrained

Setup

Margin

(ns)

Untrained

Hold

Margin

(ns)

Optimum

Setup

Margin

(ns)

Optimum

Hold

Margin

(ns)

Optimum

Shift (ns)

Trained

Setup

Margin

(ns)

Trained

Hold

Margin

(ns)

Number of

Taps

Trained Shift

(ns) Transfer Net Corner

2.43 -2.343 0.044 0.044 2.387 0.039 0.048 132 2.391 L0_dqs_x8_2R_0R_0R TTTE

2.249 -2.163 0.043 0.043 2.206 0.046 0.04 182 2.203 L1_dqs_x8_2R_0R_0R TTTE

2.008 -1.922 0.043 0.043 1.965 0.039 0.047 131 1.969 L2_dqs_x8_2R_0R_0R TTTE

1.769 -1.685 0.042 0.042 1.727 0.046 0.038 143 1.723 L3_dqs_x8_2R_0R_0R TTTE

1.631 -1.545 0.043 0.043 1.588 0.037 0.049 132 1.594 L4_dqs_x8_2R_0R_0R TTTE

1.822 -1.734 0.044 0.044 1.778 0.041 0.047 148 1.781 L5_dqs_x8_2R_0R_0R TTTE

2.062 -1.977 0.043 0.043 2.02 0.046 0.039 168 2.016 L6_dqs_x8_2R_0R_0R TTTE

2.24 -2.151 0.045 0.045 2.196 0.049 0.04 183 2.191 L7_dqs_x8_2R_0R_0R TTTE

1.621 -1.535 0.043 0.043 1.578 0.039 0.047 131 1.582 L8_dqs_x8_2R_0R_0R TTTE


SiSoft DDR3 Architectural Kits

• Architectural Design Kits

– Generic topologies, one pin per transfer net

– Technology-specific timing and SI models

• DDR3 Unbuffered Architecture Kit

– Controller to 2 SDRAM devices

– Spec timing/SI models

• DDR3 Registered Architecture Kit

– Controller to 2 SDRAM devices

– Spec timing/SI models

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SiSoft DDR3 Validation Kit

• 2 slot reference motherboard

• JEDEC Raw Card “A”

– Registered, x8, single rank

• Idealized routing; all traces perfectly matched

– “Best case” scenario

• Kit set up for 1066 MT/s, can be changed by editing master clock file

– Timing models automatically adapt for different clock speeds

• Generic timing & SI models for controller, memory & register

DDR3 Validation Kit


Summary

• SI interconnect delays must be normalized based on component timing specs

– Incorrect normalization causes integration error

• DDR3 isn’t just “DDR2-Plus”; high speed analysis requires SI & timing analysis methodologies

• Quantum-SI provides an automated flow for integrated DDR3 SI / Timing analysis

• Quantum-SI DDR3 Design Kits accelerate DDR3 high speed design and analysis

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For More Info

• Interconnect delay normalization / Integration error

– “Counting the Picoseconds: Integrating Timing, Signal and Power Integrity Analysis”, SiSoft / Denali

• DesignCon 2008, Session 6-WP1 / Wednesday, Feb 6, 2007

• Quantum-SI and Quantum-SI design kits

– www.sisoft.com

– SiSoft @ DesignCon 2008, Booth 106

• DDR3

– DDR3 Spec – JESD79-3A, Sept 2007, www.jedec.org

– JEDEC Oct 2007 DDR3 workshop materials on CD

• https://www.jedec.org/secure/jedecStore0.cfm

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