integration and fabrication techniques for 3d...

Integration and Fabrication Techniques for3D Micro- and Nanodevices

ANDREAS C. FISCHER

Doctoral ThesisStockholm, Sweden 2012

Front cover picture:Fabrication of 3D nanostructures by alternating steps of silicon deposition and localion implantation by focused ion beam (FIB) writing.

TRITA-EE 2013:001ISSN 1653-5146ISBN 978-91-7501-583-5

KTH Royal Institute of TechnologySchool of Electrical Engineering

Department of Micro and Nanosystems

Akademisk avhandling sommed tillstånd av Kungliga Tekniska högskolan framläggestill offentlig granskning för avläggande av teknologie doktorsexamen i elektriskmätteknik fredagen den 18 januari 2013 klockan 10.00 i F3, Lindstedtsvägen 26,Stockholm.

Thesis for the degree of Doctor of Philosophy at KTH Royal Institute of Technology,Stockholm, Sweden.

© Andreas C. Fischer, December 2012

Tryck: Universitetsservice US AB, Stockholm, 2012

iii

Abstract

The development of micro and nano-electromechanical systems (MEMSand NEMS) with entirely new or improved functionalities is typically basedon novel or improved designs, materials and fabrication methods. However,today’s micro- and nano-fabrication is restrained by manufacturing paradigmsthat have been established by the integrated circuit (IC) industry over thepast few decades. The exclusive use of IC manufacturing technologies leadsto limited material choices, limited design flexibility and consequently tosub-optimal MEMS and NEMS devices. The work presented in this thesisbreaks new ground with a multitude of novel approaches for the integrationof non-standard materials that enable the fabrication of 3D micro and nano-electromechanical systems. The objective of this thesis is to highlight methodsthat make use of non-standard materials with superior characteristics ormethods that use standard materials and fabrication techniques in a novelcontext. The overall goal is to propose suitable and cost-efficient fabricationand integration methods, which can easily be made available to the industry.

The first part of the thesis deals with the integration of bulk wire mate-rials. A novel approach for the integration of at least partly ferromagneticbulk wire materials has been implemented for the fabrication of high aspectratio through silicon vias. Standard wire bonding technology, a very matureback-end technology, has been adapted for yet another through silicon viafabrication method and applications including liquid and vacuum packagingas well as microactuators based on shape memory alloy wires. As this thesisreveals, wire bonding, as a versatile and highly efficient technology, can beutilized for applications far beyond traditional interconnections in electronicspackaging.

The second part presents two approaches for the 3D heterogeneousintegration based on layer transfer. Highly efficient monocrystalline sili-con/germanium is integrated on wafer-level for the fabrication of uncooledthermal image sensors and monolayer-graphene is integrated on chip-level forthe use in diaphragm-based pressure sensors.

The last part introduces a novel additive fabrication method for layer-by-layer printing of 3D silicon micro- and nano-structures. This method combinesexisting technologies, including focused ion beam implantation and chemicalvapor deposition of silicon, in order to establish a high-resolution fabricationprocess that is related to popular 3D printing techniques.

Keywords: Microelectromechanical systems, MEMS, Nanoelectromechan-ical systems, NEMS, silicon, wafer-level, chip-level, through silicon via,TSV, packaging, 3D packaging, vacuum packaging, liquid encapsulation,integration, heterogeneous integration, wafer bonding, microactuators, shapememory alloy, SMA, wire bonding, magnetic assembly, self-assembly, 3D, 3Dprinting, focused ion beam, FIB.

Andreas C. Fischer, andreas. fischer@ ee. kth. seDepartment of Micro and Nanosystems, School of Electrical EngineeringKTH Royal Institute of Technology, SE-100 44 Stockholm, Sweden

Contents

Contents v

List of Publications vii

Symbols xi

Abbreviations xiii

Objectives and Overview xvStructure of the thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv

1 Introduction to 3D Integration and 3D Fabrication 1

2 3D Heterogenous Integration of Bulk Wire Materials 52.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1.1 Introduction to wire bonding technology . . . . . . . . . . . 72.1.2 Introduction to through silicon via technology . . . . . . . . . 15

2.2 Integration of bulk wire materials based on magnetic assembly . . . 172.2.1 Through silicon vias with very high aspect ratios . . . . . . . 182.2.2 Through silicon vias for high-frequency applications . . . . . 24

2.3 Integration of bulk wire materials based on wire bonding technology 262.3.1 Wire-bonded through silicon vias . . . . . . . . . . . . . . . . 262.3.2 Room-temperature wafer-level integration of liquids . . . . . 312.3.3 Room-temperature wafer-level vacuum sealing . . . . . . . . 352.3.4 Wafer-level integration of Shape Memory Alloy wires . . . . . 38

2.4 Discussion and outlook . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3 3D Heterogeneous Integration Based on Layer Transfer 433.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.2 Via-last integration of monocrystalline SiGe for infrared bolometers 45

3.2.1 Wafer-level integration of monocrystalline SiGe . . . . . . . . 463.2.2 Uncooled infrared bolometer design . . . . . . . . . . . . . . 473.2.3 Bolometer via structures . . . . . . . . . . . . . . . . . . . . . 48

v

vi CONTENTS

3.2.4 Bolometer leg structures . . . . . . . . . . . . . . . . . . . . . 513.3 Via-first integration of graphene monolayers for pressure sensors . . 53

3.3.1 Chip-level integration of graphene monolayers . . . . . . . . . 543.3.2 Graphene-based pressure sensor . . . . . . . . . . . . . . . . . 55

3.4 Discussion and outlook . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4 3D Free-Form Patterning of Silicon 574.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574.2 3D free-form patterning of silicon by ion implantation, silicon

deposition, and selective silicon etching . . . . . . . . . . . . . . . . . 584.3 Discussion and outlook . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5 Conclusions 63

Summary of Appended Papers 65

Acknowledgments 69

References 71

Paper Reprints 91

List of Publications

The thesis is based on the following international reviewed journalpapers:

1. ”Wire-bonded through-silicon vias with low capacitive substrate coupling”,A.C. Fischer, M. Grange, N. Roxhed, R. Weerasekera, D. Pamunuwa, G.Stemme and F. Niklaus, IOP Journal of Micromechanics and Microengineer-ing, vol. 21, no. 8, pp. 085035, August 2011

2. ”Hermetic integration of liquids using high-speed stud bump bonding forcavity sealing at the wafer level”, M. Antelius, A.C. Fischer, F. Niklaus,G. Stemme and N. Roxhed, IOP Journal of Micromechanics and Microengi-neering, vol. 22, no. 4, pp. 045021, April 2012

3. ”Wire-bonder-assisted integration of non-bondable SMA wires into MEMSsubstrates”, A.C. Fischer, H. Gradin, S. Schröder, S. Braun, G. Stemme,W. van der Wijngaart and F. Niklaus, IOP Journal of Micromechanics andMicroengineering, vol. 22, no. 5, pp. 055025, May 2012

4. ”Very high aspect ratio through silicon vias (TSVs) fabricated using au-tomated magnetic assembly of nickel wires", A.C. Fischer, S.J. Bleiker,T. Haraldsson, N. Roxhed, G. Stemme and F. Niklaus, IOP Journal ofMicromechanics and Microengineering, vol. 22, no. 10, pp. 105001, October2012

5. ”3D free-form patterning of silicon by ion implantation, silicon deposition,and selective silicon etching”, A.C. Fischer, L.M. Belova, Y.G.M. Rikers,B.G. Malm, H.H. Radamson, M. Kolahdouz, K.B. Gylfason, G. Stemme andF. Niklaus, Wiley Advanced Functional Materials, vol. 22, no. 19, pp. 4004-4008, October 2012

6. ”Process considerations for layer-by-layer 3D patterning of silicon, using ionimplantation, silicon deposition, and selective silicon etching”, K.B. Gylfason,A.C. Fischer, B.G. Malm, H.H. Radamson, L.M. Belova, G. Stemme andF. Niklaus, AVS Journal of Vacuum Science and Technology, vol. 30, no. 6,pp. 06FF051-06FF05-4, October 2012

vii

viii LIST OF PUBLICATIONS

7. ”Pressure sensors based on suspended graphene membranes”, A.D. Smith, S.Vaziri, F. Niklaus, A.C. Fischer, M. Sterner, A. Delin, M. Östling and M.C.Lemme, Elsevier Solid-State Electronics, accepted for publication

8. ”High aspect ratio through silicon vias (TSVs) for high-frequency applicationsfabricated by automated magnetic assembly of gold-coated nickel wires”, S.J.Bleiker, A.C. Fischer, N. Somjit, T. Haraldsson, N. Roxhed, G. Stemmeand F. Niklaus, submitted to IEEE Transactions on Electron Devices

9. ”Heterogeneous 3D integration of 17 µm pitch Si/SiGe quantum well bolome-ter arrays for infrared imaging systems”, K.F. Forsberg, N. Roxhed, A.C.Fischer, B. Samel, P. Ericsson, G. Stemme and F. Niklaus, submitted toIOP Journal of Micromechanics and Microengineering

10. ”Very large scale heterogeneous integration (VLSHI) and wafer-level vacuumpackaging for infrared bolometer focal plane arrays”, K.F. Forsberg, N.Roxhed, A.C. Fischer, B. Samel, P. Ericsson, N. Høivik, A. Lapadatu,M. Bring, G. Kittilsland, G. Stemme and F. Niklaus, submitted to ElsevierJournal of Infrared Physics and Technology

11. ”Wafer-level vacuum sealing by coining of wire bonded gold bumps”, M.Antelius, A.C. Fischer, N. Roxhed, G. Stemme and F. Niklaus, manuscript

The contribution of Andreas C. Fischer to the different publications:

1. major part of design, fabrication and experiments, part of writing

2. part of design, fabrication, experiments and writing

3. major part of design and writing, part of fabrication and experiments

4. major part of design, fabrication, experiments and writing



7. part of experiments and writing

8. major part of design, part of fabrication, experiments and writing




ix

The thesis is also based on the following review paper:

12. ”Wire bonding creates new opportunities for microsystem integration”, A.C.Fischer, J.G Korvink, N. Roxhed, G. Stemme, U. Wallrabe and F. Niklaus,IEEE Proceedings of the IEEE, submitted June 2012

In addition, the author has contributed to the following internationalreviewed journal papers:

13. ”Graphene membrane-based nanoelectromechanical pressure sensors”, A.D.Smith, F. Niklaus, S. Vaziri, A.C. Fischer, M. Sterner, A. Delin, M. Östlingand M.C. Lemme, manuscript

14. ”Low stress packaging of inertial sensors using wire bonding”, S. Schröder,S. Haasl, A.C. Fischer, K. Persson, E. Westby, G. Stemme and F. Niklaus,manuscript

The work has also been presented at the following international reviewedconferences:

15. ”Heterogeneous integration for optical MEMS”, A.C. Fischer, F. Forsberg,M. Lapisa, N. Roxhed, G. Stemme, F. Zimmer and F. Niklaus, Proceedingsof the 23rd Annual Meeting of the IEEE Photonics Society, pp. 487-488,November 2010

16. ”Selective electroless nickel plating on oxygen-plasma-activated gold seed-layers for the fabrication of low contact resistance vias and microstructures”,A.C. Fischer, M. Lapisa, N. Roxhed, G. Stemme and F. Niklaus, Proceed-ings IEEE International Conference on Micro Electro Mechanical Systems(MEMS), pp. 472-475, January 2010

17. ”Low-cost through silicon vias (TSVs) with wire-bonded metal cores andlow capacitive substrate-coupling”, A.C. Fischer, N. Roxhed, G. Stemmeand F. Niklaus, Proceedings IEEE International Conference on Micro ElectroMechanical Systems (MEMS), pp. 480-483, January 2010

18. ”Low-cost uncooled microbolometers for thermal imaging”, N. Roxhed, F.Niklaus, A.C. Fischer, F. Forsberg, L. Höglund, P. Ericsson, B. Samel, S.Wissmar, A. Elfving, T.I. Simonsen, K. Wang and N. Hoivik, ProceedingsSPIE Optical Sensing and Detection, vol. 7726, pp. 772611-1-772611-10,May 2010

19. ”Fabrication of high aspect ratio through silicon vias (TSVs) by magneticassembly of nickel wires”, A.C. Fischer, N. Roxhed, T. Haraldsson,N. Heinig, G. Stemme and F. Niklaus, Proceedings IEEE InternationalConference on Micro Electro Mechanical Systems (MEMS), pp. 37-40,January 2011

x LIST OF PUBLICATIONS

20. ”Wafer-level integration of NiTi shape memory alloy wires for the fabricationof microactuators using standard wire bonding technology”, A.C. Fischer,H. Gradin, S. Braun, S. Schröder, G. Stemme, and F. Niklaus, Proceed-ings IEEE International Conference on Micro Electro Mechanical Systems(MEMS), pp. 348-351, January 2011

21. ”Hermetic integration of liquids in MEMS by room temperature, high-speedplugging of liquid-filled cavities at wafer level”, M. Antelius, A.C. Fischer,N. Roxhed, G. Stemme and F. Niklaus, Proceedings IEEE InternationalConference on Micro Electro Mechanical Systems (MEMS), pp. 356-359,January 2011

22. ”Toward 17 um pitch heterogeneously integrated Si/SiGe quantum wellbolometer focal plane arrays”, P. Ericsson, A.C. Fischer, F. Forsberg, N.Roxhed, B. Samel, S. Savage, G. Stemme, S. Wissmar, O. Öberg and F.Niklaus, Proceedings SPIE Infrared Technology and Applications, vol. 8012,pp. 801216-1-801216-9, May 2011

23. ”Room-temperature wafer-level vacuum sealing by compression of high-speedwire bonded gold bumps” M. Antelius, A.C. Fischer, N. Roxhed, G. Stemmeand F. Niklaus, Proceedings IEEE International Conference on Solid-StateSensors, Actuators and Microsystems (Transducers), pp. 1360-1363, June2011

24. ”High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires”, A.C. Fischer, S.J. Bleiker, N. Somjit, N. Roxhed,T. Haraldsson, G. Stemme and F. Niklaus, Proceedings IEEE ElectronicComponents and Technology Conference (ECTC), pp. 541-547, May 2012

25. ”Wafer-level heterogeneous 3D integration for MEMS and NEMS”, F. Niklaus,M. Lapisa, S.J. Bleiker, V. Dubois, N. Roxhed, A.C. Fischer, F. Forsberg,G. Stemme, D. Grogg and M. Despont, Proceedings IEEE InternationalWorkshop on Low Temperature Bonding for 3D Integration (LTB-3D), pp.247-252, May 2012

26. ”3D patterning of Si micro and nano structures by focused ion beamimplantation, Si deposition and selective Si etching”, A.C. Fischer, K.B.Gylfason, L.M. Belova, G.B. Malm, M. Kolahdouz, Y.G. Rikers, G. Stemme,and F. Niklaus, Proceedings International Conference on Electron, Ion,Photon Beam Technology (EIPBN), May 2012

27. ”Layer-by-layer 3D printing of Si micro- and nanostructures by Si deposition,ion implantation and selective Si etching”, A.C. Fischer, K.B. Gylfason,L.M. Belova, G.B. Malm, H. Radamson, M. Kolahdouz, Y.G. Rikers, G.Stemme, and F. Niklaus, Proceedings IEEE International Conference onNanotechnology (NANO), pp. 1-4, August 2012

Symbols

Symbol Physical quantity Unit

αE Coefficient of thermal expansion (CTE) ppm/KαR Temperature coefficient of electrical resistance (TCR) %/KB Magnetic field TC Capacitance Fd Distance mδ Skin depth mE Young’s modulus Paκ Relative permittivity -F Force Nf Frequency HzHV Vickers hardness PaI Current AL Inductance Hµ Magnetic permeability H/mρ Electrical resistivity Ω mR Resistance Ω

S21, S12 Insertion loss dBS11, S22 Return loss dB

T Temperature /CU Voltage VΩ Angular velocity /sω Angular frequency 1/sp Pressure bar

xi

Abbreviations

AC Alternating currentAFM Atomic force microscopyALD Atomic layer depositionBCB BenzocyclobuteneCAD Computer aided designCNT Carbon nano tubeCMOS Complementary metal-oxide semiconductorCPW Coplanar waveguideCSP Chip-scale packageCTE Coefficient of thermal expansionCVD Chemical vapor depositionDC Direct currentDRIE Deep reactive ion etchEFO Electrical flame-offFAB Free air ballFIB Focused ion beamFPA Focal plane arrayHB LED High-brightness light emitting diodeIC Integrated circuitI/O Input/OutputIR InfraredLED Light emitting diodeLIGA ”Lithographie, Galvanoformung, Abformung”

(Lithography, Electroplating, Molding)MM ”More Moore”MtM ”More than Moore”MPU Microprocessor unitMEMS Microelectromechanical systemNEMS Nanoelectromechanical systemRF Radio frequencyRGA Residual gas analysisRIE Reactive ion etchROIC Read-out integrated circuit

xiii

xiv ABBREVIATIONS

SOLT Short-open-load-thruSoB System on boardSoC System on chipSiP System in packageSEM Scanning electron microscopySMA Shape memory alloySMD Surface-mount deviceSOI Silicon on InsulatorTEM Transmission electron microscopyTGV Through glass viaTSV Through silicon viaTC Thermocompression (wire bonding)TS Thermosonic (wire bonding)US Ultrasonic (wire bonding)VCSEL Vertical-cavity surface-emitting laserVNA Vector network analyzer

Objectives and Overview

This thesis breaks new ground with a multitude of novel approaches for theintegration of non-standard materials that enable the fabrication of 3D micro andnano-electromechanical systems. The objective of this thesis is to highlight methodsthat make either use of non-standard materials with superior characteristics or usestandard materials and fabrication techniques in a novel context. The overall goalis to propose suitable and cost-efficient fabrication and integration methods thatcan be easily made available to the industry.

Structure of the thesis

Chapter 1 gives a brief introduction to the recent trends in semiconductormanufacturing and packaging methods that are the foundation of this thesis. Inthe first part of Chapter 2, a detailed introduction to bulk wire materials andwire bonding technology is given. The second part then deals with the integrationof bulk wire materials for a variety of applications including through silicon viafabrication, liquid and vacuum packaging and microactuators. The integration ofbulk wire materials is based on a novel assembly process and existing wire bondingtechnology, which has been adapted here. Chapter 3 presents two approachesfor the 3D heterogeneous integration based on layer transfer of monocrystallinesilicon/germanium for thermal image sensors and monolayers of graphene forpressure sensors. Chapter 4 introduces a novel additive fabrication method forlayer-by-layer printing of 3D silicon micro- and nanostructures. The concludingchapter summarizes the achievements of the work presented in this thesis.

xv

Chapter 1

Introduction to 3D Integration and3D Fabrication

Micro and nano-electromechanical system (MEMS and NEMS) technology hasgained an increasing impact not only on industry but also on our society. The rapidgrowth of this technology within the past few years was driven by a broad spectrumof application fields ranging from consumer, mobile and automotive applications tomedicine, pharmaceutics and bioengineering. A multitude of products with entirelynovel or improved functionalities that are enabled by MEMS and NEMS devices,including digital light processors, accelerometers and gyroscopes, pressure sensors,microphones, magnetometers, inkjet printheads, oscillators, filters and many more,have thereby emerged.

Most micro- and nano-fabrication methods have been developed by the in-tegrated circuit (IC) industry, which for the past five decades has followedMoore’s law. This law, named after Intel co-founder Gordon E. Moore, isbased on an observation made during the years 1959 and 1965. During thistime, Moore discovered that the number of transistors of integrated circuits haddoubled approximately every two years. In 1965, he predicted that the numberof components that could be incorporated per integrated circuit would increaseexponentially over time and that this trend will continue at least for ten moreyears [1]. In fact, his ingenious prediction proved valid even until today. Thecontinuous improvement of electronics in terms of performance has a major impacton global productivity and is directly coupled to the continuous scaling process thatis paced by Moore’s law.

As a result of this continuous scaling process, todays IC industry is strivingto establish technology nodes with ever decreasing feature sizes. As illustrated inFigure 1.1, the physical gate length of a single MPU transistor, i.e. the technologynodes, has steadily decreased from 10 µm in 1971 to the present deep sub-micronregime of 22 nm [2]. However, scaling is about to reach the fundamental limitsof physics with silicon as the base material, and the economic limits of cost for

1

2 CHAPTER 1. INTRODUCTION

Te

ch

no

log

y N

od

e

10 µm(1971)

130 nm(2000)

14 nm(2014)

22 nm(2012)

4 nm(2022)

32 nm(2010)

Scalin

g -

“M

ore

Moore

” (M

M)

Functional Diversification

“More than Moore” (MtM)

Electronics MEMS/NEMS

Analog

Power &Energy

RF

Passives Actuators

Sensors

Digital

Beyond CMOS

Figure 1.1: Ongoing trends in semiconductor fabrication and integration. On the one hand,industry is further scaling down feature sizes and is thereby about to approach ultimate physicallimits in the deep sub-micron regime (”More Moore”). On the other hand, a functionaldiversification of semiconductor-based devices takes place (’More than Moore”).

establishing next generation manufacturing infrastructure. This continued scalingapproach is known as ”More Moore” (MM).

A second parallel trend that is currently strongly emerging is characterized by afunctional diversification of semiconductor-based devices. As shown in Figure 1.1,these functionalities are mostly non-digital and are based on different fabricationtechnologies compared to that of traditional IC manufacturing. The novelty isthat these functionalities migrate from the system on board (SoB) level into thepackage (SiP) or onto the chip (SoC). This migration is mainly enabled by novelheterogenous integration and packaging techniques and is driven by the needfor increased performance in terms of signal speed, bandwidth, reduced powerconsumption, smaller form factors, and ultimately, lower cost of the overall system.This trend has been entitled ”More than Moore” (MtM) as it does not contributeto the scaling of pure digital systems that is described by Moore’s law.

The developments of ”More than Moore” and ”More Moore” are not competingideologies, rather they can be considered as complimentary technology trends.”More Moore” drives the development of digital functions in terms of performancewhile ”More than Moore” stands for a diversification of non-digital functions [3].

With respect to the bulk silicon wafer thickness, the implementation of digitalfunctions, i.e. traditional CMOS manufacturing, can essentially be consideredas a 2D process technology due to the fact that only a fraction of the bulk

3

silicon thickness is used, as seen in Figure 1.2 a. In contrast, non-digitalfunctions, e.g. MEMS, MOEMS, RF, etc., typically consist of considerably larger3D structures. These structures are implemented by substractive fabricationmethods (bulk micromachining) and additive methods (surface micromachining andmicroforming), as indicated in Figure 1.2 b. With substractive methods (e.g. wetand dry etching) structures are formed by removing material from the silicon bulkmaterial. With additive methods, on the other hand, material is built up on thesurface of the substrate. Additive methods include deposition techniques such asevaporation, sputtering, plating and chemical vapor deposition [4].

a) Digital Functions b) Non-digital Functions

µm

- m

m

Substrate

Bulk Micromachining

Surface Micromachining

Microforming

nm

- µ

m

Substrate

Figure 1.2: a) The active components of IC’s (i.e. digital functions) only take a fraction ofthe actual bulk silicon material. b) Considerably larger 3D structures for the realization of non-digital functions are manufactured by substractive (bulk micromachining) and additive (surfacemicromachining and microforming) fabrication methods.

The key enablers for the realization of diverse systems that include both digitaland non-digital functions are heterogeneous integration techniques (introduced insection 3.1) and electronics packaging. In electronics packaging, a great varietyof integration approaches for the realization of versatile systems co-exist today.Figure 1.3 illustrates a general classification of the most common system integrationapproaches for two or more dies. The functional diversification is represented by twodies, Die 1 andDie 2, that are fabricated separately with different base technologies,e.g. CMOS and MEMS process technology. Individual base technologies aretypically characterized by short development times, low fabrication costs, highyields and are well-established. Separate manufacturing of dies with optimizedfabrication technologies and the integration to a SiP in a final packaging step offersthe highest versatility and typically lowest costs of the system.

During the past decades, the hybrid integration of two or more different dies to asystem has been dominated by 2D-approaches, such as the system-on-board (SoB)integration where each die is packaged individually and then merged on the printedcircuit board (PCB) (Figure 1.3 a). This led consequently to the development of 2D

4 CHAPTER 1. INTRODUCTION

system-in-packages (2D-SiP) where, as shown in Figure 1.3 b, the dies are placedside-by-side in a common package and then interconnected on package level by flipchip and/or wire bonding. This approach reduces the signal path length betweenthe dies significantly and occupies less area on the PCB real estate.

2D SoB2D System on Board

Printed Circuit Board

2D SiP2D System in Package


Die 1 Die 2

2.5D SiP2.5D System in Package


Die 1 Die 2

SiP Substrate

Interposer

3D SiP3D System in Package

stacked dies, flip chip & wire bonds stacked dies with TSVs, flip chip


Die 1Die 2

SiP Substrate

Die 2

Die 1


SiP Substrate

a) b)

c) d)

Solder

Bump

Micro

Bump

Flip Chip

BumpDie 1 Die 2

Leadframe Leadframe

Wire

Bond

SiP Substrate

TSV

Figure 1.3: Overview of the most common packaging approaches for the integration of twoor more dies. The illustrations are not to scale, 2.5D and 3D SiPs are considerably smaller ascompared to 2D SoBs and SiPs.

More recently, 2.5D and 3D-SiP solutions, which are based on vertical (3D) chipstacking, have become a general trend in many integration approaches. Not only do3D-SiPs decrease costs by further reducing the volume and weight of the package,they also improve system performance through enhanced bandwidth and signaltransmission speed as well as lower power consumption, which is of importancefor various demanding applications [5, 6]. These benefits are primarily due toshorter signal path lengths and lower capacitive, resistive and inductive parasiticcomponents in the interconnections [7].

The main difference between the traditional 2D-SiP and a 2.5D-SiP is that aninterposer (e.g. silicon or glass) is placed between the SiP substrate and the dies.As indicated in Figure 1.3 c, the interposer has vertical interconnects connecting themetallization layers on its front- and back-side. The interposer serves the purposeof a signal redistribution substrate that enables the integration of very thin dies andthe implementation of significantly smaller interconnects (microbumps) comparedto 2D-SiPs and SoBs. 3D-SiPs, as indicated in Figure 1.3 d are based on stacked diesand enables the most compact packages and shortest possible signal path lengths.”True” 3D-SiPs require vertical interconnects through selected dies in the stack inorder to connect their functional layers. These vertical interconnects are typicallyreferred to as through silicon vias (TSVs). Both, TSV and wire bonding technologyare introduced in the following chapter.

Chapter 2

3D Heterogenous Integration ofBulk Wire Materials

This chapter introduces novel methods for the integration of bulk wire materials atchip- and wafer-level for a variety of applications.

The first section of this chapter, gives an introduction to bulk wire materialsand the most commonly used interconnection technique in electronics packaging,wire bonding technology. Also, in the context of 3D packaging, a brief overviewabout state-of-the-art fabrication technology of through silicon vias (TSVs) is given.The main part is dedicated to novel microwire integration methods that havebeen developed within this work. First, a novel method for the integration offerromagnetic bulk wire materials based on magnetic assembly is presented. Finally,approaches based on existing wire bonding technique that have been adapted foruse in through silicon via (TSV) fabrication, liquid and vacuum sealing applicationsand microactuators, are presented.

2.1 Introduction

A ”wire” is defined as a metal drawn out into the form of a thin flexible threador rod. The fabrication of a wire, the wire drawing process, is an ancient methodthat originated in the first century AD. Wire drawing follows a straightforwardconcept that did not change significantly over the centuries. In order to form awire with a desired diameter, a pre-formed metal rod is pulled through a formingtool, a drawing die, which consists of a metal plate with a tapered hole. By pullingthe wire through the tapered hole its diameter decreases and its length increaseswhile maintaining a constant volume. In order to reach the desired wire diameter,the wire is typically drawn through several successively smaller holes. Today, amultitude of different metal and metal alloy wire types are manufactured in highvolumes with diameters ranging from several micrometers to several millimeters fora wide range of applications.

5

6 CHAPTER 2. 3D INTEGRATION OF BULK WIRE MATERIALS

Figure 2.1: Packaging levels in electronics, from [8]

As shown in Figure 2.1, wires traditionally possess a firm place in electronicspackaging as chip-to-package interconnection at level 1 and 1.5 (i.e. wire bonds,discussed in section 2.1.1) as well as macroscopic wiring at level 2 and 3 [8].However, recent developments by a number of research groups are inducing aparadigm shift. Wires are being utilized more and more at chip-level (level 0)as an actual functional material rather as a simple interconnection (see Paper 12).The reason for this trend is a combination of superior characteristics of wire bulkmaterials in comparison to thick films and an existing infrastructure, i.e. wirebonding equipment (discussed in section 2.1.1), that allows a precise 3D integrationof microwires at high speed and low cost.

As illustrated in Figure 2.2, there exists a broad spectrum of physical andchemical methods for the deposition of metallic layers as thin as an atomicmonolayer or up to thicknesses of several tens of micrometers. However, a good 3Dprocessabilty is typically not given for most thick film deposition technologies. Themanufacturabilty of solid 3D structures with high aspect ratios plays a crucial rolein MEMS and 3D packaging applications. Therefore, enormous development effortsare currently ongoing in order to adapt plating and CVD technologies to the needsof the industry. As indicated in Figure 2.2, the integration of bulk wire materialshas the potential to serve as an alternative to conventional thick film technology,especially regarding plating processes. As wire diameters decrease and more bulkwire materials are available, novel methods for the integration of wires have to bedeveloped in order to make use of this promising material class. This chapter dealswith such novel methods for the integration of bulk wire materials by the adaptionof established technologies as well as by entirely novel approaches.

2.1. INTRODUCTION 7

10-91 nm

Typical Material Thickness

3D

pro

ce

ssa

bili

ty

po

or

go

od

10-61 µm

10-31 mm

10-101 Å

10-8 10-7 10-5 10-4

Atomic LayerDeposition (ALD)

Chemical VapourDeposition (CVD)

Sputtering

Evaporation

Plating

µ-wires

Chemical Deposition Physical Deposition

Figure 2.2: Overview of standard metal deposition techniques used in electronics and MEMSmanufacturing. Typical material thicknesses with respect to the 3D manufacturability of theprocess are compared in this diagram.

2.1.1 Introduction to wire bonding technology1

The main application of wire bonding technology is to create electrical intercon-nections between integrated circuit (IC) chips and their packages (see Figure 1.3).The interconnections are formed by a thin metal wire, which is mechanically andelectrically connected to the chip and to the package by using a wire bonding tool.The requirements of the integrated circuit industry have pushed the developmentof the wire bonding processes towards higher speeds (number of bonds per second),improved reliability, increased density (in terms of bond pitch) and hence finer wires,and nonplanar topographies (e.g. multilayer stacks of thinned chips). Becausewire bonding forms part of the back-end of semiconductor chip production, it isrequired to achieve exceptionally high reliability and yield in order to obtain thelowest possible packaging costs. Although alternative processes exist, such as flip-chip assembly and tape automated bonding [8], wire bonding continues to be acrucial process in semiconductor packaging. This is partly due to the advantages ofcompliant wires under thermal and bending stress conditions, which results in highreliabilities of the packaged interconnects. It is estimated that more than 4 · 1012

wire bonds are produced annually [9].

1Excerpt from paper 12.


Wire Bonding Mechanisms

In wire bonding, the attachment of a bond wire to a bond pad is realized by awelding process. The energy input for the welding process is a combination offorce, temperature and/or ultrasonics. For standard wire bonding, three weldingmethods exist which are based and named after the type of energy input:

• Thermocompression (TC) bonding, first introduced in 1957 [10], uses me-chanical force and a relatively high temperature on the order of 300 C. TCis typically used for gold wire to gold pad wedge-wedge bonding. It is verysensitive to surface contaminants, requires high temperature and long processtimes and therefore has no significant commercial relevance today.

• Ultrasonic (US) bonding, introduced around 1960, is a room-temperatureprocess and uses mechanical force and ultrasonic energy. US wedge-wedgebonding of aluminum wire to aluminum or gold pads enables the use ofwires with large diameters (typically 75 − 500 µm) primarily for high-powerelectronic applications.

• Thermosonic (TS) bonding, introduced in 1970, is a combination of ther-mocompression and ultrasonic bonding and is typically used for ball-stitchbonding of gold wire to various pad materials. The combination of heat,ultrasound and force allows a moderate level of each type of input energy.Thermosonic bonding of thin wire (typically 18 − 50 µm) is today by farthe most commonly used interconnection method in integrated circuit chippackaging.

Wire Bonding Process Technology

The two main wire bonding process technologies are ultrasonic wedge-wedge(Figure 2.3 and 2.4) and thermosonic ball-stitch bonding (Figure 2.5 and 2.6).The shape of the wire bonded interconnection is determined by the bonding toolused, which is typically either a wedge (Figure 2.4 a) for wedge-wedge bondingor a capillary (Figure 2.6 a) for ball-stitch bonding. The wedge generates twoidentical wedge bonds (Figure 2.4 b) whereas the capillary generates first a ballbond (Figure 2.6 c) and subsequently a stitch bond (sometimes called a crescentbond), as shown in Figure 2.6 d. A ball and stitch bond generated by the capillaryof a ball-stitch bonder has considerably larger dimensions with respect to the wirediameter compared to the wedge generated by a wedge-wedge bonder.

Wedge-Wedge Wire Bonding

Figure 2.3 illustrates an ultrasonic wedge-wedge bonding process, which typicallyemploys an aluminum wire that is bonded to aluminum or gold bond pads. Asshown in Figure 2.3 a, the wire is fed through the tool towards the wedge. Thewire is then pressed with a predetermined force against the bond pad. In addition,

2.1. INTRODUCTION 9

Force &

Ultrasonics

Force &

Ultrasonics

a) b) c) d) e)

Bond

WedgeWire

Clamp

Figure 2.3: Process flow of standard wedge-wedge bonding.

ultrasonic energy is simultaneously applied, generated by a transducer that vibratesthe wedge parallel to the substrate and in a direction along the wire axis, with afrequency typical of 120 − 140 kHz [10], as depicted in Figure 2.3 b). The toolthen moves towards the second bond position (Figure 2.3 c) and performs a secondbond that is similar to the first one (Figure 2.3 d). Finally, the wire clamp isclosed and the wire is torn off directly behind the wedge by pulling back the tool,as depicted in Figure 2.3 e. Ultrasonic wedge-wedge bonding of aluminum wireis an attractive room-temperature process and enables the use of both thin wiresfor fine pitch applications and thick wire for high power applications. However,automated wedge-wedge bonding tools are comparatively slow and have limitationsin generating arbitrary loop shapes and directions [8, 10, 11].

a) b)

Figure 2.4: a) SEM image of a wedge tool (MaxiBond wedge, Gaiser Tool Company) b) SEMimage of a wedge bond.

Figure 2.4 a shows an SEM image of the lower part of a wedge tool thatis typically made of tungsten carbide, titanium carbide or ceramic/metalliccomposites (cermet). The main features of a wedge tool are the feed hole visibleon the right side of the structure and the exit hole in the center that are used tofeed the wire towards the bond foot situated at the left side. The bond foot is thepart of the wedge tool that is in contact with the wire during the bond process anddefines the impression in the bonded wire, depicted in Figure 2.4 b [12].


Ball-Stitch Wire Bonding

Figure 2.5 a illustrates a thermosonic ball-stitch bond process using gold wire thatis bonded to gold or aluminum pads. This technique and material combinationis by far the most commonly used interconnection method in integrated circuitpackaging. As shown in Figure 2.5 a, gold wire is fed through a ceramic bondcapillary, an electrical flame off (EFO) melts the wire and forms a gold sphere,the free air ball (FAB), at the end of the wire. The free air ball is then pulledup to the tip of the capillary and the tool moves laterally to a position above thedesired bond pad on the device, which is placed on a heated work piece holder(Figure 2.5 b). The tool then presses the free air ball with a defined force againstthe pad. Together with a simultaneous input of ultrasonic energy, the weld betweenthe ball and the pad is generated, as depicted in Figure 2.5 c. The tool then movestowards the second bond pad where the stitch bond is performed (Figure 2.5 dand e). As shown in Figure 2.5 e, the wire is compressed between one side of thecapillary tip and the pad. Again force, ultrasonic and heat energy create the weldbetween the wire and the pad. The tool then moves upwards (Figure 2.5 f) wherethe wire is torn off by closing the wire clamp and moving the tool straight upwards(Figure 2.5 g).

Temperature

Force &

Ultrasonics

Ball Bond

Temperature Temperature

Force &

Ultrasonics

Stitch Bond

Temperature Temperature Temperature

a) b) c) d) e) f) g)

Flame Off

Electrode

Bond

Capillary

Wire

Clamp

Free Air Ball

Figure 2.5: Process flow of standard thermosonic ball-stitch bonding of gold wire. A free airball (FAB) is ball-bonded to a metal pad, and after generating a specific loop shape of the wire,it is stitch-bonded to the second bond pad.

Thermosonic ball-stitch bonding of gold wire is the method of choice for mosthigh-volume, low-cost applications since it is a very mature process, providing highreliability and throughput. This process offers the highest degree of freedom andflexibility for arbitrary loop shapes and directions of the bonded wire [8, 10, 11].This is mainly due to the fact that the wire can be led off to any position withrespect to the first bond position. The ball bond has a circular shape and henceoffers a 360 freedom of movement of the bondhead and looping of the wire towardsthe second bond position. Wegde-wedge bonding in contrast has a more limitedfreedom of movement of the bondhead due to the predetermined direction of thewire that is caused by the wedge bond [10, 11]. In ball-stitch bonding, various loopshapes, mainly driven by shrinking package sizes, have been implemented over theyears. Common loop shapes in electronics packaging are depicted in Figure 2.7.The standard loop with a rounded wire profile (Figure 2.7 a) can be modified to a

2.1. INTRODUCTION 11

a) b)

d)c)

Figure 2.6: a) Photo micrograph of a fine-pitch ceramic bond capillary (SBNS-35DP-C-1/16-XL, SPT Roth Ltd, Switzerland) with a 25 µm gold bond wire and free air ball. The tip of theflame off electrode is visible in the lower right corner of the image. Inset: The tip of the capillaryis tapered for fine-pitch applications. b) Scanning electron micrograph (SEM) image of threeball-stitch bonds with typical loop shape and a gold wire diameter of 25 µm. c) SEM image offine-pitch ball bonds with 20 µm gold bond wire. d) SEM image of a stitch bond.

flat loop (Figure 2.7 b) in order to create a lower loop profile and thereby reducethe volume of the package. More specialized loops with even lower wire profiles canbe created by reverse bonding (Figure 2.7 c). In reverse bonding first a ball bumpis placed on the die, then a ball bond is performed on the lead and the wire finallyis stitch bonded on the ball bump on the die. Figure 2.7 d depicts another type ofloop that is used for ultra small chip scale packages (CSP).

a) b)

Die Package Die Package

d)c)

Die Package Die Package

Figure 2.7: Some representative examples of loop shapes that can be created by ball-stitch wirebonding. a) Standard forward loop. b) Flat forward loop. c) Reverse loop. d) Chip scale package(CSP) loop.


Gold ball bumping

Gold ball bumping is a variation of ball-stitch bonding and is widely used to creategold-to-gold interconnections for flip-chip packages used for e.g. HB LEDs andCMOS imagers [13]. The estimated cost per 100,000 ball bumps is approximately14 $ in high-volume [13] and thus, ball bumping can be cost competitive towardswafer-level plating processes for scenarios with I/O counts on that order or below.

T T TT

Force &

Ultrasonics

a) b) c) d) e)

Figure 2.8: Ball bumping process flow. A free air ball is ball-bonded to a metal pad and thewire is subsequently torn off.

Gold bumps are typically formed on wafer-level according to the procedureillustrated in Figure 2.8. Similar to the ball-stitch bonding process, an electricalflame off (EFO) forms the free air ball, as depicted in Figure 2.8 a. The free airball is then thermosonically bonded to a pad with the help of force, ultrasonics andtemperature (Figure 2.8 c). Instead of performing a second stitch bond, the toolnow moves to a certain height where the wire is torn off by closing the wire clampand moving the tool straight upwards (Figure 2.8 d and e).

After bumping, the wafer is typically diced, flipped and thermosonically weldedto a substrate with corresponding gold pads. Figure 2.9 a and b show standardgold ball bumps. In ball bumping it is common to planarize the top surface ofthe bumbs. This technique is called coining and creates uniform bump heights,flat bump surfaces and an increased bond area, as shown in Figure 2.9 c. Pai etal. use patterned coining tools for imprinting high aspect ratio structures in thebumps [14]. Ball bumping also enables the stacking of multiple bumps, as depictedin Figure 2.9 d. This is commonly used as a technique to create higher standoffsbetween flip-chip bonded dies [8, 15]. Wire-bonded ball bumps can serve as analternative to regular TSVs and have already been implemented in mass-produceddevices such as CMOS image sensors [16]. However, this method is restricted toTSVs with low aspect ratios and thin substrates as the possible dimensions of ballbumps are limited.


a) b)

c) d)

Figure 2.9: SEM images of a) a standard Au ball bump, b) a low-profile Au ball bump, c) acoined ball bump and d) stacks of two and three ball bumps.

Materials Used in Wire Bonding

All wire bonding processes are limited to certain material combinations and can besensitive to imperfections and contamination of the bond pad surfaces [8, 10, 11].Commercially relevant and well-developed wire-pad material combinations are Au-Au, Au-Al, Au-Cu, Au-Pd, Al-Au, Al-Al and Al-Ni. Strongly emerging wire-padmaterial combinations are Cu-Al and Cu-Cu due to a more attractive commodityprice of copper as compared to gold [10]. For mainstream wire bonding, copper wireis now firmly established and many resources are focussed on optimization of thisprocess [17–19]. Other, more exotic wire-pad combinations such as Pd-Al [20, 21],Pt-Pt [22], Ni-SiC [23], Ag-Au [24], Ag-Al [25] and Ag-SiC [26] have been reportedas well. It has also been shown to be possible to bond gold wires to silicon structureswith the help of standard wire bonding tools. In this case, the bond mechanism isnot based on metal/metal-welding but on a plastic deformation of a ball bond intoa silicon hole, which results in a mechanical attachment [27]. This method howeverrequires a wire with a low hardness in order to enable a plastic deformation of thewire without deforming or damaging the substrate.

Unconventional uses of wire bonding technology

One of the key opportunities represented by the wire bonder is the ability to formmicro-structures directly from micron-sized metal wire stock. The combination ofwire stock, kinematics of the bond-head and capillary and wire loops enable therapid formation of solenoids. To date, a range of morphologies have been explored inorder to create electrical coils for applications including MRI [28–30], NMR [30, 31],


levitation [31], THz meta-material [32], energy harvesting [33, 34], transformers andDC-DC converters [35] and inductors [36].

Wire-bonded structures have also been explored for use as RF devices. Byforming a single semicircular loop between two separated bond-pads, Willmot [37–39] has created a half-wavelength loop antenna at 40 GHz for use in an on-chipradio. In order to overcome the space limitations of on-chip waveguides, Lim etal. [40] have created slow wave structures for a lower frequency range (GHz), fromco-planar on-chip capacitor plates, connected via wire bonds to form a classicallumped LC transmission line structure. Yet another productive area of wire-bondexploration is RF signal conditioning. Khatri et al. [41] employ two orthogonallyplaced sets of three chip-to-substrate wire bonds that connect to the RF electronics,to form a band pass differential Butterworth filter structure for the lower GHzdecade. This in turn exploits the mutual inductance of adjacent wires and theaccurate on-chip capacitors. Similarly, [42] uses patterned capacitors and wire bondlengths as inductors to form an RF structure connected to an integrated MEMS RFswitch. In order to achieve microwave filter tunability, Zhou et al. [43] have createda hierarchy of capacitive and inductive patches close to a three-pole microstrip filteron a low-loss substrate.

One of the early unconventional uses of wire bonders was reported by Stieglitzet al. in [44–46], in which the ball bumps were used as rivets to attach, bothmechanically and electrically, a flexible micro-ribbon to a microchip. The maintarget of this application was neural prosthesis. This idea was later picked upin [47], for use in implantable MEMS with an attached micromachined flex cable,achieving contact resistances below 1 mΩ. The ball bump can also be used as acomplete printing platform, and Pai et al. [14] have combined wire bonding withimprinting in an interesting manner. By first forming a ball bump on a gold platedwafer substrate, it is then reshaped through plastic deformation using a previouslyprepared silicon microstructured stamps.

Vertical wire bond studs, out of the wafer or chip plane, are useful structuresin their own right. Tonomura et al. [48] have created a chemical analysis chip thatuses an array of 16 wire bond stud wires, protruding above the chip surface andinto a liquid channel formed above the chip. Another interesting application of wirebonding is the use of parallel bond wires as movable masses in an accelerometerfor very-low-cost sensor applications [49–51]. Therefore, parallel bond wires areconnected to the sensor read-out electronic circuit. The wire movement due toexternal acceleration forces changes their capacitance, which can then be measuredas the sensor signal. In another work, micro-scale hotwire anemometers for air-flowsensing have been fabricated by using wire bonding of aluminum bondwires.

The wide spectrum of applications reveals that wire bonding is a fast and flexiblemicrostructuring tool, with growing potential for new applications, as new processcapabilities are being explored. Wire bonding is a viable approach for efficientlyintegrating wire materials with interesting properties into micro-structures, andthereby enabling heterogeneous microsystems. A detailed review of all applicationareas can be found in paper 12.


2.1.2 Introduction to through silicon via technologyThree main technologies for the electrical interconnection of stacked dies in2.5D and 3D SiPs exist: wire bonding, flip-chip bonding and through siliconvias (TSVs). Especially TSVs enable shorter signal path lengths with superiorelectrical characteristics in terms of lower capacitive, resistive and inductiveparasitic components [7]. Therefore, large development efforts for the realization ofreliable and cost-efficient TSVs are currently ongoing and the first commerciallyavailable devices such as MEMS inertial sensors, MEMS microphones, CMOSimagers and HB LEDs successfully incorporate TSV technology [52, 53]. Asshown in Figure 2.10, the structure, and hence the fabrication, of TSVs can beroughly divided into three major elements: a vertical hole through the substrate, aconductive core and a dielectric layer acting as an insulator between conductor andsubstrate. The most common fabrication techniques of these elements are brieflydiscussed in the following part.

Substrate Insulator Conductor

a) b) c)

Figure 2.10: Cross-sectional view of three common TSV designs. a) Solid metal filled TSV, b)annular metal-lined TSV and c) metal-lined TSV with tapered side wall profile (Paper 1)

Via holes — Various methods for the formation of via holes exist and can becategorized into dry etching [5, 54–60], wet etching [55] and drilling processes [52,61]. Via holes can have either straight [56, 57, 59, 60] (Figure 2.10 a and b)or tapered sidewall profiles [54, 58] (Figure 2.10 c) as well as combinations ofboth [5, 55]. Typical diameters of via holes vary between a few microns [6, 56]and several hundreds of microns [59], and the majority of TSVs have an aspectratio between 1:1 and 10:1. Deep Reactive Ion Etching (DRIE) is by far themost commonly used technology to form TSV holes. It offers excellent processcontrollability and is capable of creating high aspect ratio features with specificsidewall profiles and topographies. The etch rate of DRIE is aspect ratio dependentand may cause several topographic imperfections on the sidewalls of the via holessuch as scalloping, caused by alternating etch- and passivation-steps, which resultsin corrugated sidewalls. By using state-of-the-art DRIE equipment these effects canbe minimized [54] and adopted to the demands of subsequent insulation, barrier andseed-layer deposition steps (Paper 4). Laser ablation is an emerging low-cost, high-speed process for drilling TSV and TGV holes as it benefits from the absence of anylithographic process steps. This results in high process and design flexibility andthus lower overall costs compared to DRIE [52, 61]. Laser ablation however suffers


from a high local thermal load, crystal defects and particle generation around theperimeter of the drilled via hole. Additional cleaning and smoothening steps [61]are required and therefore reliability issues may arise due to induced stress on poresand micro-cracks [62].

Via insulator — Chemical Vapour Deposition (CVD) is a well-establishedCMOS-compatible process with moderate temperature requirements [5, 6, 56, 58]and is therefore the most commonly used method for direct deposition of silicondioxide or silicon nitride on via sidewalls. Organic dielectrics [63, 64] suchas Benzocyclobutene (BCB) [60], epoxy-based polymers [59, 60], silicone [60] orParylene [58] are used as well. Polymers, especially low-κ types with a lowerrelative permittivity κ compared to silicon dioxide, are very attractive for therealization of TSVs with improved electrical characteristics in terms of lowercapacitive parasitics [59, 65]. The relative permittivity of selected via insulationmaterials are listed in table 2.1. Furthermore, polymers can act as a buffer forthermo-mechanical stress that is caused by coefficient of thermal expansion (CTE)mismatches between the via metallization and the silicon bulk material [64–67]. Asshown table 2.1, the Young’s modulus of these polymers is typically two orders ofmagnitude lower as compared to silicon dioxide and silicon nitride.

Table 2.1: Relative permittivity κ and mechanical properties (Young’s Modulus E and Coefficientof Thermal Expansion α) of commonly used TSV insulation materials, including silicon nitrideand silicon oxide as well as emerging low-κ insulators. Silicon serves as reference in the first row.

Material κ E [GPa] α [ppm/K]Si [68] - 190 2.33SiO2 (PECVD TEOS) [69] 3.9 64 2.61Si3N4 (LPCVD) [70] 7 261 1.7-2.3BCB 3000 Series (Dow) [71] 2.65a 2.7 - 3 42.3Parylene N [72] 2.65b 2.4 69SU-8 2000 (Microchem) [73] 3.2c 2 52InterVia 8023 (Dow) [74] 3.2d 4 62

a1-20 GHz b60 Hz - 1 MHz cat 10 MHz dat 1 GHz

Via conductor — The formation of a low-resisitivity via conductor is the mostcritical and often the most costly part of the via fabrication. The two basic viadesigns are either based on solid or lined metallizations for the vertical conductor.Established processes include electrodeposition of copper [55, 56, 58–60, 67], CVDof tungsten [6, 75], CVD of polysilicon [6, 76] and the use of low-resistivity bulksilicon [57]. Especially electrodeposition of copper, being a very well-establishedsemiconductor process, is used by many research groups and implemented in mostcommercialized devices containing TSVs. Electrodeposition of copper benefits fromwidely available tool vendor support and process maturity as well as being amenableto deposition at near to room temperature, but suffers due to its complexity interms of process controllability, reliability and throughput [52]. In particular,it is challenging to implement high aspect ratio TSVs with void-free conductive

2.1. WIRE INTEGRATION BASED ON MAGNETIC ASSEMBLY 17

metal cores [52, 56, 77]. Alternative approaches to plating processes have thereforebeen investigated, such as the via filling with conductive metal pastes [5, 78, 79],solder [80, 81] as well as the use of wire-bonded ball bumps [16] (Paper 4).

Table 2.2: Electrical resistivity ρ and mechanical properties (Young’s Modulus E and Coefficientof Thermal Expansion α) of TSV metal fillings, separated by standard materials and ferromagneticelements. Silicon serves as reference in the first row.

Material ρ [Ω · m] E [GPa] α [ppm/K]Si [68] - 190 2.33Cu [82] 1.7 · 10-8 110 16.4Tu [82] 5.65 · 10-8 400 4.4Au [82] 2.2 · 10-8 77.2 14.4Ni [82] 6.4 · 10-8 207 13.1Co [82] 6.24 · 10-8 211 12.5Fe [82] 8.9 · 10-8 200 12.2

2.2 Integration of bulk wire materials based on magneticassembly

A novel approach for the integration of bulk wire materials for through siliconvia applications with medium to high I/O counts is investigated in this thesis. Aconcept based on the magnetic assembly of ferromagnetic pre-formed via cores isproposed. This assembly technique allows for a parallel and cost-effective metalfilling of via holes and hence meets the requirements of increasing I/O counts.

Magnetism as a non-contact force enables a contactless manipulation offerromagnetic features over long distances and is insensitive to the surroundingmedium and independent of details of the surface chemistry. Magnetic fieldscan have high energy densities and can influence feature sizes from millimeter tonanometer-scale [83–86]. At a macroscopic scale, magnetic forces have been usedfor the self-aligned assembly of discrete components that are magnetic or containpatterned magnetic structures. Representative applications include the assembly ofvertical-cavity surface-emitting laser (VCSEL) chips to IC substrates [87], paralleloriented assembly of components on carrier substrates [88, 89], generic wafer-levelpackaging approaches [88, 90] and the integration of SMD capacitors into through-silicon holes [91]. At micro- and nanoscales, magnetic assembly has been usedfor the trapping, alignment and assembly of magnetic nanowires [92–96]. In [83],state-of-the-art methods and applications for self-assembly are reviewed in detail.

The first part of this section introduces the novel magnetic assembly concept forthe fabrication of TSVs with very high aspect ratios (> 20 : 1), where the secondpart deals with a optimized design for the transmission of high frequency signals.


2.2.1 Through silicon vias with very high aspect ratios

a) b)

Ni

SiO2

Si BCB

c) d)

Figure 2.11: Via formation concept: a) The via hole is formed by DRIE, stopping on a silicondioxide layer. b) A conductive, ferromagnetic nickel core is placed in the via hole by magneticassembly. c) The remaining hollow space in the via cavity is filled with the thermosetting polymerBenzocyclobutene (BCB). d) A grinding and polishing step removes excess polymer and nickelfrom the front-side (Paper 4).

As illustrated in Figure 2.11, the metallization of the via is realized by aninstantaneous filling technique that magnetically assembles pre-formed ferromag-netic via cores into the via holes. The order of the metallization and insulationprocess step is reversed (Figure 2.11 b and c) as compared to most conventionalTSV fabrication scenarios (as described in section 2.1.2), where the metallizationis gradually grown on a barrier, insulation and seed layer. The proposed approachtherefore is insensitive to the topography of the via sidewall (i.e. scallops). Theinsulator used is the thermosetting polymer BCB CYCLOTENE ®, which is knownfor excellent electrical characteristics and that it is suited for a void-free filling ofhigh aspect ratio features [97]. As shown in table 2.2, the electrical resistivity offerromagnetic nickel is similar to tungsten, but approximately 3 to 4 times higherthan gold and copper. The thermal coefficient of expansion (CTE) of nickel isapproximately 20 % lower as compared to copper. Volume-manufactured nickelwires with diameters down to 10 µm are commercially available and are typicallyused for chemically resistant woven filter cloth, screen printing masks and recentlyalso as bond wire for interconnections in the high-temperature packaging of SiCelectronics [23]. The ferromagnetic properties, the availability at low cost and thefair electrical DC characteristics of nickel makes this material a highly attractivechoice for the presented TSV fabrication concept.

Figure 2.12 shows hundreds of straight nickel wires that are aligned along themagnetic field lines of a underlying permanent magnet. The wires have a diameterof 35 µm and a length of 350 µm. By moving the magnet laterally below thesubstrate, the wires can be steered to certain positions such as via holes in the


substrate. Within this work, this filling technique has been automized and used tofabricate TSVs with very high aspect ratios.

a) b)

B = 0 T B = 1.1 T

Figure 2.12: Behavior of nickel wires in a magnetic field: a) about 300 straight nickel wires(35 µm diameter, 350 µm length) without an applied magnetic field. b) a magnetic field of 1.1 Tis generated by a permanent magnet. The nickel wires align along the field lines and thereby erectthemselves perpendicular to the ground plane.

a) b) c)

e) g)f)

Silicon Silicon Oxide

Nickel

BCB

Gold

j)i)

h)

Via

Form

ation

Via

Fill

ing b

y

Magnetic A

ssem

bly

Via

Conta

cts

N

S

d)

k)

N

S

N

S Magnet

Figure 2.13: The TSV fabrication scheme can be divided into three main steps. First is theformation of the via hole by DRIE etching, second is the magnetic assembly of the conductiveTSV core and third is the filling with the dielectric (Paper 4).

The fabrication process for the TSVs is illustrated in Figure 2.13 and is based ondouble-side polished Si wafers with a silicon dioxide layer on both sides. A standardlithography and RIE on the front-side of the substrate defines the circular openingsfor the vias in the silicon dioxide hardmask, as illustrated in Figure 2.13 b. Seenin Figure 2.13 c, a DRIE process creates via holes with straight side walls. TheDRIE stops at the silicon dioxide on the bottom of the cavity. A subsequent hightemperature treatment in a furnace is used to remove polymer residuals from theDRIE passivation cycles by pyrolization. In the same furnace a thermal oxidationcreates a thin silicon dioxide layer, as shown in Figure 2.13 d. The silicon dioxidelayer ensures an electrical insulation of the via sidewalls and creates a hydrophilicsurface of the via sidewall, which is of importance for the insulation step that iscarried out later on.


Pre-fabricated nickel cores are then distributed on the front side of the targetwafer. By utilizing an automated robotic assembly tool, the permanent magnetcan be moved into close proximity to the back-side of the wafer, as indicated inFigure 2.13 f. The nickel wires that are manually placed on the wafer surface aredrawn to the location of the magnet and erect themselves perpendicular to thesubstrate surface. With programmed patterns for the magnet movement all viaholes can be filled in an automated process. The results of the performed assemblyexperiments, including the movement patterns and the yield of the filling process,are presented below.

The via cavities are subsequently filled with the thermosetting polymer BCB CY-CLOTENE ® 3022-46 (Figure 2.13 g). The subsequent hard-curing of the BCB isperformed on a hotplate in a vacuum environment in order to prevent any voidformation in the polymer. A subsequent grinding and polishing step removes excessnickel and BCB from the surface of the substrate, as shown in Figure 2.13 i. Alithography and RIE of the silicon dioxide and BCB residues opens the contactarea of the via on the back-side of the wafer, as illustrated in Figure 2.13 j. Twoconsecutive TiW / Au depositions on both sides of the wafer interconnects the nickelcores of the vias. A lithography, wet Au etch and dry TiW etch (Figure 2.13 k)is made to define Kelvin test structures intended for the measurement of the DCresistance of the vias.

Assembly ArmWafer Scanner

Wafer

Gripper

Wafer

Cassette

Assembly

Stage

a) b)

Permanent

Magnet

Wires

Robot Arm

Camera

Wafer

Figure 2.14: a) Assembly setup with the wafer gripper and assembly part on robot arm in thecentre of the table, the wafer cassette station and the assembly stage to its right. The assemblyprocess consists of four steps: 1. scanning the cassette for wafers, 2. picking the chosen wafer andplacing it on the assembly stage, 3. positioning the assembly arm, placing the magnetic via coresmanually on the substrate and carrying out the automated magnetic assembly, 4. putting thewafer back into the cassette. b) Schematic drawing showing the custom built assembly arm thatconsists of a permanent magnet mounted on an aluminum sheet and a camera above the magnet.

For the magnetic assembly process, a robotic setup shown in Figure 2.14 a,has been devised. It is based on a wafer handler robot for 200 mm substrates.Figure 2.14 b shows a schematic depiction of the robot arm that has been modifiedin order to mount a permanent magnet. The tool enables programmable movementof the magnet with three degrees of freedom and a precision of 30 µm. In this way


different movement patterns were implemented and adopted to varying layoutsof via holes. Also depicted in Figure 2.14 is a camera for optical inspection,which is mounted directly above the magnet and faces the front-side of thesubstrate. By using a wafer handler robot for the magnetic assembly, an automatedcassette-to-cassette process can be implemented, i.e. picking a wafer from aninput/output cassette, placing it on a dedicated assembly stage, performing themagnetic assembly and placing the wafer back into the cassette.

MagnetArray Chip

Array Chip

Magnet

b)

a) 5 mm

d

d

Movement

Pattern A

Movement

Pattern B

c)

0

10

20

30

40

50

60

70

80

90

100

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210

66 81Time [s]

Yie

ld -

Fille

d H

ole

s [

%]

Fast pattern A (fig. 6 a)

Fast pattern B (fig. 6 b)

Slow pattern B (fig. 6 b)

Slow pattern B (fig. 6 b)

Figure 2.15: Movement patterns of the assembly robot: a) Small advancing rectangles with anedge length of d = 0.76 mm. b) Long linear sweep with a length of approximately d = 1.5 cm.The sweeping is based on a radial movement of the robotic arm. In both illustrations the sweepsare approximated to straight linear movements due to the large radius of the radial movement(approximately 0.75 m) and the comparable short sweep length d. c) Filling rates for the assemblyof via arrays (10 × 10 holes, approximately 2500 to 3000 wires). Two different movement patternsand two different speeds were tested. The slow patterns exhibited a yield of 100 % and the highestfilling rate.

A series of assembly experiments with different movement parameters wasconducted. As shown in Figure 2.15, the assembly process was evaluated on10 × 10 via arrays with an excess amount of nickel wires (approximately 2500to 3000). The wires in these experiments had diameters of 35 µm and lengths of360 µm. The via holes had diameters of 42 µm and were fabricated in arrays of10 × 10 - vias with a pitch of 350 µm on a substrate with a thickness of 350 µm.With respect to the array size of 3.5 mm and the size of the cubic permanent magnetwith an edge length of 5 mm two different movement patterns were programmed,as schematically illustrated in Figure 2.15. The pattern in Figure 2.15 a has avery short sweep length d of 0.76 mm, whereas the pattern in Figure 2.15 b has asweep length d of 1.5 cm. Furthermore, the experiments have been conducted attwo assembly motion speeds, a fast motion (Ω1 at 120/s) and a slow motion (Ω2at 4/s). The vertical distance of the magnet to the back-side of the wafer wasapproximately 125 µm in all experiments.


As Figure 2.15 c shows, the filling rate, i.e. the number of filled via holes persecond, is dependent on the speed and the sweep length d of the assembly motion.Larger sweep lengths result in a faster filling process. The lateral force on thewires only occurs due to a gradient in the magnetic field, which is more prominentnear the edge of the cubic magnet. For small sweep lengths this implies that thewires located above the center of the magnet move very little or not at all, whichexplains the poor filling rate from the movement pattern shown in Figure 2.15 a.Also shown in Figure 2.15, the assembly process improves with decreasing speed ofthe assembly motion. A fast assembly motion causes the wires to tilt from theirperpendicular position while being dragged along the substrate surface which makesit more difficult to pull them into the via holes. Slower motion speeds reduce thewire tilt and therefore increase the filling rate. As shown in Figure 2.15, a fillingyield of 100 % within 66 s to 81 s could be demonstrated by using the movementpattern indicated in Figure 2.15 b and a slow motion speed (Ω2 at 4/s).

Figure 2.16: SEM image of a 30 × 30 array with a pitch of 120 µm of nickel wires placed inthe via hole prior to to the filling of BCB. The minimum via hole diameter for a 35 µm wire wasdetermined to be 40 µm.

As shown in Figure 2.16, assembled wires that are protruding from the substratesurface act both as a mechanical and magnetic obstruction for the excess wiresduring the assembly process. These two effects have a negative impact on thefilling rate. In order to overcome the mechanical obstruction, the wires can becut to a length that is the same or shorter as the depth of the via holes. Due tothe magnetization of the nickel during the assembly process, the excess wires canstick to the ends of assembled wires and cluster even after the assembly-magnetmoves on. It is possible to demagnetize, and thereby eliminate the clustering of theferromagnetic nickel rods, by reversing the magnetic field. This can be achievedby either flipping the permanent magnet or using an alternating magnetic field


that is induced by an electromagnet. By flipping the permanent magnet it waseven possible to fill a via array with a very dense pitch of 120 µm with wires thatwere considerably protruding the surface by approximately 150 µm, as shown inFigure 2.16.

100 µm

Aluminum

Nickel

BCB

Silicon

Aluminum

Nickel

BCB

Silicon

a) b)

Figure 2.17: a) SEM image of a polished cut through a TSV with an aspect ratio of 8:1. Note:As indicated in the drawing, the sample was tilted during the grinding process of the cross section,which leads to the apparent view of a non-constant via diameter. b) Optical microscope imageof a polished cut through a TSV with an aspect ratio of 31:1 for the metal core and an overallaspect ratio of 24:1.

Figure 2.17 a and b shows two cross-sectional SEM images of polished cuts ofmagnetically assembled TSVs. The filling with BCB was successfully conductedwithout any visible air-voids or defects after the complete hard curing procedure.Also, due to the use of the wire as a base material, the nickel core is inherentlyvoid-free. There are no indications for delamination of the BCB at the via sidewalls or the via core, which might cause mechanical or electrical failures of the vias.Figure 2.17 a shows the cross-section of a magnetically assembled TSV with anaspect ratio of 8:1 that consists of a nickel core with diameter of 35 µm, a length of325 µm and a via hole diameter of 20 µm. As depicted in Figure 2.17 b, a similarinspection was performed with a magnetically assembled TSV with an aspect ratioof approximately 24:1. This TSV consists of a nickel core with diameter of 15 µmand a length of 470 µm, which was assembled in a via hole with a diameter of20 µm.

The electrical DC resistance of magnetically assembled nickel TSVs witha diameter of 35 µm and a length of 250 µm has been evaluated by a 4-wire measurement. The measured TSV DC resistance including the contactmetallization on the front- and back-side of the chip is approximately 40 mΩ, whichis in good agreement with the theoretical resistance, which is approximately 20 mΩexcluding any contact metallization.

More details concerning wire preparation, fabrication and characterization canbe found in Paper 4.


2.2.2 Through silicon vias for high-frequency applicationsEven though DC resistances of ferromagnetic materials such as nickel, cobalt oriron are within a very close range to those metals commonly used for vias such ascopper, gold, aluminum, or tungsten, there is an enormous discrepancy regardingtheir performance for the transmission of AC signals. This is mainly due to theskin effect which causes the resistance of a conductor to substantially increase withincreasing frequency. The skin effect causes the flow of an alternating current in aconductor to be confined to a small area close to the surface of the conductor. Thearea of confinement is dependent on the frequency of the alternating current andcan be described by the skin depth. In Equation 2.1, the definition of the skin depthδ is given in relation to the specific electrical resistivity ρ, the angular frequency ofthe current ω, and the magnetic permeability µ. The skin depth decreases for higherfrequencies, causing the effective electrical resistance of the conductor to increase.Especially, for high frequency applications, ferromagnetic materials provide verypoor conductivity (i.e. low skin depth) due to their high magnetic permeability µ.

δ =√

2ρωµ

(2.1)

Gold Nickel

Au-coated Ni wire

BCB

Gold

Nickel

30 µm

a)

b)

Figure 2.18: a) SEM image of a gold-coated nickel wire. In order to evaluate the thickness ofthe electroplated gold layer, a small pit was formed on the wire surface by focused ion beam (FIB)milling. The gold thickness was measured to be 1.7 µm. The surface of the gold film has a roughsurface, which is characteristic for electro-deposited layers. b) Top-view on a TSV after grindingthe front-side.

In order to improve the high frequency capabilities of this TSV concept, nickelwires with a gold-cladding were fabricated. In this way, the ferromagnetic propertiesneeded for the magnetic self-assembly process are combined with the high electricalconductivity of gold. Due to the skin effect, the current density is greatest atthe outermost region of the conductor. Thus, the skin effect can be utilized toconfine most of the current to the gold cladding of the wires, which enables aconsiderable improvement of the high frequency conductivity and reduction of the


signal losses [98]. The thickness of the gold layer is determined by the skin depthat the targeted operating frequency of 75 GHz. For this frequency, the skin depthin gold was calculated to be 0.29 µm. In order to ensure satisfying broad bandcharacteristics of the TSV, a gold layer with a thickness of 1.5 µm was depositedby electroplating on the nickel wires, as shown in Figure 2.18 a and b.

Si

Front-Side Back-Side TSV

SiO2 Au

Ni

BCB

Signal TraceGround

Trace

a)

b)

c)

Figure 2.19: a) Cross section and b) top-view of the micromachined coplanar-waveguide (CPW)that have been used for the evaluation of the electrical performance. c)

For the RF characterization, coplanar-waveguide (CPW) structures have beendesigned and fabricated according to the process flow that is depicted in Figure 2.13.High-resistivity silicon substrates (5000-8500 Ωcm) have been used for the fabri-cation of the CPW structures depicted in Figure 2.19 a and b. The CPW hasa signal line width of 120 µm and a gap of 85 µm, where the total length of thetransmission line is 2450 µm with a impedance of 50 Ω at the nominal frequency of75 GHz. To extract the transmission loss from the test structure, a reference CPWtransmission line without any interconnections was fabricated on the front-side ofthe wafer. The test structures, illustrated in Fig. 3, are measured using a vectornetwork analyzer (VNA), which is calibrated with a standard short-open-load-thru(SOLT) technique from 100 MHz to 110 GHz. The measured results indicate thatthe CPW integrated with gold-coated nickel wire interconnections offers an excellentRF performance for a very wide band. At the nominal frequency of 75 GHz, thereturn loss is better than −11 dB and the insertion loss is better than −2.26 dB.As compared to the CPW with direct transmission line trace from the input tothe output ports (no interconnections), a single section of the proposed TSVs hasan insertion loss of −0.53 dB. Moreover, a return loss of better than −10 dB isachieved up to 85.7 GHz. The insertion loss at 85.7 GHz is −3.2 dB, resulting inan insertion loss of −0.96 dB per single section of interconnection.

Although the vertical interconnections in [99–103] can achieve slightly wideroperational bandwidths up to 110 GHz, the aspect ratios of these through siliconconnections are much lower than the novel concept proposed in this work. This is


due to the fact that the designs in [99–103] rely on anisotropic etching of the siliconwafer, typically with potassium hydroxide (KOH), whereas the concept presentedhere utilizes a plasma etching process of the substrate, resulting in a more compactTSV design and a better control of the process parameters.

More details concerning wire preparation, fabrication and characterization canbe found in Paper 8.

2.3 Integration of bulk wire materials based on wirebonding technology

This section introduces novel methods for the integration of bulk wire materialson wafer level that have been developed within this thesis work. The first partis dedicated to novel uses of existing wire bonding technology for yet anotherthrough silicon via fabrication concept, liquid and vacuum packaging applicationsand microactuators.

2.3.1 Wire-bonded through silicon viasIn this part, two novel fabrication methods for TSVs based on wire bondingtechnique are presented. The first wire-bonded TSV concept is optimized forhigh electrical performance for for demanding applications and the second conceptfocuses on the realization of high aspect ratio TSVs.

Wire-bonded through silicon vias with high electrical performance

In order to reduce resistive, inductive and capacitve (RLC) parasitics both thedesign of the via and the used materials have to be considered. The mainrequirements are:

• A metal via core with low AC/DC electrical resistance for low conductivelosses in the via

• An insulation layer with a low relative permittivity (i.e. a low-κ material)and sufficient thickness for low capacitive coupling to the substrate

• A sufficiently large via pitch for low capacitive coupling between the vias

They key for a TSV with high electrical performance is a low resistance metalcore and a low-κ insulator with a sufficient thickness. The proposed TSV designis therefore based on a high quality and inherently void-free gold metal core thatis integrated into the via structure by wire bonding technology. As depicted inFigure 2.20, a wire is ball-bonded to a metal membrane on the bottom of the viacavity. The remaining hollow space of the cavity is subsequently filled with a low-κ dielectric, which both acts as an insulator and provides mechanical support forthe via core. Similar to the magnetically assembled TSV concept, the order of

2.3. WIRE INTEGRATION BASED ON WIRE BONDING TECHNOLOGY 27

the metallization and insulation process step is reversed as compared to traditionalTSV fabrication schemes.

BCBSilicon

Aluminum

Gold

Figure 2.20: CAD image with a cross sectional illustration of the main elements of the wirebonded TSV design. The metal core in the center of the via is a ball-bonded wire on a metalmembrane and is surrounded by a polymer (Paper 1).

The via core consists of a gold bond wire with a diameter of 25 µm. In order tobe able to wire-bond at the bottom of the via cavity and to achieve a low capacitivecoupling of the metal core to the substrate, a via hole diameter of 200 µm waschosen. The electrical characteristics of a TSV based on the proposed design isshown in Figure 2.21. The inductance shows a deviation of less than 25 pH but theresistance changes from 40 mΩ at DC to 250 mΩ at 50 GHz. For digital signaling,the change in resistance is still negligible but it must be be potentially consideredfor other applications. The capacity for the proposed design is on the order of 20 fF.

The fabrication process for the TSVs is depicted in Figure 2.22 and is based on300 µm thick double-side polished 100 mm-substrates with a silicon dioxide layer onboth sides. A lithography and RIE process on the front-side of the substrate removesthe oxide and defines the circular openings for the vias in the oxide hardmask. Analuminum layer with a thickness of 5 µm is sputtered on the unpatterned backsideof the wafer (Figure 2.22 b). A DRIE process creates the via holes with straightside walls. The etch stops on the lower silicon dioxide layer on the bottom of thecavity, which is subsequently removed (Figure 2.22 c). As depicted in Figure 2.22 d,a bond capillary with a small tip-diameter for ultra-fine pitch applications is usedin order to be able to place the wire bond on the bottom of the cavity. The bondhead moves down after the free-air-ball (FAB) formation by an electrical discharge.The bond head moves subsequently straight upwards, generating a tail length of


50 100 150 200 250 300 350 400 450 50015

20

25

30

35

40

45

Insulation Thickness (BCB) [µm]

To

tal C

ap

acitan

ce o

f th

e v

ia [

fF]

a) b)

0 10 20 30 40 500

50

100

150

200

250

Resis

tance [m

Ω]

Frequency [GHz]

0 10 20 30 40 50172

173

174

175

176

177

Inducta

nce [pH

]

Resistance

Inductance

Figure 2.21: RLC Simulation: a) Frequency-dependence of the resistance and inductance of asingle wire-bonded via between 100 MHz and 50 GHz. Au core diameter = 25 µm, BCB diameter= 100 µm b) Simulated capacitance for a TSV with BCB insulation with a thickness ranging from1 µm to 500 µm, Au core diameter = 25 µm, via length = 300 µm (Paper 1).

about 400 µm (Figure 2.22 e). A second electrical flame off (EFO) cuts the wireon a spot above the upper substrate surface (Figure 2.22 f). The via cavities aresubsequently filled with the thermosetting polymer BCB CYCLOTENE ® 3022-46(Figure 2.22 g). The subsequent hard-curing of the BCB is performed on a hotplateusing the temperature profile according to the manufacturer’s standard processprocedures [71]. The curing procedure was performed in a vacuum environmentat 0.02 mbar in order to prevent any void formation in the polymer. A grindingand polishing step of the frontside removes the remaining gold of the bond wireand the BCB from the surface of the substrate (Figure 2.22 h). A final aluminumdeposition and patterning step contacts the gold core of the via (Figure 2.22 i).

The wire bonding and the filling process are the most crucial steps in thepresented fabrication scheme and have therefore been extensively investigated. Aprocess for wire bonding on a metal membrane has been developed with a set ofbond parameters optimized for room temperature conditions, low bond force andmoderate ultrasonic power. The formation of truncated bond wires with the helpof a second flame-off showed the best results in terms of straightness of the wireand overall process reliability, as shown in Figure 2.23 a. The void-free dielectricfilling with BCB and its characteristics have been investigated with the help offocused ion beam (FIB) milling, then subsequent SEM inspection (Figure 2.23 b -d). There were no damages, such as cracks or holes in the aluminum membranevisible, which could have been caused by the wire bonding process. The filling withBCB could be successfully conducted without any visible air-voids. Regarding thepolymer, typical shrinkage during cross-linking led to a delamination at parts of theAu/BCB interface with a gap width of less than 1 µm (Figure 2.23 d). There are noindications that the delamination causes mechanical or electrical failures of the via,however, the general reliability of this TSV concept remains to be experimentally


a) b) c)

d) f)e)

Silicon Silicon Oxide Gold BCBAluminum

g) i)h)

Via

Form

ati

on

Wir

e B

on

din

gV

ia

Fil

lin

g

Figure 2.22: The fabrication scheme can be divided into three major tasks. First is the formationof the via hole by DRIE etching, second is the wire bonding of the conductive TSV core and lastis the filling with the polymer.

verified. The electrical characterization showed an average resistance of 86 mΩ perwire-bonded TSV.

b) prior to FIB-milling

outer viadiameter

d) close-up Al

BCB Au

c) after FIB-milling

Au ballAu wire

Delamination

a) after wire bonding

Figure 2.23: The fabrication scheme can be divided into three major tasks. First is the formationof the via hole by DRIE etching, second is the wire bonding of the conductive TSV core and lastis the filling with the polymer (Paper xyz).

A proof-of-concept for the fabrication of wire-bonded TSVs with an overallaspect ratio of 1.5:1 has been demonstrated. Smaller TSV diameters and higheraspect ratios are feasible but limited by the wire bonding process. The usage ofbond capillaries with smaller tip-diameters and/or thinner substrates should enable


via diameters down to 100 µm. The concept therefore is suitable for applicationswith a comparatively low via density and large TSV pitch and also in order toretain high electrical performance in terms of low RLC parasitics and low crosstalk.More details concerning simulation, fabrication and characterization can be foundin Paper 1.

Wire-bonded through silicon vias with high aspect ratios

For applications that do not have as high requirements for the electrical performancebut instead require higher aspect ratios of the TSVs, an alternative wire-bondingprocess has been developed and a proof-of-concept device has been manufactured.The concept is based on a long bond wire that is fed into a through hole with abarely larger diameter than the wire. The wire is then fixed by a stitch bond tothe surface of the substrate.

a) b) c)

e) f)

h)g)

Via

Form

ati

on

Wir

e B

on

din

gV

ia

Fil

lin

g

d)

i)

Silicon Silicon Oxide Gold BCB

Figure 2.24: The fabrication scheme can be divided into three major tasks. First is the formationof the via hole by DRIE etching, second is the wire bonding of the conductive TSV core and lastis the filling with the polymer.

The fabrication process for the TSVs is depicted in Figure 2.24 and is basedon 625 µm thick double-side polished 200 mm-substrates with a silicon dioxidelayer on both sides. A lithography and RIE process on the front-side of thesubstrate removes the oxide and defines the circular openings for the vias in theoxide hardmask. A subsquent DRIE process creates the via holes with straightside walls (Figure 2.24 b). The etch stops on the lower silicon dioxide layer on the


bottom of the cavity, which is subsequently stripped. A thermal oxidation createsa new insulation layer on front- and backside and the via sidewalls. A TiW/Aulayer is the sputtered on the front-side as bond metallization (Figure 2.24 c). Asdepicted in Figure 2.24 d, a bond capillary feeds a long Au wire in the via hole. Thebond head moves subsequently sidewards and performs a stitch bond, as shown inFigure 2.24 e and f. The bondhead finally moves upwards and generates a tail witha sufficient length for the next via filling. The via cavities are subsequently filledwith the thermosetting polymer BCB CYCLOTENE ® 3022-46 and hard-cured invacuum (Figure 2.24 g). A grinding and polishing step of the front- and back-sideremoves the remaining gold of the bond wire and the BCB from the surface of thesubstrate (Figure 2.24 h). A final Au deposition and patterning step contacts thegold core of the via (Figure 2.24 i).

a) b)

Stitch Bond

Gold

BCB

Silicon

Figure 2.25: a) Array of 16 wire bonded TSVs metal cores. The close-up illustrates thesuccessfully integrated details of the metal core, prior the subsequent filling using BCB. b) Cross-sectionial view on a wire bonded TSV with an aspect ratio of 20:1.

With this process, gold wires with a diameter of 20 µm and a length ofapproximately 650 µm were fed into via holes with a diameter of 30 µm, as depictedin Figure 2.25 a. Figure 2.25 b shows across-sectional SEM image of a polished cutof the via after the filling and hard curing of BCB. Both the BCB insulation andthe metal core are void-free. The metal core is however slightly tilted due to thebond process. There is however no risk of short-circuiting the via and the substrateby a bent wire as the via sidewalls are insulated by a silicon dioxide layer. Withthis fabrication method, TSVs with aspect ratios of up to 20:1 were manufactured.

2.3.2 Room-temperature wafer-level integration of liquidsThe use of liquids in MEMS devices is ever increasing. Currently, applications rangefrom drug delivery systems [104] and small volume chemistry, e.g. electrochemicalgas sensors [105], to MEMS lenses with variable focal length [106] and microhy-draulics [107]. Liquid integration, i.e. filling and sealing, at the microfabrication


stage is a recent feature which can enable new devices, simplify production ofexisting devices and ease the use of existing devices by enabling liquid filling duringdevice production.

However, difficulties associated with integrating liquids at the microfabricationstage include high evaporation rates at elevated temperatures. Some applicationsadditionally contain temperature-sensitive species which limit the temperaturebudget in processing. The maximum safe temperature can be as low as 37 Cfor sensitive or biological materials. This temperature limit has, in previous waferlevel liquid-integration schemes [108–113], restricted the sealing method to a room-temperature polymer process, instead of a more hermetic sealing method utilizingceramics, glasses and metals. Two other methods for liquid sealing have utilizedparylene, either for deposition directly on a liquid droplet [114] or for collapsingvalves which seal the liquid cavity by stiction after drying of excess liquid [109, 115].

Since the diffusion distance through the seal of the package often is muchshorter than through the bulk of the package, the seal material type has a greaterimpact than the bulk material type on the hermeticity of the package. Comparedto more established sealing materials such as glasses and metals, polymers aretypically several orders of magnitude more permeable to moisture [116]. This highpermeability makes polymers unsuitable as seal material for hermetic packaging.To address this, packaging by embossing gold rings into gold [117] and gold coldwelding [118] has been shown. Gold has been the preferred metal due to its highductility. However, both these methods require additional mechanical stabilizationby polymers after sealing. Liquid filling of the cavity during bonding can alsobe difficult. Two options for fillings exist: serial pipetting and liquid immersion.

a) b)

Gold Stud

Bump

Access

Port

Sealed

Access

Port

To Liquid

Cavity

Gold

Figure 2.26: Hermetic sealing concept for the integration of liquids: a) One or several accessports that lead to a liquid-filled cavity are sealed by b) placing a Au ball bump centered on eachaccess port. A reliable metal/metal welding joint between the Au ball bump and the Au topsurface of the device creates a hermetic seal of the access port.


Immersion is useful for single-phase, non-fouling and inexpensive liquids, whereadditionally adhesive bonding and sealing has been shown in the submergedstate [108, 110] (Paper 2).

Ball bumping technology is utilized for a novel concept for the hermeticintegration of liquids. As illustrated in Figure 2.26, the concept is based on thehermetic sealing of access ports or inlets that lead to a liquid-filled cavity. First, thecavities including access ports are fabricated on wafer-scale using standard MEMSprocessing such as DRIE and anodic wafer bonding. Then the cavities are eitherfilled in parallel by submerging the wafer using a vacuum chamber or individuallyfilled by automated pipetting of each cavity. The actual sealing of the cavitiesis performed at room-temperature by an ultrasonic-based ball pumping process.Finally the cavities are diced. This process implementation uses exclusively low-temperature processes after the cavities have been filled with liquid, which allowsfor the integration of temperature-sensitive fluids, e.g. drugs etc.

Device 1 Device 3Device 2 Device 4

Step 1Step 2

Step 3

Step 4

Liquid Liquid Liquid Liquid

Force &

Ultrasonics

Electrical

Flame-Off

Figure 2.27: Illustration of the wire bond vacuum sealing process. A gold ball is formed by anelectrical discharge, the ball is bonded to the substrate by force and ultrasonic energy applied bythe bond capillary and the wire is sheared of by a horizontal motion of the bond capillary, yieldinga sealed device.

The fabrication of the cavities, shown in Figure 2.27, utilizes standard MEMSprocessing technology and is based on 100 mm silicon and borofloat® substrates.First, the cavities are KOH-etched on the back-side of the silicon substrate usinga SiO2 hardmask. After stripping the SiO2 hardmask, the silicon substrate isanodically bonded to a borofloat® substrate. Access ports are then etched fromthe front-side of the silicon wafer by DRIE. A TiW/Au layer is sputter-depositedand serves as a bond surface for the sealing. The cavity wafer is then filled witha liquid and sealed by ball bumping, as illustrated in detail in Figure 2.27. Awafer-level process could be implemented with the fully automated wire bondingtool used, model ESEC 3100+, as shown in Figure 2.28 a. Even though thebondable area of this tool is limited to 52 × 70 mm2 a full wafer process couldbe implemented by manually moving the wafer on the chuck of the machine. Asdescribed in section 2.1.1, special bumping tools for full wafer applications existand are considered to be most suitable for an industrial use of the proposed sealingtechnology.


a) b)

Figure 2.28: a) Photograph of the wire bonding tool with a 100 mm cavity wafer. b) Cavitiesfilled with red-dyed water, seen from the glass side. The empty cavity was not filled since theaccess holes were insufficiently deep etched. The dimensions of the cavities are 11 × 11 × 0.4 mm3.

The result of the wafer level cavity filling is shown in Figure 2.28 b. Two accessports with a diameter of 20 µm were sufficient to completely fill a cavity withliquid. In Figure 2.29 a, an SEM image of a plugged hole and, for comparison, anon-plugged access port with a diameter of 37 µm is shown. The used free air ballsize of 75 µm proved to be sufficient to reliably place bumps on holes smaller than42 µm in diameter. A SEM image of a cross-section of a sealed access port is shownin Figure 2.29 b. It reveals that a significant amount of gold was pushed inside thehole during the bonding process.

a) b)

Access Port

Gold StudBump

EpoxyMold

Figure 2.29: a) SEM image of two fluidic access ports, with and without a wire-bonded plug.The hole diameter is 37 µm. b) Cross-sectional view of a wire-bonded plug in 30 µm diameterfluid access port. The chip was embedded in a polymer matrix and polished until the access portwas reached.

In order to provide long-term hermeticity measurements, six water-filled andsealed devices were stored at 90 C for two months while the mass of the deviceswas monitored regularly. At that temperature, the internal cavity overpressure was


0.6 bar. The overpressure was calculated in the same manner as for the burst testdescribed in the next paragraph. Figure 2.30 shows that one of the devices leaked,while the other five devices only showed noise from the measurement. The locationof the leak is not known, but it is likely at the plugged port since the gold seal atthis point is 100 times narrower compared to the anodic bond, which is yet anotherpossible leak location. The three possible causes for leaking ports are: (1) bondto port misalignment, (2) no bond between plug and substrate and (3) insufficientamount of gold (Paper 2). Details concerning fabrication and measurements canbe found in Paper 2.

0 10 20 30 40 50 6038

40

42

44

46

48

50

52

Time (days)

Liq

uid

vo

lum

e (

µl)

80 x 30 µm

2 x 35 µm

80 x 30 µm

2 x 35 µm

2 x 30 µm

reference

Figure 2.30: The cavity water volume for six different samples over 54 days of storage at 90 C.One of the samples with two 35 µm diameter ports leaked, while the other five samples had noliquid loss (Paper 2).

2.3.3 Room-temperature wafer-level vacuum sealing

There is a need for low-cost and reliable vacuum encapsulation processes fora wide range of MEMS devices, such as infrared sensors, accelerometers andgyroscopes [119]. For sensitive devices, sealing at room temperature can be vital.In addition, the low temperature can reduce out-gassing from surfaces which inturn will reduce the need for getters, necessary to obtain low vacuum pressures.Hermetic packaging at room temperature is challenging since few bonding methodsyield truly hermetic seals at room temperature. Reported methods include plasmaactivated direct bonding [120] and local heating of sealing structures [121]. However,these methods require certain material systems for the activation to functionor tailor-made and fairly complex sealing structures. Deformation and coldwelding of partly overlapping electroplated gold sealing rings between two wafers


for room-temperature cavity formation and vacuum encapsulation has also beendemonstrated [118] (Paper 11).

Gold Stud

BumpAccess

Port

Coined

Bump

Sealed

Access

Port

To Vacuum

Cavity

Gold

a) b)

Figure 2.31: a) First, a wire bonded gold bump is placed partly overlapping the access port of acavity. (b) Second, the bump is compressed in a vacuum atmosphere, causing plastic deformationand a flow of the bump material into the access port, thereby clogging the port and sealing thecavity.

In order to address the need for reliable vacuum encapsulation processes, thehermetic sealing concept for liquid-filled cavities, described in section 2.3.2, hasbeen adapted for the realization of vacuum cavities. As ball bumping cannotbe performed in vacuum per se, this technique has been combined with a low-temperature deformation of gold bumps, a process called coining, where wirebonded gold bumps are plastically deformed in order to both make the top surfaceflat and to achieve a predetermined bump height. This process was originallyintroduced in order to increase the electrical and mechanical reliability of studbumps used in flip chip packaging [15]. As illustrated in Figure 2.31 a, in ambientpressure, a ball bump is bonded slightly off-centered on an access port that leadsto a vacuum cavity. That way the cavity is not sealed yet and can be evacuated.The cavity is then evacuated and after reaching a desired pressure the ball bumpis coined and thereby the access ports are sealed through the material deformationof the ball bump, as illustrated in Figure 2.31 b.

Figure 2.32 shows the fabrication scheme for the vacuum encapsulation pro-cesses. Similar cavities as described in section 2.3.2 are fabricated for that purpose.Wafer-level ball bumping is performed with slightly off-centered placement as shownin Figure 2.32 a and 2.33 a. The cavity wafer was finally transferred to a substratebonder where the cavities were batch sealed by coining the bumps in a vacuumenvironment. Therefore, an oxidized silicon substrate was placed on top of thecavity wafer in order to ensure a flat and evenly distributed compression of thebumps over the entire wafer area. The wafer stack is placed in the substrate bond


chamber and after pumping to a vacuum pressure of 5 · 10−6 mbar, the wafer stackwas compressed with a total force of 3.5 kN from the bond tool as indicated inFigure 2.32 b. This bond force corresponds to a force per bump of 9 N. The entirecompression process was performed with the bond chucks at room temperature.As indicated in Figure 2.32 c, the pressure difference between the cavity and theambient pressure causes a bending of the silicon membrane.

1. Flame Off

2. Bump Bond

Vacuum

Atmospheric Pressure

3.5 kN

Vacuum chamber

Dummy Si Wafer

b) c)a)

to vacuum pump

Chuck

Figure 2.32: a) 1.) In the wire bonder, an electrical discharge locally melts the gold wire andforms a sphere at the end of the wire. 2.) The gold bump is bonded with an offset in order tonot fully cover and clog the access port. b) A polished Si wafer is placed on the bumps and thestack is placed in a wafer bonder. At a chamber pressure of 10−5 mbar a bond force is applied,pressing the bumps into the holes and hermetically sealing them. c) The difference between thecavity pressure and the ambient pressure causes a bending of the silicon membrane.

Gold Bump

Access Port

Gold

Polymer Matrix

Gold

Silicon

DRIE Hole

Figure 2.33: (a) A gold bump prior to vacuum sealing. The bump has a diameter ofapproximately 95 µm and a height of 50 µm. It is placed with an offset of 35 µm from thecenter of the access port. b) A coined gold bump after the vacuum sealing. The height of thebump is reduced to 15 µm. c) Cross sectional view of a sealed access port. The cross section wasmade by grinding and polishing.

Figure 2.34 shows an optical profilometer measurement of the membranedeflection of a single cavity that is caused by the pressure difference betweenthe cavity and the ambient pressure. For a longer term leak rate evaluation, thedeflection of the membranes suspended over the vacuum cavities was monitored over30 days. These measurements yielded the membrane deflection at the center of themembrane, which is directly proportional to the pressure over the membrane. The


Figure 2.34: Profilometric image of a single vacuum-sealed cavity with 80 access ports (brightspots). The zero-level corresponds to the undeflected substrate surface.

detection limit of this measurement method is approximately 9 · 10−11 mbarl/s.With that method, there was no leak detectable during the measurement period of30 days. A residual gas analysis (RGA) of a sealed cavity with 80 access ports afterthe entire packaging procedure was performed in order to evaluate the vacuum levelinside the cavity. The RGA measurement revealed a vacuum level inside the cavityof 8.2 · 10−4 mbar and an extrapolated leak rate of 2.9 · 10−14 mbarl/s (Paper 11).More details concerning fabrication and characterization can be found in Paper 11.

2.3.4 Wafer-level integration of Shape Memory Alloy wiresShape memory alloys (SMAs), are very attractive actuator materials for microelec-tromechanical system (MEMS) applications, especially when high forces and largedisplacements are desired. At the microscale, the work density of SMA materialsis at least one order of magnitude higher than other actuation mechanisms, suchas electrostatic, piezoelectric and magnetic actuation [122]. Traditionally there aremainly two ways of integrating SMA materials into microsystems. Most commonare sputter deposition and thermal evaporation of thin SMA films directly ontothe microstructure [122]. These methods enable wafer level processing. However,because of difficult deposition control, the process is limited with respect tothe achievable layer thickness and reproducibility of transformation temperaturesand strains [123]. The second approach for the integration of SMA wires intomicrosystems is to use bulk SMA materials. The MEMS structures and the SMAmaterial are first fabricated separately and then combined at device level by a pickand place approach [124]. Bulk SMA materials are commercially available in awide thickness range; at comparably low material cost, but integration on a perdevice level results in high assembly cost. Recently, wafer level heterogeneousintegration processes [125] for bulk SMA sheets using both adhesive [126] andAu-Si eutectic bonding [127] have been presented for the creation of actuators


and microvalves. Also wafer level integration processes for SMA wires have beenpresented for the creation of high performance actuators, using both polymers [128]and Ni-electroplating [129] for attaching the wires to the substrates. However, thesewire integration approaches suffer from a number of problems and disadvantages.Firstly, a dedicated frame is needed to hold the SMA wires in place and placementof the wires in the frame is performed by hand. Secondly the frame with the wiresneeds to be manually aligned to a pre-processed silicon wafer under a microscope(Paper 3).

Wire bonding technology is ideal to replace the manual alignment and at-tachment of the wires in the aforementioned concept. However, as describedin section 2.1.1, standard wire bonding technique is limited to certain materialcombinations in order to realize a reliable weld between the wire and themetallization on the substrate. The hardness of the used wire material has animportant impact on the bondabilty and the reliability of the welding joint. It isknown that material failures, such as cratering, are more likely to occur for hardwire materials [10, 11]. Therefore, standard wire bonding is typically based onwelding soft wire materials to other soft or, in rare cases, to hard metal pad surfaces.Table 2.3 lists the Vickers hardness of standard bond materials and NiTi SMA wires.The excessive Vickers hardness of NiTi, which is one order of magnitude higher ascompared to Au, makes direct wire bonding of NiTi SMA wires not feasible usingtraditional ball/stitch or wedge/wedge bonding techniques.

Table 2.3: Vickers HardnessHV of standard metals used for wire bonding such as gold, aluminumand copper. Platinum, palladium, nickel and silver wires are known to be bondable as well. Wirebonding has not been demonstrated for equiatomic NiTi shape memory alloys (SMA) due to theextreme hardness of the material class.

Material HV [MPa]Au 245 [82]Al 147 [82]Cu 490 [82]Pd 362 − 1030 [82]Pt 392 [82]Ni 981 [82]Ag 245 [82]NiTi (SMA) 2000 − 2300 [130]

A novel and generic method for the integration of very hard and hence non-bondable wire materials has been developed in this thesis work. This approach isdemonstrated with NiTi SMA wires, which are commercially available in a widerange of thicknesses from 25 µm to 500 µm [131]. The proposed method utilizesa conventional and unmodified wire bonding tool. However, the attachment ofthe wire to the substrate is not realized by traditional means of wire bonding (i.e.metal/metal-welding). Instead, the wire is mechanically fixated and clamped bymicromachined silicon structures.


Bond Capillary SMA

Wire

SMA Wire

Chip-Level

SMA WireClamp

Free Air

Ball

a) Anchor Structure b) Clamp Structure

c) SMA Wire Integration

Wafer

Landing

Zone

100 mm Silicon Substrate

Step 2Bond

Capillary

Anchor Clamp

Chip Level

Electrical

Flame

Off

Step 3

Step 1

Figure 2.35: Illustration of the mechanical fixation structures used for anchoring (a) andclamping (b) of a wire. c) The wire is integrated with the help of a regular wire bonding tool.The wire is anchored with the help of the free air ball (FAB) at one end and then fixated by aclamp structure at the other end.

Figure 2.35 illustrates the novel wire integration scheme. The free air ball (FAB)acts as an anchor that is attached to a deep- and underetched silicon structureusing a wire bonding tool. As illustrated in Figure 2.35 a, the anchoring structureconsists of two features, which are a landing zone and the actual tapered fixationstructure. The bond tool lowers the free air ball above the landing zone until ittouches the ground, it then moves laterally towards the tapered fixation structure(Figure 2.35 c, step 1). This fixation structure self-centers and fixates the freeair ball due to its in-plane tapered and underetched features. The tool movesthen towards the second attachment position (Figure 2.35 c, step 2) where thewire is fixated by a clamp structure, which also is a deep- and underetched siliconstructure, as illustrated in Figure 2.35 b. The wire bonding tool pushes the wirewith a defined force into the clamp without deforming the wire, as indicated inFigure 2.35 c, step 3. Finally, the wire is truncated by applying a high force andultrasonic energy. The attachment of the wire to the substrates with the help of theanchor and clamp structures is purely mechanical. This novel attachment techniqueis performed in room-temperature conditions, which is essential in order not totrigger the SMA effect for applications using prestrained SMA wires (Paper 3).


SMA wire

Clamp

SMA

wire

Free Air Ball

Landing Zone

a) b)

Figure 2.36: a) SEM image of the anchor structure with an anchored SMA wire. The inset showsa magnified view on the tapered design of the anchor. b) SEM image of a clamping structurewith a clamped SMA wire. The inset is a tilted view on the deep etched cantilevers of the clampstructures.

A proof-of-concept of the wire bonder assisted integration of NiTi SMA wiresto 100 mm Si substrates was successfully demonstrated. Anchoring and clampingstructures, shown in Figure 2.36, for the fixation of SMA wires structures have beenfabricated by a dedicated DRIE process. Even though the wire has been integratedwith the help of a manual wire bonder, an excellent placement accuracy could beachieved. The in-plane placement accuracy of the wires on a wafer is within 14 µmover a length of 75 mm and the mechanical fixation strength of the anchoring andclamping structures is higher than the ultimate strength of the NiTi wire.

T = 70°C

T = 90°C20 mm

a)

b)

c)

Figure 2.37: Actuation demonstrator: a) drawing of a cross-section, the red dashed outlinerepresents the chip in a hot state. b) image of an slightly actuated device on a hotplate with atemperature of 70 C. c) device with increased actuation at 90 C (Paper 3).


In order to verify the mechanical stability of the presented wire fixationapproach, two 75 mm long SMA wires have been integrated in parallel on a siliconchip with a size of 2 mm × 100 mm. The energy input is provided indirectly by ahotplate on which the actuator is fixed on one side to enhance the thermal contact.Figure 2.37 a illustrates the cross-section of the actuator both in actuated and idlepositions. Figure 2.37 b depicts the actuator in a semi and Figure 2.37 c in fullyactuated state. This demonstrates that both SMA wire fixation elements withstandthe forces that are generated by the SMA wires.

This wire integration approach is generic and has the potential to be appliednot only to SMAs for actuator applications but also to other non-bondable wirematerials such as steel or titanium, and even optical fibers. The presentedmanual integration approach can potentially be implemented on fully automatedwire bonding tools in order to increase reliability and throughput. With highlyefficient conventional wire bonding tools broadly available, this novel mechanicalfixation approach lowers the barriers for a wider use of unconventional wirematerials in MEMS applications. Detailed information concerning fabrication andcharacterization of the anchoring and clamping structures can be found in Paper 3.

2.4 Discussion and outlook

The results that are presented in this chapter demonstrate that the integration ofbulk wire materials is feasible for a multitude of applications. The integration ofmicrowires proves to be an attractive alternative to conventional plating processesthat suffer from limited material choice, difficult controllability, long process timesand issues connected to void formation. Conventional plating techniques usedin IC and MEMS processing is not suitable for applications that require highlyfunctionalized metal alloys with a precise material composition and crystallinestructure (e.g. SMA). However, these highly specialized materials are besides agreat variety of inherently void-free standard bulk wire materials, including high-purity metals and alloys, commercially available.

This work follows the ongoing paradigm shift that is moving wire bondingtechnology from the back-end to the front-end in MEMS and IC fabrication. Itshows that wire bonding must not merely serve the purpose of creating electricalinterconnections but that this technology can be utilized very efficiently in amultitude of novel and existing applications.

Chapter 3

3D Heterogeneous IntegrationBased on Layer Transfer

This chapter deals with two 3D heterogenous integration approaches that arebased on layer transfer techniques. First, a brief introduction to 3D heterogenousintegration techniques within the scope of this thesis is given. In the second section,a via-last integration process for the fabrication of bolometer arrays for thermalimaging is presented. The third section deals with a via-first integration processfor the fabrication of pressure sensors based on graphene diaphragms.

3.1 Introduction

A system on a chip (SoC) is a semiconductor-based device where differentfunctionalities are embedded on a single chip. This integration approach, alsoknown as ”monolithic integration”, combines different functions such as digital,analog, mixed-signal, RF, actuators and sensors that are based on differentfabrication technologies. SoCs are typically characterized by high performance,very compact footprints and relatively low cost. However, this approach suffersfrom a limited design flexibility and, due to constraints in terms of temperaturebudget, contamination and a very limited choice of compatible materials thatcan be used in CMOS processing. This is in particular a disadvantage for SoCswith embedded actuator and sensor systems, that require often highly specializedmaterials including germanium, III–V materials, piezoelectric materials, shapememory alloys (SMAs) or layers of monocrystalline silicon [125].

Heterogeneous integration technologies combine the advantages of monolithicand chip-level hybrid integration technologies and allow the manufacturing of SoCsthat cannot be fabricated by conventional micromanufacturing techniques. Layer-based heterogeneous 3D integration on chip and wafer level for MEMS and NEMScan be categorized in:

43

44 CHAPTER 3. 3D INTEGRATION BASED ON LAYER TRANSFER

1. Via-first (or anchor-first) processes, as illustrated in Figure 3.1 a

2. Via-last (or anchor-last) processes, as illustrated in Figure 3.1 b

In heterogeneous integration using via-first processes, the vias establishingmechanical and electrical contacts between components on the different substratesare defined during the bonding process. Conversely, in heterogeneous integrationusing via-last processes the components are first bonded to each other, then thevias establishing mechanical and electrical contacts between the components on thedifferent substrates are defined.

b) Via-Last Process

Donor Wafer

Donor Wafer

Device Material

Via

Bond Layer

a) b) c)

d) e) f) MEMS/NEMS device

a) Via-First Process

Donor Wafer

CMOS Wafer

Pre-fabricated

devices with vias

a) b) c)

Donor Wafer

Donor Wafer

MEMS/NEMS device

CMOS Wafer

CMOS Wafer

CMOS Wafer

CMOS Wafer

CMOS Wafer

CMOS Wafer

CMOS Wafer

CMOS Wafer

Figure 3.1: Example of heterogeneous 3D integration using a (a) via-first and (b) via-last process.

Both, via-first and via-last heterogeneous 3D integration approaches areused in volume-manufactured commercially available devices. Very mature via-first heterogeneous 3D integration platforms are currently used e.g. for themanufacturing of gyroscopes by InvenSense, Inc (USA). Here, parts of the MEMSsensor package are pre-fabricated together on one wafer and subsequently bonded

3.1. VIA-LAST INTEGRATION OF MONOCRYSTALLINE SiGe 45

to the CMOS IC wafer [125, 132, 133]. Other via-last implementation include micromirror arrays [134] and atomic force microscope (AFM) tip arrays [135].

A commercially available via-last heterogeneous 3D integration platform,suitable for the fabrication of IC-integrated MEMS devices such as inertial sensors,has been presented by semiconductor foundry TSMC, Ltd (Taiwan) [136]. Otherdemonstrations of via-last heterogeneous integration technologies for MEMS andNEMS include infrared bolometer arrays [137–143], arrays of tilting and piston-typemicro-mirrors [143–147], micro-pirani vacuum gauges [148], RF MEMS [136, 149]and other devices [125]. For most of these applications, adhesive wafer bonding hasbeen used for joining MEMS and IC wafers.

Wafer level heterogeneous 3D integration approaches are attractive and cost-efficient if the components on both wafers have a similar manufacturing yieldand more importantly identical wafer sizes. For applications with a substantialdifference of the size of the dies or wafers, device distribution processes such aspick-and-place or modified heterogeneous integration schemes are used. Devicedistribution processes have been used for a variety of applications [125] and includewafer-to-wafer selective component distribution known as microdevice distribution(MD) technology [150–153], chip-to-wafer pick-and-place technologies [154, 155],the use of expandable handle substrates [156, 157] and chip-to-wafer self-assemblytechniques [83, 84, 158–160].

3.2 Via-last integration of monocrystalline SiGe forinfrared bolometers

The detection of infrared (IR) radiation is an integral part of a vast numberof applications in fields ranging from medical, industrial, consumer, security tospace. Detectors for IR radiation are categorized as either thermal or photondetection principles and are based on a variety of physical effects and detectormaterials. Photon detectors are typically made of semiconductor materials and arecharacterized by very fast response times and high wavelength selectivity. However,photon detectors require typically cryogenic cooling for their operation. Thermaldetectors are based on materials that absorb IR radiation and thereby change theirphysical properties in a measurable way. These detectors can be operated at roomtemperature and have less wavelength selectivity, however, exhibit comparativelyslow response times [161, 162].

For thermal imaging or IR thermography, light is coupled to 2D arrays of IRdetectors where each pixel corresponds to a thermal detector. These thermalimaging sensors are used in applications such as industrial process control [163–165], predictive maintenance for mechanical and electrical equipment [163], buildingmaintenance [163], surveillance [163], person counting and tracking [163, 166],firefighting [163] and automotive night-vision [139, 163, 167] (Paper 10). Dueto the comparably high cost and complexity of cryogenically cooled detectors,the majority of today’s commercially available IR imaging systems are based on


uncooled bolometer focal plane array (FPA) detectors. The detection principle ofbolometers is a change in the electrical conductivity of an IR-absorbing thermistormaterial. The change of conductivity of each thermistor pixel is measured anddigitalized by CMOS-based read-out integrated circuits (ROICs).

Commercially available uncooled IR bolometer arrays have resolutions of upto 640 × 480 pixels and pixel pitches down to 17 µm [168]. The thermistormaterial of these bolometer arrays consist of either vanadium oxide (VOx) [169](e.g. Flir Systems Inc., USA and BAE Systems Inc., UK) or amorphous silicon (a-Si) [170] (e.g. Ulis, France). In both cases, the bolometer material is monolithicallyintegrated to CMOS-based ROIC wafers. The direct deposition of thermistormaterial on CMOS wafers has a limited temperature budget of approximately400 − 450 C (Paper 10). A variety of attractive thermistor materials improvedcharacteristics exist but require elevated deposition temperatures that do not allowa direct deposition and monolithic CMOS integration.

3.2.1 Wafer-level integration of monocrystalline SiGeIn this work, Si/SiGe quantum well material is used as bolometer thermistor.SiGe is an attractive thermistor material due to its high temperature coefficientof electrical resistance (TCR) and noise levels being several orders of magnitudelower than for VOx and a-Si [171]. However, this material requires elevateddeposition temperatures that do not allow for a direct deposition and hence amonolithic integration on CMOS circuitry. The Si/SiGe quantum well material isgrown epitaxially on silicon-on-insulator (SOI) wafers at temperatures above 600 C(Paper 18). The temperature coefficient of resistance of this material is controlledby the concentration of Ge present in the SiGe quantum well layers and can reachvalues of well above −3 %/K [171]. A high TCR of the thermistor material isdesired to obtain high bolometer sensitivities and low noise levels in the thermistormaterial result in better signal-to-noise ratios [138, 140] (Paper 10).

A simplified overview of the very large scale heterogeneous via-last integrationprocess for fabricating the Si/SiGe bolometer structures is depicted in Figure 3.2.As indicated in Figure 3.2 a, the wafer containing the thermistor material and theread-out wafer have been manufactured separately and are fused in a full-waferadhesive bonding procedure (Figure 3.2 a). The handle wafer, including the buriedoxide layer is then removed by grinding and etching (Figure 3.2 c). As illustrated inFigure 3.2 d, the thermistor pixels are then defined by a lithography and subsequentetch. Via holes that serve as molds for the subsequent via deposition are thendefined in the bond polymer (Figure 3.2 e). As a final step the sacrificial bondpolymer is removed and the thermistor pixels are released (Figure 3.2 f).


Handle Wafer

Read-Out Wafer

Handle Wafer

Thermistor Material

Bolometer Via

Adhesive Bondpolymer

a) b) c)

d) e) f)

Read-Out Wafer Read-Out Wafer

Read-Out Wafer Read-Out Wafer Read-Out Wafer

Figure 3.2: Via-last integration for uncooled infrared bolometer arrays: a) fabrication of ROICwafer and separate handle wafer with thermistor material b) adhesive wafer bonding c) thinningof handle wafer d) bolometer definition e) via formation f) sacrificial etching of adhesive.

3.2.2 Uncooled infrared bolometer designWithin this work uncooled IR bolometer FPAs with pixel pitches down to 17 µmhave been manufactured and characterized. As illustrated in Figure 3.3 a and b,each bolometer pixel consist of a free-standing thermistor membrane that isthermally insulated from ROIC substrate and its surroundings. The two electricalinterconnections from the thermistor to the ROIC, i.e. leg structures, are designedin way to minimize thermal conductivity. The leg structures are long with asmall cross-sectional area and consist of a very thin metallization for the electricalconnection and a structural material with lower thermal conductivity as comparedto the metal. The non-conductive structural material serves the purpose of a propermechanical support of the thermistor pixel. The leg structures lead to via structuresthat are the vertical part of the electrical interconnect. Besides the purpose of anelectrical interconnect, the vias elevate the bolometer pixel by creating a stand-offbetween the thermistor membrane and the substrate, which is of importance toachieve a sufficient thermal insulation.


a) b)

Thermistor

Via

Leg

structure

ROIC

Current path

p+ Si

p+ Si

QW

IR

R

Figure 3.3: a) Schematic view on a bolometer pixel. b) Cross-sectional view on a bolometerpixel. Incoming IR radiation is absorbed by the thermistor. The resulting change in resistance ismeasured by a read-out circuit.

3.2.3 Bolometer via structuresAn electroless nickel plating process, which simplifies the integration process ascompared to electroplated vias, has been developed. Electroplated vias require aseed-layer that is electrically connected to the plating setup. For the fabrication ofbolometer structures, the pads on the read-out wafers that serve as seed-layer haveto be short-circuited for that purpose. In a subsequent step, the short-circuitedpads have to be disconnected by a etching step [137]. This approach requiresadditional demanding process steps that can be difficult to implement. In thiswork, a new electroless plating process, which does not require interconnected seed-layers, is investigated. This plating process uses plasma-activation of the platingseed surfaces and was shown to be stable and yields plating vias with reducedresistances.

a) b) c)

d) e)

Substrate Si3N4Seed

Au/Ni

Polymer TiWVia Ni

Figure 3.4: Fabrication scheme for selective plating of nickel vias on Au and Ni seed-layers.


The fabrication of Kelvin test structures is schematically depicted in Figure 3.4and is based on an insulated substrate (e.g. oxidized silicon). The seed-layer(either Ni or Au) is deposited and structured with the help of a lift-off process. Athermosetting polymer is subsequently spun-on and hard-cured. A silicon nitridelayer acts as a hardmask for the etch of the via mold (Figure 3.4 a). Thesilicon nitride layer is structured by stepper lithography and a standard dry etch.The polymer of the via mold was anisotropically etched in an oxygen plasma(Figure 3.4 b). For Au seed-layers, a surface-activation takes part in a mildoxygen plasma. For Ni seed-layers, a wet acidic pre-treatment was performedin order to remove the native oxide of the Ni seed-layer. The plating processwas conducted with a hydrophosphite-based electroless Ni plating solution, asindicated in Figure 3.4 c. The top-metallization layer was deposited, as shown inFigure 3.4 d, by sputtering with a prior sputter etch without breaking the vacuumin order to remove the native oxide from the top-surface of the nickel via. Afinal photolithography and a dry etch forms the structures of the top-metallization(Figure 3.4 d). In order to be able to electrically probe both the seed-layer andthe top-metallization, the polymer was selectively removed by a second anisotropicplasma etch (Figure 3.4 e) (Paper 16).

Ni viaMetallization

Seed-layer

Figure 3.5: SEM images of the Kelvin test structures. The close-up shows the gold seed-layer,the square-shaped nickel via and the TiW-metallization on top of the polymer (Paper 16).

The electrical characterization of the plated Ni vias was performed with thehelp of Kelvin test structures, depicted in Figure 3.5, a 4-point probe station anda digital multimeter. The electrical charcterization was focused on square-shaped3 µm-wide vias with a height of 1.5 µm. The total resistance of the vias on gold seed-layers showed very low values (0.45 ± 0.13 Ω (3σ)), which are about seven timeslower as compared to similarly fabricated vias on nickel seed-layers (3.02 ± 1.81 Ω


(3σ)). Also the variance of the measured total resistances was lower for vias ongold seed-layers.

a) b)

c) d)

Figure 3.6: a) Free-etched 5×5 via test array (1.5 µm via diameter on Ni seed-layer) b) Free-etched via with a minimum achievable diameter of approximately 0.5 µm, slightly overplated on Niseed-layer c) Free-etched 5×5 via test array (1.5 µm via diameter on Au seed-layer) d) Free-etchedvia with a minimum achievable diameter of approximately 1.5 µm, on Au seed-layer

As depicted in Figure 3.6, the morphology of plated nickel structures varies,depending to the used seed-layer material. Vias, which were grown on gold seed-layers, as depicted in Figure 3.6 c and d, have a rougher surface topology than vias,which were grown on nickel seed-layers, as shown in Figure 3.6 a and b. The platingrate was in general higher and less controlled close to the edge of the structures,that were plated on gold seed-layers. This effect has no impact on the electricalfunctionality of the via but causes problems for small via pitches, where vias can beshort-circuited, as shown in Figure 3.6 c. The shape of the fabricated vias, whethersquare or circular, had in general no impact on the electrical performance and thematerial morphology. More information concerning the bolometer via experimentscan be found in Paper 16 and Paper 18.


3.2.4 Bolometer leg structures

As indicated in section 3.2.2, the bolometer leg structures need to fulfill threefunctions: an electrical connection of the thermistor to the read-out circuit, athermal decoupling of the thermistor from the surrounding and a structural supportof the free-standing bolometer pixel. Materials with low electrical resistivity(e.g. metals) are excellent thermal conductors as the same mobile electrons whichparticipate in electrical conduction also take part in the transfer of heat. Therefore,the bolometer legs consist of two materials, a conductive material (TiW) and non-conductive structural material (Si3N4) as mechanical support for the bolometerpixel. These two materials have different electrical, mechanical and thermalproperties. Hence, the CTE mismatch of these two materials causes a mechanicaldeformation of the bolometer legs. Depending on the CTE αE , Young’s Modulus Eand the thickness t of the material the deformation results either in an upward ordownward bending, as illustrated in Figure 3.7 a. A common workaround in orderto prevent bending is to use symmetric material stacks [172] (t1=t3), as indicatedin Figure 3.7 b.

Si3N4: α1, E1, t1

TiW: α2, E2, t2

Si3N4: α1, E1, t1

TiW: α2, E2, t2

Si3N4: α1, E1, t3

a) b)

Figure 3.7: Simplified model of bolometer legs with a) two layers and b) three layers. Impacton the bending have the mechanical properties of the used materials (Coefficient of ThermalExpansion αE , Young’s Modulus E and material thickness t).

Figure 3.8: Tilted SEM image of bolometer leg structures consisting of symmetric triple stacksthat bend downwards and thereby create electrical and thermal short-circuits.


In the bolometer fabrication, the lower Si3N4 layer of the leg stack was initiallydeposited by PECVD at 300 C on top of the adhesive bond polymer. Subsequently,the TiW layer was sputter-deposited on the lower Si3N4 layer before the upper Si3N4layer was deposited on the TiW layer. Even though identical Si3N4 layer thicknesseshave been deposited, the released leg structures showed stress-induced bendingdownwards. Especially a bending downwards cannot be tolerated for the risk ofelectrical and/or thermal short-circuits, as shown in Figure 3.8. The bending of theleg structures is caused by a combination of stresses induced by different depositiontemperatures of the leg materials and internal stresses of the bond-adhesive onwhich the leg stack is deposited (Paper 9).

In order to address this problem, asymmetric triple-stacks with slightly thickerupper Si3N4 layers were fabricated. By changing t1 the bending of the bolometerlegs could be tuned. That way, straight legs or, as a precaution, legs that bendslightly upwards could be manufactured, as depicted in Figure 3.9 b. Besidesother measures during the leg fabrication (see Paper 9 for details), all depositiontemperatures were harmonized to 100 C.

a) b)

Figure 3.9: Tilted SEM images of bolometer leg test structures. a) Symmetric triple stacks benddownwards b) Asymmetric triple stacks bend upwards.

a) b) c)

Figure 3.10: SEM images of bolometer leg structures: a) Leg structures consisting of symmetrictriple stacks bend downwards. b)-d) Straight leg structures consisting of optimized asymmetric(t1=200 nm, t2=50 nm, t3=150 nm) triple stacks. The legs are 500 − 575 nm wide and 17 − 34 µmlong.

3.2. VIA-FIRST INTEGRATION OF GRAPHENE MONOLAYERS 53

Shown in Figure 3.10 a - c are uncooled IR bolometer FPAs with pixel pitchesdown to 17 µm and sub-micron wide bolometer leg structures with excellentelectrical, thermal and mechanical properties. More details concerning fabricationand characterization of the bolometer structures can be found in Paper 9 and 10.

3.3 Via-first integration of graphene monolayers forpressure sensors

Most macroscopic and micromachined pressure sensors convert pressure to a motionof a mechanical element, which can be transduced to an electrical signal. Thetransducer elements are typically based on piezoresistive, capacitve, optical andresonance effects. In addition, vacuum pressure sensors measure either the thermalconductivity of the gas (Pirani gauge) or the rate of ionization of the gas (Ionizationgauge), which are both directly proportional to the pressure. Micromachinedpressure sensors are either based on the Pirani gauge principle or more commonlyon the deflection of a diaphragm due to an applied pressure (p1), as illustrated inFigure 3.11 [173]. With respect to the used pressure reference (p2), three differenttypes of sensors exist:

• Absolute pressure sensor: Measurement relative to static vacuum pressure p2.

• Gauge pressure sensor: Measurement relative to ambient atmospheric pres-sure p2.

• Differential pressure sensor: Measurement of the pressure difference betweentwo varying pressures p1 and p2.

p1 p2

Transducer

Diaphragm

p1 = p2 p1 > p2

Figure 3.11: Concept of a diaphragm-based pressure sensor. A pressure difference (p1, p2)causes a deflection of the diaphragm. The deflection is proportional to the pressure difference andcan be measured with the help of a transducer.


Micromachined diaphragms are fabricated either by bulk micromachined mono-crystalline silicon or surface micromachined polycrystalline and amorphous thinfilms including polysilicon, metals, and silicon nitride. The actual sensing elementcan be integrated in the diaphragm material, e.g. ion implantation createspiezoresistive Si strain gauges directly in Si diaphragms, or are externally situated,e.g. capacitive parallel plate pressure sensors or optical interferometric sensors [173].All micromachined diaphragm-based pressure sensors consist of a structural element(i.e. diaphragm) and one or multiple transducer elements that require additionalprocess steps or external structures and components for their function. Thiswork deals with a micromachined gauge-type pressure sensor that consists ofa graphene diaphragm that fulfills both the function as structural element andelectromechanical transducer at the same time.

3.3.1 Chip-level integration of graphene monolayersMonolayer graphene exhibits exceptional electric and mechanical properties, includ-ing high carrier mobility [174, 175], high Young’s modulus of about 1 TPa [176],stretchability of up to approximately 20% [177], strong adhesion to silicon dioxidesurfaces [178] and near impermeability for gases, including helium [179]. Therfore,monolayer graphene is a very promising material for various applications (Paper 7).

MEMS Chip

a) b) c)

Pad Cavity

d) e) f)

Copper

Graphene Polymer

Copper

Graphene PolymerGraphene

SiO2

MEMS Chip MEMS Chip

Figure 3.12: Via-first integration for graphene-based pressure sensors: a) A monolayer ofgraphene .

Single- and few-layer graphene is fabricated epitaxially by chemical vapourdeposition (CVD) of hydrocarbons on metal substrates or by thermal decompositionof SiC [180]. CVD-based Graphene is typically grown at temperatures between750 − 1000 C [181] and is incompatible with CMOS processing. Therefore,techniques for the transfer of commercially available CVD monolayer graphene filmson copper foils are being explored, as indicated in Figure 3.12 [182–186]. For thelayer transfer, a polymer is spin-coated on the graphene film (Figure 3.12 b) in orderto act as a mediator between the initial and the final substrate. Subsequently, the

3.3. VIA-FIRST INTEGRATION OF GRAPHENE MONOLAYERS 55

copper substrate is stripped by wet etching, as illustrated in Figure 3.12 c. Aftera wet cleaning procedure, the graphene is brought into contact with the silicondioxide surface of the cavity chip of the pressure sensor (Figure 3.12 d/e). Thebond mechanism is based on van der Waals force but the exact mechanism thatcauses the extraordinary strong adhesion of monolayer graphene to silicon dioxideis not entirely understood yet [178]. The polymer is then stripped and the graphenelayer is patterned by a lithography and a plasma etch (Figure 3.12 f) (Paper 7).

3.3.2 Graphene-based pressure sensorThe graphene-based pressure sensor is depicted in Figure 3.13 and consists of fourmetal pads intended for a 4-wire resistance measurement of the graphene membranethat is suspended over a rectangular cavity. The sealing of the cavity with grapheneis performed at ambient atmospheric pressure and hence creates a gauge-typepressure sensor. A pressure difference between the pressure in the cavity and theoutside pressure causes a deflection of the graphene diaphragm. Mechanical strainin graphene changes the electronic band structure [187] creating a piezoresistiveeffect. While graphene has been used as a piezoresistive strain gauge on siliconnitride [188] and polymer membranes [189], it is feasible to use the graphene forboth diaphragm and electromechanical transduction simultaneously.

GoldGraphene

Silicon

Dioxide

Silicon

Cavity

Wire Bond

a) b)

Figure 3.13: a) The graphene based pressure sensor consists of four gold metal pads on whichthe graphene monolayer is suspended over a rectangular cavity with an area of 3 × 80 µm2 and adepth of 650 nm b) SEM image of the packaged graphene diaphragm pressure sensor.

The pressure sensor chip is mounted into a ceramic package with open cavity andinterconnected by wire bonding, as depicted in Figure 3.13 b. For the evaluation, thepackage was placed in a vacuum chamber with electrical feed-throughs for the 4-wireresistance measurement. The devices show typical graphene field effect transistor-like behavior. Pressure dependent measurements show that the suspended devicesfunction as pressure sensors. The sensors do not require a strain gauge and shouldbe scalable aggressively in size. Finally, the design and fabrication process is


mainly compatible with silicon CMOS technology, making it relevant for futureindustrial applications. Detailed information on fabrication and characterization ofthe pressure sensor can be found in Paper 7.


Novel materials, such as SiGe and Graphene, are very attractive due to theirhigh-performance and/or unique characteristics. However, the deposition of thesematerials takes part at temperatures far above 400 C and is therefore incompatiblewith standard IC manufacturing or is for some cases simply technically not feasible.The results that are presented in this chapter show that the integration based onlayer transfer is an effective approach in order to be able to make use of non-standardmaterials. A separate manufacturing of these materials and an integration on pre-manufactured devices is a powerful method for the realization of novel sensors andactuators.

Chapter 4

3D Free-Form Patterning of Silicon

In this chapter a novel additive fabrication method for layer-by-layer printing of 3Dsilicon micro- and nanostructures is described. This manufacturing method is basedon alternating steps of chemical vapor deposition of silicon and local implantation ofgallium (Ga+) ions by focused ion beam (FIB) writing and a final selective releaseetch of the non-implanted silicon.

4.1 Introduction

Engineers and designers have been using 3D printers for more than a decade,mostly to build prototypes quickly and cheaply before they embark on the expensivebusiness of tooling up a factory to produce in high volume. As 3D printers have veryrecently become more capable and able to work with a broader range of materials,the machines are increasingly being used to make final products. Using 3D printersas production tools has become known in industry as ”additive manufacturing”,in contrast to ”subtractive” methods as cutting, drilling and milling. Differentbase technologies for 3D printings exist, including laser sintering, fused filamentfabrication, extrusion modeling, stereolithography and laminated object modeling.Each technology is typically optimized for a certain material class, includingproduction-grade plastics, ceramics and metals. Various 3D printers in differentprice classes ranging from consumer to professional production tools are availablefrom different suppliers.

Existing additive layer-by-layer manufacturing techniques include stereolithog-raphy [190, 191], solid ground curing [190], selective laser sintering [190, 192],3D inkjet printing [190], fused deposition modeling [190, 192–201] and laminatedobject modeling [190, 202, 203]. In direct laser writing, solid ground curing andstereolithography 3D, 3D polymer structures are fabricated by locally exposing aphotosensitive polymer to light, which allows subsequent selective dissolution ofthe polymer [190, 191, 204–206]. In 3D inkjet printing and similar techniques,3D structures are formed by printing functional inks, often in combination with

57

58 CHAPTER 4. 3D FREE-FORM PATTERNING OF SILICON

supporting sacrificial inks that are subsequently selectively dissolved [190, 192].Typical materials used in 3D inkjet printing include polymers, waxes and inksfilled with e.g. metal, carbon or ceramics. Laser-beam [195–197], focused ion-beam(FIB) [198–200] electron-beam [198] and proton-beam [201] assisted depositionare other techniques for additive fabrication of 3D structures. Focused ion-beam,electron-beam and proton-beam assisted deposition methods can achieve structuraldimensions as small as a couple of tens of nm. However, the fabrication ofsuspended Si structures has not been shown with these techniques. In [202, 207]methods for the layer-by-layer fabrication of 3D polycrystalline Si structures withdimensions below 1 µm using conventional semiconductor manufacturing processeshave been demonstrated. The applied processes are combinations of polycrystallineSi deposition, SiO2 deposition, photolithography, reactive ion etching, chemical-mechanical polishing (CMP) and selective etching of the sacrificial layer. Theseapproaches require a large number of different processing and photolithographysteps that cannot be easily automated. Transfer printing of pre-patterned Simembranes (laminated object modeling) is another approach to realize 3D Sistructures with dimensions in the micrometer-range [203, 208]. It is however difficultto efficiently automate these processes, and to achieve sub-micrometer alignmentaccuracies during lamination of the pre-patterned membranes (Paper 5).

Silicon (Si) is a very attractive material for micro- and nanoscale devices dueto its excellent mechanical, optical and electrical properties [68]. ConventionalSi machining techniques, including lithography and Si etching, allow cost-efficientimplementation of simple suspended three dimensional Si structures. To implementmore complex 3D Si structures, elaborate process schemes involving a multitudeof different processes are required. The possibility for additive layer-by-layerfabrication of arbitrarily shaped 3D Si structures could potentially provide a wealthof opportunities for new types of nanophotonics, nano- and microelectromechanicaldevices.

4.2 3D free-form patterning of silicon by ion implantation,silicon deposition, and selective silicon etching

A novel additive fabrication method for the fabrication of 3D silicon micro- andnanostructures has been developed. An iterative process of defining a pattern withimplanted gallium ions (Ga+) in a Si layer using FIB writing (Figure 4.1, steps1 and 3) was used. This was followed by chemical vapor deposition of a Si layer(Figure 4.1, step 2) and pattern definition in the deposited Si layer using FIBwriting. This process is repeated for as many layers as desired to define the Sistructures. A final wet etch releases the structures.

In order to estimate the required parameters for the ion implantation and Silayer thicknesses, a simulation of the Ga+ ions implantation into Si using the TRIMcode [209] was performed. For successful layer-by-layer patterning, the thicknessof the deposited layers must match the implantation depth of the Ga+ ions. If

4.2. 3D FREE-FORM PATTERNING OF SILICON 59

KOH

Wet EtchingSEM

e-

Ga

+FIB

Alignment &

Inspection

Ion

Impl

anta

tion

SEM

e-

Ga

+FIB

Alignment &

Inspection

Ion

Impl

anta

tion

CVD

Silicon Deposition

Si S

ubst

rate

Step 1: Implantation

n

:

3

2

1

0

1

0

10

n

:

3

2

1

0

Step 2: Si Deposition Step 3: Implantation Step 4: Free Etch

Final 3D Structure

RepeatStep 2 & 3

Figure 4.1: The process scheme for 3D-patterning of arbitrarily shaped Si micro- andnanostructures, using focused ion beam writing, Si deposition, and selective Si etching in KOH(Paper 5).

the deposited layer is too thin, the Ga+ ions will penetrate through the layer andimplant the layer below. Figure 4.2 shows a TRIM simulation of the implantationof an area dose of 10 pC/µm2 of Ga+ ions into Si, at ion energies in the range from10 − 50 keV. The thickness of the layer that reaches a Ga+ dopant concentrationabove 2.2 · 1019 cm−3, the threshold required for etch selectivity in KOH [210],ranges from 29 nm at 10 keV to 85 nm at 50 keV. At 30 keV, the resulting Silayer thickness in which the critical implantation dose is exceeded is about 60 nm,as depicted in Figure 4.2. Furthermore, the simulation suggests that the criticalimplantation dose is not reached in a few nanometre thick layer near the Si surface(Paper 6).

0 20 40 60 80 1001018

1020

1022

10 20 30 40 50

Implantation depth [nm]

Dop

ant c

once

ntra

tion

[cm−3

] +TRIM simulation (Ga energy in keV)Critical dopant concentration

Figure 4.2: Simulation of the implantation of an area dose of 10 pC/µm2 of Ga+ ions into Si,at ion energies in the range from 10 − 50 keV (Paper 6).


In the ion implantation steps, an area dose of 10 pC/µm2 of Ga+ ions wasused, at an acceleration voltage of 30 kV, using a Nova 600 NanoLab from FEI (theNetherlands). In the Si deposition, the layers were grown from a disilane (Si2H6)precursor at a temperature of 635 C, using an Epsilon 2000 single wafer epitaxytool from ASM International N.V. (the Netherlands). After the final implantation,the wafers were treated with a rapid thermal anneal in an argon atmosphere at650 C. The structures were formed by a final etch in KOH. First, a 3 s dip in HFwas done to remove the native silicon oxide, and then the wafers were etched in atroom temperature. Finally, the wafers were cleaned and dried (Paper 6).

b)

20 μm

a)

Figure 4.3: SEM image of 2-layer structures, fabricated by two Ga+ ion implantation steps, andone Si deposition step, followed by a final KOH release etch (Paper 5).

Layer 1

Layer 2

Layer 3

Substratea)

33 nm

65 nm

130 nm

b)

2 µm 300 nm

Figure 4.4: a) SEM image of 3-layer structures, fabricated by three Ga+ ion implantation steps,and two Si deposition steps, followed by a final KOH release etch. b) SEM image of lines of widthsdown to 33 nm, patterned in a deposited Si layer (Paper 5).

Based on that approach, Si structures consisting of two and three layers as wellas Si structures that determine the maximal resolution of the ion implantation,were fabricated. It has been shown viable to fabricate 2-layer structures, asdepicted in Figure 4.3 a, including suspended beams, shown in Figure 4.3 b. 3-layer structures are depicted in Figure 4.4 a, and line width test structures are

4.2. 3D FREE-FORM PATTERNING OF SILICON 61

shown in Figure 4.4 b. With used set of parameters for the ion implantation andthe Si deposition patterned lines with dimensions down to 33 nm were fabricated.

100 nm Intrinsic Si

Implanted Si

Deposited Si

Pt layer

Si wafer

a) c)

Deposited Si

Si wafer

Pt layerSuspended

beam layer67 nm 37 nm

44 nm

b)

Figure 4.5: TEM cross sections at: a) the edge of the deposited and implanted beam layer; b)the edge of platform implantation c) the suspended deposited and implanted beam layer (Paper 5)

.

5 nm

10 nm 2 nm-1

a) b)

Original

wafer

surface

b c)

Figure 4.6: a) A TEM image of the cross section of the layer stack at the edge of the platformimplantation. b) An enlarged view of the interface between the original wafer surface and thedeposited and implanted layer. c) FFT analysis of a) (Paper 5).

Figure 4.5 shows a SEM image of a sample that has been prepared fortransmission electron microscope (TEM) imaging. The images depict a layer stackalong a suspended beam. The three Si layers visible in Figure 4.5 a are, frombottom to top, the intrinsic Si of the substrate, the implanted platform layer,and the grown and implanted beam layer. The platinum (Pt) protective layerwas deposited locally via a combination of electron beam and ion beam induceddeposition, during the TEM lamella preparation. By comparing, in Figure 4.5 a,the surface level of the implanted platform region on the left to the level of theoriginal wafer surface protected under the deposited layer on the right, we find


that no more than a few nm of implanted silicon is removed during the KOH etch.Considering that 350 nm of non-implanted silicon is removed in the same etch step,we observe an etch selectivity in our process of at least the order of 100:1 betweenimplanted and non-implanted regions. A slight under-etch of the deposited Si layeris visible, most likely due to incomplete penetration of the Ga+ ions through thelayer. Figure 4.5 b shows the cross-section at the edge of the platform implantationinto the substrate. The thickness of the implanted layer in the platform area is44 nm. The thickness of the layer deposited over the implanted platform region is67 nm, and the thickness of the free-etched suspended layer deposited over the non-implanted region is 37 nm. The thickness of the free-etched suspended layer agreesreasonably well with the predictions of the TRIM simulation code. Figure 4.5 cshows the suspended beam layer embedded in the platinum cover layer (Paper 5).

Figure 4.6 shows a high-resolution TEM image of the area indicated inFigure 4.5 b, i.e., around the original wafer surface (shown in more detail inFigure 4.6 b). Lattice fringes are clearly visible, indicating that both the implantedlayer of the wafer and the deposited layer are polycrystalline with grains smallerthan 10 nm. This is confirmed by the fast Fourier transform (FFT) analysisshown in Figure 4.6 c. Amorphization of Si is a known result of FIB Ga+ ionimplantation [211] and the subsequent annealing steps have caused recrystallizationof the amorphized Si to a polycrystalline state (Paper 5).


This chapter proposes a novel additive fabrication process for the manufacturing of3D micro- and nanostructures. The technique is similar to popular 3D printingapproaches but uses silicon as a base material and offers high resolutions. Itmay be possible to implement Si CVD and FIB writing as switched processesin a single automated tool, which could enable 3D printing of silicon micro- andnano- structures directly from CAD models. Thus, the proposed technology couldchange and greatly simplify the fabrication of many MEMS, NEMS and Si photonicdevices, without requiring a fully equipped semiconductor cleanroom. This layer-by-layer fabrication method is in principle also viable for the implementation of 3Dstructures in semiconductors other than Si.

Chapter 5

Conclusions

This work proposes a number of novel fabrication and integration techniques thatenable the realization of innovative 3D micro- and nanodevices.

3D Heterogeneous Integration of Bulk Wire Materials

• A multitude of inherently void-free bulk wire materials, including standardhigh-purity metals and highly specialized alloys, are commercially available.For a wide spectrum of applications, the integration of microwires proves tobe an attractive alternative to conventional metal deposition techniques thatsuffer from limited material choice, difficult controllability, long process timesand issues connected to void formation.

• A promising integration technique for at least partly ferromagnetic bulk wirematerials based on magnetic assembly has been developed. With that method,the fabrication of through silicon vias with very high aspect ratios (>20:1)and excellent electrical performance has been demonstrated.

• The paradigm that wire bonding merely serves the purpose of creatingelectrical interconnections is shifting. This technology has the potential tomove from back-end to front-end processing for a multitude of MEMS andIC applications. This has been successfully demonstrated on applicationsincluding through silicon via fabrication, liquid and vacuum packaging andmicroactuators.

63

64 CHAPTER 5. CONCLUSIONS

3D Heterogeneous Integration Based on Layer Transfer

• Promising novel materials can be incompatible with standard IC manu-facturing due to elevated deposition temperatures and/or issues related tocontamination. An integration based on layer transfer proves to be an effectiveand flexible method in order to be able to make use of non-standard materials.

• Layer transfer technology enables a CMOS process integration of SiGe, a highperformance thermistor material, for the manufacturing of uncooled infraredbolometer imaging arrays. The integration of monolayer Graphene, a materialwith unique and more than promising characteristics, has been demonstratedon a gauge-type pressure sensor.

3D Free-Form Patterning of Silicon

• A straightforward method, similar to popular 3D printing techniques, for themanufacturing of high resolution 3D silicon micro- and nanostructures hasbeen developed.

• The method is based on alternating steps of chemical vapor deposition ofsilicon and local implantation of gallium ions by focused ion beam writingand a final selectively release etch of the non-implanted silicon.

• 3D printing of silicon micro- and nanostructures directly from CAD modelscould be realized by implementing CVD and FIB technology as switchedprocesses in a single automated tool. The proposed technology could changeand greatly simplify the fabrication of many MEMS, NEMS and Si photonicdevices, without requiring a fully equipped semiconductor cleanroom.

Summary of Appended Papers

Paper 1: Wire-bonded through-silicon vias with low capacitive substrate coupling

Three-dimensional integration of electronics and/or MEMS-based transducersis an emerging technology that vertically interconnects stacked dies withthrough-silicon vias (TSVs). They enable the realization of circuits withshorter signal path lengths, smaller packages and lower parasitic capacitances,which results in higher performance and lower costs. This paper presents anovel technique for fabricating TSVs from bonded gold wires. The wires areembedded in a polymer, which acts both as an electrical insulator, resultingin low capacitive coupling toward the substrate and as a buffer for thermo-mechanical stress.

Paper 2: Hermetic integration of liquids using high-speed stud bump bonding forcavity sealing at the wafer level

This paper reports a novel room-temperature hermetic liquid sealing processwhere the access ports of liquid-filled cavities are sealed with wire-bonded studbumps. This process enables liquids to be integrated at the fabrication stage.Evaluation cavities were manufactured and used to investigate the mechanicaland hermetic properties of the seals. Measurements on the successfully sealedstructures show a helium leak rate of better than 10−10 mbarl/s, in additionto a zero liquid loss over two months during storage near boiling temperature.The bond strength of the plugs was similar to standard wire bonds on flatsurfaces.

Paper 3: Wire-bonder-assisted integration of non-bondable SMA wires intoMEMS substrates

This paper reports on a novel technique for the integration of NiTi shapememory alloy wires and other non-bondable wire materials into silicon-basedmicroelectromechanical system structures using a standard wire-bonding tool.The efficient placement and alignment functions of the wire-bonding toolare used to mechanically attach the wire to deep-etched silicon anchoringand clamping structures. This approach enables a reliable and accurateintegration of wire materials that cannot be wire bonded by traditional means.

65

66 SUMMARY OF APPENDED PAPERS

Paper 4: 3D free-form patterning of silicon by ion implantation, silicondeposition, and selective silicon etchingA method for additive layer-by-layer fabrication of arbitrarily shaped 3Dsilicon micro- and nanostructures is reported. The fabrication is based onalternating steps of chemical vapor deposition of silicon and local implantationof gallium ions by focused ion beam (FIB) writing. In a final step, thedefined 3D structures are formed by etching the silicon in potassium hydroxide(KOH), in which the local ion implantation provides the etching selectivity.The method is demonstrated by fabricating 3D structures made of two andthree silicon layers, including suspended beams that are 40 nm thick, 500 nmwide, and 4 µm long, and patterned lines that are 33 nm wide.

Paper 5: Very high aspect ratio through silicon vias (TSVs) fabricated usingautomated magnetic assembly of nickel wiresThrough-silicon via (TSV) technology enables 3D-integrated devices withhigher performance and lower cost as compared to 2D-integrated systems.This is mainly due to smaller dimensions of the package and shorter internalsignal lengths with lower capacitive, resistive and inductive parasitics. Thispaper presents a novel low-cost fabrication technique for metal-filled TSVswith very high aspect ratios (>20). Nickel wires are placed in via holes of asilicon wafer by an automated magnetic assembly process and are used as aconductive path of the TSV. This metal filling technique enables the reliablefabrication of through-wafer vias with very high aspect ratios and potentiallyeliminates characteristic cost drivers in the TSV production such as advancedmetallization processes, wafer thinning and general issues

Paper 6: Process considerations for layer-by-layer 3D patterning of silicon, usingion implantation, silicon deposition, and selective silicon etchingThe authors study suitable process parameters, and the resulting patternformation, in additive layer-by-layer fabrication of arbitrarily shaped three-dimensional (3D) silicon (Si) micro- and nanostructures. The layer-by-layerfabrication process investigated is based on alternating steps of chemical vapordeposition of Si and local implantation of gallium ions by focused ion beamwriting. In a final step, the defined 3D structures are formed by etching theSi in potassium hydroxide, where the ion implantation provides the etchingselectivity.

Paper 7: Pressure sensors based on suspended graphene membranesA novel pressure sensor based on a suspended graphene membrane isproposed. The sensing mechanism is explained based on tight bindingcalculations of strain-induced changes in the band structure. A CMOScompatible fabrication process is proposed and used to fabricate prototypes.Electrical measurement data demonstrates the feasibility of the approach,which has the advantage of not requiring a separate strain gauge, i.e. the

67

strain gauge is integral part of the pressure sensor membrane. Hence,graphene membrane based pressure sensors can in principle be scaled quiteaggressively in size.

Paper 8: High aspect ratio through silicon vias (TSVs) for high-frequencyapplications fabricated by automated magnetic assembly of gold-coated nickelwiresIn this paper we demonstrate a novel manufacturing technology for highaspect ratio (> 6) vertical interconnects with superior figure of merits forhighfrequency applications. This novel approach is based on magnetic self-assembly of pre- fabricated nickel wires that are subsequently insulatedwith a thermosetting polymer. Superior high frequency performance isachieved by depositing a gold layer on the outer surface of the nickel wires.Using highly-conductive materials such as gold offers an improvement of theelectrical characteristics for many technologies like e.g. interposer, MEMS,or millimeter wave applications. As compared to the conventional throughsilicon via (TSV) designs, this novel concept offers a more compact design andbetter control of the process parameters. Moreover, this fabrication conceptis adaptable to almost any kind of conductive via material which enablestailor-made functionalizations for various different technologies and fields ofapplication.

Paper 9: Heterogeneous 3D integration of 17 µm pitch Si/SiGe quantum wellbolometer arrays for infrared imaging systemsThis paper reports on the realization of 17 µm × 17 µm pitch bolometer arraysfor uncooled infrared imagers. Microbolometer arrays have been available inprimarily defense applications since the mid eighties and are typically based ondeposited thin films on top of CMOS wafers that are surface machined intosensor pixels. This paper instead focuses on the heterogeneous integrationof monocrystalline Si/SiGe quantum well-based thermistor material in aCMOS-compliant process using adhesive wafer bonding. The high qualitymonocrystalline thermistor material opens up for potentially lower noisecompared to commercially available uncooled microbolometer arrays togetherwith a competitive temperature coefficient of resistance (TCR). Characterizedbolometers had a TCR of −2.9 %/K in vacuum while the bolometer designsresulted in measured thermal conductances of around 5 · 10−8 W/K andthermal time constants of around 5 ms, depending on design. Complicationsin the fabrication of stress-free bolometer legs and low noise contacts arediscussed and analyzed.

68 SUMMARY OF APPENDED PAPERS

Paper 10: Very large scale heterogeneous integration (VLSHI) and wafer-levelvacuum packaging for infrared bolometer focal plane arraysImaging in the long wavelength infrared (LWIR) range from 8 − 14 µmis an extremely useful tool for non-contact measurement and imagingof temperature in many industrial, automotive and security applications.However, the cost of the infrared (IR) imaging components has to be reducedsignificantly to make IR imaging a viable technology for many cost-sensitiveapplications. This paper demonstrates new and improved fabrication andpackaging technologies for next-generation IR imaging detectors based onuncooled IR bolometer focal plane arrays. The proposed technologies includevery large scale heterogeneous integration for combining high-performance,SiGe quantum-well bolometers with electronic integrated read-out circuitsand CMOS compatible wafer-level vacuum packing. The fabrication andcharacterization of bolometers with a pitch of 25 µm × 25 µm that arearranged on read-out-wafers in arrays with 320 × 240 pixels are presented.The bolometers contain a multilayer quantum well SiGe thermistor witha temperature coefficient of resistance of −3 %/K. The proposed CMOScompatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquidinterdiffusion (SLID) bonding. The presented technologies are suitable forimplementation in cost-efficient fabless business models and could bringabout the cost reduction needed to enable low-cost IR imaging products forindustrial, security and automotive applications.

Paper 11: Wafer-level vacuum sealing by coining of wire bonded gold bumpsThis paper reports on the investigation of a novel room temperature vacuumsealing process based on compressing wire bonded gold bumps placed partlyoverlapping cavity access ports. The bump compression, which is done undervacuum, causes a material flow into the access ports, hermetically sealinga vacuum inside the ports. The sealed cavity pressure was measured byresidual gas analysis to 8 · 10−4 mbar two weeks after sealing, which canbe extrapolated to a cavity pressure of 2 · 10−2 mbar after one year. Theseals are found to be mechanically robust and easily processed by the use ofstandard commercial tools and processes.

Acknowledgments

I would like to express my sincere gratitude to the head of the department GöranStemme and my supervisor Frank Niklaus for giving me the opportunity to do myPh.D. studies in one of the best work environments imaginable. I also owe specialthanks to Niclas Roxhed for his guidance throughout the years and his out-of-the-box thinking that not only led to elegant solutions to problems but also to greatnew ideas. This dissertation would not have been possible without the support,guidance, understanding and encouragement of these persons.

I would like to thank the members of the dissertation committee, Karl Böhringer,Ilia Katardjiev, Per-Erik Hellström and Niklas Svedin for reviewing my thesis.

I owe special thanks to my co-worker, friend and office roommate Martin Lapisawho not only brought me to Sweden in the first place but always provided anoutstanding professional and private support.

I especially want to thank my former intern Nora Heinig and my masterstudents, Paw Toldbot Kristiansen, Stephan Schröder and Simon Bleiker for theiroutstanding work. I am more than grateful that the two latter candidates becamefellow Ph.D. students, respectable colleagues and more importantly friends of mine.

I also would like to thank my co-workers at MST who have enriched my stay inSweden and who made the department the work environment that it is: Erika Appelfor her patience and guidance through KTH’s bureaucracy | Kjell Norén for makingthings work every single time and in no time | Niklas Sandström for encouragingme to speak swedish at work, his optimism and many great discussions about,well, almost everything | Fritzi Töpfer for her highly appreciated and countlessinitiatives to bring the group closer together during and after the regular officehours | Umer Shah, the man with the niftiest mustache of all, for his ability toexplain RF-related things in a way even I can understand | Fredrik Forsberg forhis heroic cleanroom work and his ability to manage processes with at least azillion steps | Henrik Gradin for a great and highly effective co-authorship and forsharing his experiences as entrepreneur | Kristinn Gylfason for his objectivenessand knowledge and for making me fall in love with Iceland | Mikael Sterner, for hisreadiness to help and for always offering ingeniously simple solutions to complexproblems | Wouter van der Wijngaart for many out-of-the-box ideas and turning theevenings of international conferences into big fun | Laila Ladhani for not hesitatingfor a second to proofread this thesis | Fredrik Carlborg for introducing me to chinese

69

70 ACKNOWLEDGMENTS

culture and food, a truly great experience | Mikael Antelius, I envy your calm.Thank you for an enjoyable collaboration and for spending many interesting hoursin the lab | Mikael Karlsson for his constantly positive attitude and readiness tohelp others | Staffan Johansson for sharing his views on swedish haute cuisineand for organizing tasty sill lunches | Hans Sohlström for sharing his insightsabout photography, optics and teaching | Tommy Haraldsson, the rubber rocketscientist, for turning ordinary polymers into fantastic polymers | Stefan Braun forestablishing various (positive) german customs at MST | Björn Samel for helpingme to understand swedish mentality | Zargham Baghchehsaraei for his enthusiasmand positive attitude towards others | Valentin Dubois for bringing the frenchtouch to MST and for many fitness related discussions at KTH Hallen | JoachimOberhammer for his vast knowledge about RF technology and his slightly sarcasticview on things | Gaspard Pardon for many great discussions and for being part offantastic journeys all over the world | Farizah Saharil for representing our groupin social media | Nutapong Somjit for a fruitful collaboration and delicious thailunches | Nikolai Chekurov for lightning up the place with his humor | AlexanderVastesson for being a part of the lunchbox gang | Xiamo Zhou for bringing a freshwind to our group | Floria Ottonello for explaining the italian way of life.

Furthermore, I’d like to thank my collaborators outside of MST I hadthe pleasure of working with: Matt Grange, Roshan Weerasekera and DineshPamunuwa from Lancaster University for their TSV simulation expertise andenjoyable co-authoring process. Yuri Rikers from FEI and Lyubov Belova, GunnarMalm, Henry Radamson and Mohammadreza Kolahdouz from KTH for theirFIB/SEM/TEM/Epi expertise. Kai Kratt, Ali Moazenzadeh, Ulrike Wallrabe andJan Korvink from University of Freiburg for their support and sharing the vision ofwire bonding. Daniel Carlsson from KTH Innovation for his coaching and proactivesupport during the process of commercialization of research ideas.

The personnel from our cleanroom facility, namely Magnus Lindberg, RezaNikpars and Sven Valerio for keeping the wheels greased.

Beyond MST, Amina Kandri and Peter Lodemann: I don’t know what thisworld would be like without your friendship. Alexandré Magny and the ”Bengeclan” - Anika, Stephen, David and Joel for making my stay in Sweden a great one.My buddies Emelie Eldrige and Yasser Abdali for their friendship above and belowthe water surface.

I would also like to express my gratitude to my friends Christoph Hepp andPhilipp Waibel (a.k.a. ”The Office”) for their companionship throughout the pastyears, for exceptionally great ”office meetings” at places all over the world andinvaluable discussions giving insights about life and work as a Ph.D. student.

Almost finally, but particularly and most of all: Anna, for coming into my lifeand for teaching me that there is more to Sweden than Stockholm. Jag älskar dig.

Last but definitely not least I want to thank the persons who made me believein myself in all phases throughout my life - my family. I owe my deepest gratitudeto my brother and my parents, truly fantastic individuals who always were therefor me and supported me in every way imaginable. Danke.

References

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[4] M. J. Madou, Fundamentals of Microfabrication : The Science ofMiniaturization. Taylor and Francis, 2002.

[5] M. Motoyoshi, “Through-silicon via (TSV),” Proceedings of the IEEE, vol. 97,no. 1, pp. 43 –48, jan. 2009.

[6] M. Koyanagi, T. Fukushima, and T. Tanaka, “High-density through siliconvias for 3-D LSIS,” Proceedings of the IEEE, vol. 97, no. 1, pp. 49 –59, jan.2009.

[7] R. Weerasekera, D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, “Two-dimensional and three-dimensional integration of heterogeneous electronicsystems under cost, performance, and technological constraints,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on,vol. 28, no. 8, pp. 1237 –1250, aug. 2009.

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