Document No: 330788-003

Intel® C610 Series Chipset and Intel® X99 Chipset Platform Controller Hub (PCH)Datasheet

October 2015

ii Intel® C610 Series Chipset and Intel® X99 ChipsetPlatform Controller Hub (PCH) Datasheet

Intel technologies features and benefits depend on system configuration and may require enabled hardware, software, or serviceactivation. Learn more at intel.com, or from the OEM or retailer.No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or anydamages resulting from such losses.You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intelproducts described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter draftedwhich includes subject matter disclosed herein.No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.The products described may contain design defects or errors known as errata which may cause the product to deviate frompublished specifications. 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Contact your Intel representative to obtain the latest Intel product specifications and roadmaps.Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness fora particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, orusage in trade.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtainedby calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com/design/literature.htm.I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.Requires an Intel® HD Audio enabled system. Consult your PC manufacturer for more information. Sound quality will depend on equipment and actual implementation. For more information about Intel HD Audio, refer to Intel® High Definition AudioIntel® Active Management Technology (Intel® AMT) requires activation and a system with a corporate network connection, an Intel® AMT-enabled chipset, network hardware and software. For notebooks, Intel AMT may be unavailable or limited over a host OS-based VPN, when connecting wirelessly, on battery power, sleeping, hibernating or powered off. Results dependent upon hardware, setup & configuration. For more information, visit http://www.intel.com/technology/platform-technology/intel-amt Intel® Smart Response Technology requires a Intel® Core™ processor, select Intel® chipset, Intel® Rapid Storage Technology software version 12.5 or higher, and a solid state hybrid drive reporting at least 16GB capacity and supporting SATA-IO hybrid information feature. Depending on system configuration, your results may vary. Contact your system manufacturer for more information.No computer system can provide absolute security under all conditions. Intel® Trusted Execution Technology (Intel® TXT) requires a computer system with Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible Measured Launched Environment (MLE). Intel TXT also requires the system to contain a TPM v1.s. For more information, visit http://www.intel.com/technology/security No system can provide absolute security under all conditions. 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Availability of features and results will depend upon the setup and configuration of your hardware, software and IT environment. To learn more visit: http://www.intel.com/technology/vpro Intel, Intel vPro and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.*Other names and brands may be claimed as the property of others.Copyright © 2015, Intel Corporation

Intel® C610 Series Chipset and Intel® X99 Chipset iiiPlatform Controller Hub (PCH) Datasheet

Contents

1 Introduction............................................................................................................... 11.1 About This Manual ...............................................................................................1

1.1.1 Chapter Descriptions...............................................................................21.2 Overview ...........................................................................................................4

1.2.1 Capability Overview ................................................................................51.3 PCH SKU Definition............................................................................................ 10

1.3.1 High-End Desktop (HEDT) Platforms ....................................................... 101.4 Device and Revision ID Table .............................................................................. 111.5 Electrostatic Discharge (ESD) Testing................................................................... 12

2 Signal Description.................................................................................................... 132.1 Flexible I/O ...................................................................................................... 152.2 USB Interface ................................................................................................... 162.3 PCI Express* .................................................................................................... 202.4 Serial ATA Interface........................................................................................... 212.5 Clock Signals .................................................................................................... 242.6 Real Time Clock Interface................................................................................... 262.7 External RTC Circuitry........................................................................................ 26

2.7.1 Crystal Requirements............................................................................ 262.8 Interrupt Interface ............................................................................................ 272.9 Processor Interface............................................................................................ 272.10 Direct Media Interface (DMI) to Host Controller ..................................................... 282.11 Intel® High Definition Audio Link ......................................................................... 282.12 LPC Interface.................................................................................................... 292.13 General Purpose I/O Signals ............................................................................... 292.14 GPIO Serial Expander Signals.............................................................................. 342.15 Functional Straps .............................................................................................. 342.16 SMBus Interface................................................................................................ 372.17 MS SMBus Interface .......................................................................................... 372.18 System Management Interface............................................................................ 382.19 Serial Peripheral Interface (SPI) .......................................................................... 382.20 Manageability Signals ........................................................................................ 392.21 Power Management Interface.............................................................................. 402.22 Power and Ground Signals .................................................................................. 422.23 Thermal Signals ................................................................................................ 432.24 Miscellaneous Signals......................................................................................... 432.25 Testability Signals ............................................................................................. 452.26 Reserved / Test Pins .......................................................................................... 45

3 PCH Pin States ......................................................................................................... 473.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 473.2 Output and I/O Signals Planes and States............................................................. 483.3 Input and I/O Signals Planes and States............................................................... 53

4 System Clock Domains ............................................................................................. 594.1 Platform Clocking Requirements for Native is CLK Mode.......................................... 594.2 Platform Clocking Requirements for PCH Hybrid Mode ............................................ 614.3 Platform Clocking Requirements for External Clocking ............................................ 624.4 Functional Blocks .............................................................................................. 654.5 Clock Configuration Access Overview ................................................................... 654.6 Clock Configuration ........................................................................................... 664.7 Power up and down sequencing........................................................................... 67

iv Intel® C610 Series Chipset and Intel® X99 ChipsetPlatform Controller Hub (PCH) Datasheet

5 Functional Description..............................................................................................695.1 Flexible I/O.......................................................................................................695.2 Direct Media Interface (DMI) ...............................................................................70

5.2.1 PCI Bus Interface..................................................................................705.2.2 PCI Legacy Mode ..................................................................................70

5.3 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) .......................................705.3.1 Supported PCIe* Port Configurations .......................................................715.3.2 Interrupt Generation .............................................................................715.3.3 Power Management...............................................................................725.3.4 SERR# Generation ................................................................................745.3.5 Hot-Plug ..............................................................................................74

5.4 Gigabit Ethernet Controller (B0:D25:F0) ...............................................................765.4.1 GbE PCI Express Bus Interface ...............................................................785.4.2 Error Events and Error Reporting ............................................................795.4.3 Ethernet Interface.................................................................................795.4.4 PCI Power Management .........................................................................805.4.5 Configurable LEDs.................................................................................825.4.6 Function Level Reset Support (FLR) .........................................................83

5.5 LPC Bridge (with System and Management Functions) (D31:F0)...............................835.5.1 LPC Interface .......................................................................................83

5.6 DMA Operation (D31:F0) ....................................................................................875.6.1 Channel Priority ....................................................................................885.6.2 Address Compatibility Mode....................................................................895.6.3 Summary of DMA Transfer Sizes .............................................................895.6.4 Autoinitialize ........................................................................................905.6.5 Software Commands .............................................................................90

5.7 LPC DMA ..........................................................................................................915.7.1 Asserting DMA Requests ........................................................................915.7.2 Abandoning DMA Requests.....................................................................915.7.3 General Flow of DMA Transfers ...............................................................925.7.4 Terminal Count.....................................................................................925.7.5 Verify Mode..........................................................................................925.7.6 DMA Request de-assertion .....................................................................935.7.7 SYNC Field / LDRQ# Rules .....................................................................93

5.8 8254 Timers (D31:F0)........................................................................................945.8.1 Timer Programming ..............................................................................945.8.2 Reading from the Interval Timer .............................................................95

5.9 8259 Programmable Interrupt Controllers (PIC) (D31:F0) .......................................975.9.1 Interrupt Handling ................................................................................985.9.2 Initialization Command Words (ICWx) .....................................................995.9.3 Operation Command Words (OCW) .......................................................1005.9.4 Modes of Operation .............................................................................1005.9.5 Masking Interrupts..............................................................................1025.9.6 Steering PCI Interrupts........................................................................102

5.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0)...............................1035.10.1 Interrupt Handling ..............................................................................1035.10.2 Interrupt Mapping...............................................................................1035.10.3 PCI/PCI Express* Message-Based Interrupts...........................................1045.10.4 IOxAPIC Address Remapping ................................................................1045.10.5 External Interrupt Controller Support.....................................................105

5.11 Serial Interrupt (D31:F0)..................................................................................1055.11.1 Start Frame .......................................................................................1055.11.2 Data Frames ......................................................................................1055.11.3 Stop Frame........................................................................................1065.11.4 Specific Interrupts Not Supported Using SERIRQ .....................................1065.11.5 Data Frame Format .............................................................................106

Intel® C610 Series Chipset and Intel® X99 Chipset vPlatform Controller Hub (PCH) Datasheet

5.12 Real Time Clock (D31:F0)................................................................................. 1075.12.1 Update Cycles .................................................................................... 1085.12.2 Interrupts.......................................................................................... 1085.12.3 Lockable RAM Ranges ......................................................................... 1085.12.4 Century Rollover ................................................................................ 1085.12.5 Clearing Battery-Backed RTC RAM ........................................................ 109

5.13 Processor Interface (D31:F0) ............................................................................ 1105.13.1 Processor Interface Signals and VLW Messages....................................... 1105.13.2 Dual-Processor Issues ......................................................................... 1125.13.3 Virtual Legacy Wire (VLW) Messages..................................................... 112

5.14 Power Management ......................................................................................... 1125.14.1 Features............................................................................................ 1125.14.2 PCH and System Power States ............................................................. 1125.14.3 System Power Planes .......................................................................... 1145.14.4 SMI#/SCI Generation.......................................................................... 1155.14.5 C-States............................................................................................ 1185.14.6 Sleep States ...................................................................................... 1185.14.7 Event Input Signals and Their Usage ..................................................... 1225.14.8 ALT Access Mode................................................................................ 1255.14.9 System Power Supplies, Planes, and Signals .......................................... 1275.14.10 Legacy Power Management Theory of Operation ..................................... 1315.14.11 Reset Behavior................................................................................... 131

5.15 System Management (D31:F0).......................................................................... 1335.15.1 Theory of Operation............................................................................ 1335.15.2 TCO Modes ........................................................................................ 135

5.16 General Purpose I/O (D31:F0) .......................................................................... 1375.16.1 Power Wells ....................................................................................... 1375.16.2 SMI# SCI and NMI Routing.................................................................. 1375.16.3 Triggering ......................................................................................... 1375.16.4 GPIO Registers Lockdown .................................................................... 1375.16.5 Serial POST Codes over GPIO............................................................... 1385.16.6 GPIO Serial Expander (GSX) ................................................................ 140

5.17 SATA Host Controller (D31:F2, F5) .................................................................... 1415.17.1 SATA 6 Gb/s Support .......................................................................... 1415.17.2 SATA Feature Support......................................................................... 1425.17.3 Theory of Operation............................................................................ 1425.17.4 SATA Swap Bay Support...................................................................... 1435.17.5 Hot-Plug Operation ............................................................................. 1435.17.6 Function Level Reset Support (FLR)....................................................... 1435.17.7 Intel® Rapid Storage Technology (Intel® RST) Configuration.................... 1445.17.8 Intel® Smart Response Technology....................................................... 1455.17.9 Power Management Operation.............................................................. 1455.17.10 Power State Transitions....................................................................... 1455.17.11 SATA Device Presence......................................................................... 1465.17.12 SATA LED.......................................................................................... 1475.17.13 AHCI Operation .................................................................................. 1475.17.14 SGPIO Signals.................................................................................... 1485.17.15 External SATA.................................................................................... 152

5.18 High Precision Event Timers (HPET) ................................................................... 1525.18.1 Timer Accuracy .................................................................................. 1525.18.2 Interrupt Mapping .............................................................................. 1535.18.3 Periodic versus Non-Periodic Modes....................................................... 1545.18.4 Enabling the Timers ............................................................................ 1545.18.5 Interrupt Levels ................................................................................. 1545.18.6 Handling Interrupts ............................................................................ 1555.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors ............................ 155

vi Intel® C610 Series Chipset and Intel® X99 ChipsetPlatform Controller Hub (PCH) Datasheet

5.19 USB EHCI Host Controllers (D29:F0 and D26:F0) .................................................1565.19.1 EHC Initialization ................................................................................1565.19.2 Data Structures in Main Memory ...........................................................1565.19.3 USB 2.0 Enhanced Host Controller DMA .................................................1575.19.4 Data Encoding and Bit Stuffing .............................................................1575.19.5 Packet Formats...................................................................................1575.19.6 USB 2.0 Interrupts and Error Conditions ................................................1575.19.7 USB 2.0 Power Management.................................................................1585.19.8 USB 2.0 Legacy Keyboard Operation......................................................1595.19.9 USB 2.0 Based Debug Port ...................................................................1595.19.10 EHCI Caching .....................................................................................1645.19.11 Intel® USB Pre-Fetch Based Pause ........................................................1645.19.12 Function Level Reset Support (FLR) .......................................................1645.19.13 USB Overcurrent Protection..................................................................165

5.20 Integrated USB 2.0 Rate Matching Hub...............................................................1655.20.1 Overview ...........................................................................................1655.20.2 Architecture .......................................................................................166

5.21 xHCI Controller (D20:F0)..................................................................................1665.22 SMBus Controller (D31:F3) ...............................................................................167

5.22.1 Host Controller ...................................................................................1675.22.2 Bus Arbitration ...................................................................................1715.22.3 Bus Timing.........................................................................................1725.22.4 Interrupts / SMI# ...............................................................................1725.22.5 SMBALERT#.......................................................................................1735.22.6 SMBus CRC Generation and Checking ....................................................1735.22.7 SMBus Slave Interface.........................................................................173

5.23 Thermal Management.......................................................................................1795.23.1 Thermal Sensor ..................................................................................1795.23.2 PCH Thermal Throttling........................................................................1805.23.3 Thermal Reporting Over System Management Link 1 Interface

(SMLink1)..........................................................................................1815.24 Intel® High Definition Audio (Intel® HD Audio) Overview (D27:F0).........................1875.25 Intel® Management Engine (Intel® ME) and Intel® Server Platform Services

Firmware (SPS 3.0)..........................................................................................1875.25.1 Intel® Management Engine (Intel® ME) Requirements .............................188

5.26 Serial Peripheral Interface (SPI) ........................................................................1895.26.1 SPI Supported Feature Overview...........................................................1905.26.2 Flash Descriptor..................................................................................1915.26.3 Flash Access.......................................................................................1945.26.4 Serial Flash Device Compatibility Requirements.......................................1945.26.5 Multiple Page Write Usage Model...........................................................1975.26.6 Flash Device Configurations..................................................................1985.26.7 SPI Flash Device Recommended Pinout ..................................................1985.26.8 Serial Flash Device Package .................................................................1995.26.9 PWM Outputs .....................................................................................1995.26.10 TACH Inputs.......................................................................................200

5.27 Feature Capability Mechanism ...........................................................................2005.28 Intel® Virtualization Technology.........................................................................200

5.28.1 Intel® VT-d Objectives ........................................................................2005.28.2 Intel® VT-d Features Supported............................................................2005.28.3 Support for Function Level Reset (FLR) in PCH ........................................2015.28.4 Virtualization Support for PCH’s IOxAPIC................................................2015.28.5 Virtualization Support for High Precision Event Timer (HPET) ....................201

5.29 Enterprise Value Add (EVA)...............................................................................2025.29.1 Overview of EVA .................................................................................2025.29.2 Server Platform Services ROM (SPSR)....................................................202

Intel® C610 Series Chipset and Intel® X99 Chipset viiPlatform Controller Hub (PCH) Datasheet

5.29.3 MS SMBus controllers.......................................................................... 2035.29.4 sSATA Controllers (D17:F4) ................................................................. 2045.29.5 Asynchronous DRAM Refresh (ADR) ...................................................... 215

6 Ballout Definition ................................................................................................... 2176.1 PCH Ballout .................................................................................................... 217

7 Package Information ............................................................................................. 2317.1 PCH package .................................................................................................. 231

8 Electrical Characteristics........................................................................................ 2338.1 Thermal Specifications ..................................................................................... 233

8.1.1 PCH Storage Specifications and Thermal Design Power (TDP) ................... 2338.2 Absolute Maximum Ratings............................................................................... 2338.3 PCH Power Supply Range ................................................................................. 2348.4 General DC Characteristics ............................................................................... 2348.5 Power Sequencing and Reset Signal Timings ....................................................... 2468.6 Power Management Timing Diagrams................................................................. 2508.7 Timing Diagrams............................................................................................. 2558.8 Sequencing Rails Within The Same Well ............................................................. 258

9 Register and Memory Mapping............................................................................... 2619.1 PCI Devices and Functions................................................................................ 2629.2 PCI Configuration Map ..................................................................................... 2639.3 I/O Map ......................................................................................................... 263

9.3.1 Fixed I/O Address Ranges.................................................................... 2639.3.2 Variable I/O Decode Ranges................................................................. 266

9.4 Memory Map................................................................................................... 2679.4.1 Boot-Block Update Scheme.................................................................. 269

10 Chipset Configuration Registers............................................................................. 27110.1 Chipset Configuration Registers (Memory Space) ................................................. 271

10.1.1 RPC—Root Port Configuration Register................................................... 27310.1.2 RPFN—Root Port Function Number and Hide for PCI

Express* Root Ports Register ............................................................... 27310.1.3 FLRSTAT—Function Level Reset Pending Status Register .......................... 27510.1.4 TRSR—Trap Status Register ................................................................. 27510.1.5 TRCR—Trapped Cycle Register ............................................................. 27510.1.6 TWDR—Trapped Write Data Register ..................................................... 27610.1.7 IOTRn—I/O Trap Register (0–3) ........................................................... 27610.1.8 V0CTL—Virtual Channel 0 Resource Control Register ............................... 27710.1.9 V0STS—Virtual Channel 0 Resource Status Register ................................ 27710.1.10 V1CTL—Virtual Channel 1 Resource Control Register ............................... 27710.1.11 V1STS—Virtual Channel 1 Resource Status Register ................................ 27810.1.12 UES—Uncorrectable Error Status Register .............................................. 27810.1.13 UEM—Uncorrectable Error Mask Register ............................................... 27910.1.14 UEV—Uncorrectable Error Severity Register ........................................... 27910.1.15 CES—Correctable Error Status Register ................................................. 28010.1.16 CEM—Correctable Error Mask Register................................................... 28010.1.17 REC—Root Error Command Register...................................................... 28010.1.18 RES—Root Error Status Register ........................................................... 28110.1.19 ESID—Error Source Identification Register ............................................. 28110.1.20 LCAP—Link Capabilities Register ........................................................... 28210.1.21 LCTL—Link Control Register ................................................................. 28210.1.22 LSTS—Link Status Register .................................................................. 28310.1.23 DLCTL2—DMI Link Control 2 Register .................................................... 28310.1.24 DMIC—DMI Control Register ................................................................ 28310.1.25 TCTL—TCO Configuration Register ........................................................ 28310.1.26 D31IP—Device 31 Interrupt Pin Register................................................ 284

viii Intel® C610 Series Chipset and Intel® X99 ChipsetPlatform Controller Hub (PCH) Datasheet

10.1.27 D30IP—Device 30 Interrupt Pin Register ................................................28510.1.28 D29IP—Device 29 Interrupt Pin Register ................................................28510.1.29 D28IP—Device 28 Interrupt Pin Register ................................................28510.1.30 D27IP—Device 27 Interrupt Pin Register ................................................28610.1.31 D26IP—Device 26 Interrupt Pin Register ................................................28710.1.32 D25IP—Device 25 Interrupt Pin Register ................................................28710.1.33 D22IP—Device 22 Interrupt Pin Register ................................................28710.1.34 D20IP—Device 20 Interrupt Pin Register ................................................28810.1.35 D31IR—Device 31 Interrupt Route Register ............................................28810.1.36 D30IR—Device 30 Interrupt Route Register ............................................28910.1.37 D29IR—Device 29 Interrupt Route Register ............................................28910.1.38 D28IR—Device 28 Interrupt Route Register ............................................29010.1.39 D27IR—Device 27 Interrupt Route Register ............................................29110.1.40 D26IR—Device 26 Interrupt Route Register ............................................29210.1.41 D25IR—Device 25 Interrupt Route Register ............................................29210.1.42 D22IR—Device 22 Interrupt Route Register ............................................29310.1.43 D20IR—Device 20 Interrupt Route Register ............................................29410.1.44 OIC—Other Interrupt Control Register ...................................................29510.1.45 WADT_AC - Wake Alarm Device Timer: AC .............................................29610.1.46 WADT_DC—Wake Alarm Device Timer: DC Register.................................29610.1.47 WADT_EXP_AC—Wake Alarm Device Expired Timer: AC

Register.............................................................................................29610.1.48 WADT_EXP_DC—Wake Alarm Device Expired Timer: DC

Register.............................................................................................29710.1.49 PRSTS—Power and Reset Status Register ...............................................29710.1.50 PM_CFG—Power Management Configuration Register...............................29810.1.51 PCH_PM_STS—Chipset Power Management Status ..................................29910.1.52 DEEP_S3_POL—Deep Sx From S3 Power Policies Register.........................30010.1.53 DEEP_S4_POL—Deep Sx From S4 Power Policies Register.........................30010.1.54 DEEP_S5_POL—Deep Sx From S5 Power Policies Register.........................30010.1.55 DSX_CFG - Deep Sx Configuration Register ............................................30110.1.56 PMSYNC_CFG—PMSYNC Configuration ...................................................30110.1.57 ADR_EN — ADR Enable........................................................................30210.1.58 RC—RTC Configuration Register ............................................................30210.1.59 HPTC—High Precision Timer Configuration Register..................................30310.1.60 GCS—General Control and Status Register .............................................30310.1.61 BUC—Backed Up Control Register .........................................................30410.1.62 FD—Function Disable Register ..............................................................30510.1.63 CG—Clock Gating Register ...................................................................30710.1.64 FDSW—Function Disable SUS Well Register ............................................30710.1.65 DISPBDF—Display Bus, Device and Function Initialization Register.............30810.1.66 FD2—Function Disable 2 Register ..........................................................30810.1.67 GSXBAR—GPIO Serial Expander Base Address ........................................30810.1.68 GSXCTRL—GPIO Serial Expander Control Register ...................................309

11 Gigabit LAN Configuration Registers.......................................................................31111.1 Gigabit LAN Configuration Registers

(Gigabit LAN—D25:F0) .....................................................................................31111.1.1 VID—Vendor Identification Register

(Gigabit LAN—D25:F0) ........................................................................31211.1.2 DID—Device Identification Register

(Gigabit LAN—D25:F0) ........................................................................31211.1.3 PCICMD—PCI Command Register

(Gigabit LAN—D25:F0) ........................................................................31311.1.4 PCISTS—PCI Status Register

(Gigabit LAN—D25:F0) ........................................................................314

Intel® C610 Series Chipset and Intel® X99 Chipset ixPlatform Controller Hub (PCH) Datasheet

11.1.5 RID—Revision Identification Register (Gigabit LAN—D25:F0)........................................................................ 315

11.1.6 CC—Class Code Register (Gigabit LAN—D25:F0)........................................................................ 315

11.1.7 CLS—Cache Line Size Register (Gigabit LAN—D25:F0)........................................................................ 315

11.1.8 PLT—Primary Latency Timer Register (Gigabit LAN—D25:F0)........................................................................ 315

11.1.9 HEADTYP—Header Type Register (Gigabit LAN—D25:F0)........................................................................ 315

11.1.10 MBARA—Memory Base Address Register A (Gigabit LAN—D25:F0)........................................................................ 316

11.1.11 MBARB—Memory Base Address Register B(Gigabit LAN—D25:F0)........................................................................ 316

11.1.12 MBARC—Memory Base Address Register C(Gigabit LAN—D25:F0)........................................................................ 316

11.1.13 SVID—Subsystem Vendor ID Register(Gigabit LAN—D25:F0)........................................................................ 317

11.1.14 SID—Subsystem ID Register(Gigabit LAN—D25:F0)........................................................................ 317

11.1.15 ERBA—Expansion ROM Base Address Register(Gigabit LAN—D25:F0)........................................................................ 317

11.1.16 CAPP—Capabilities List Pointer Register (Gigabit LAN—D25:F0)........................................................................ 317

11.1.17 INTR—Interrupt Information Register(Gigabit LAN—D25:F0)........................................................................ 318

11.1.18 MLMG—Maximum Latency/Minimum Grant Register(Gigabit LAN—D25:F0)........................................................................ 318

11.1.19 STCL—System Time Control Low Register(Gigabit LAN—D25:F0)........................................................................ 318

11.1.20 STCH—System Time Control High Register(Gigabit LAN—D25:F0)........................................................................ 318

11.1.21 LTRCAP—System Time Control High Register(Gigabit LAN—D25:F0)........................................................................ 319

11.1.22 CLIST1—Capabilities List Register 1(Gigabit LAN—D25:F0)........................................................................ 319

11.1.23 PMC—PCI Power Management Capabilities Register (Gigabit LAN—D25:F0)........................................................................ 320

11.1.24 PMCS—PCI Power Management Control and StatusRegister (Gigabit LAN—D25:F0)............................................................ 320

11.1.25 DR—Data Register (Gigabit LAN—D25:F0)........................................................................ 321

11.1.26 CLIST2—Capabilities List Register 2(Gigabit LAN—D25:F0)........................................................................ 321

11.1.27 MCTL—Message Control Register(Gigabit LAN—D25:F0)........................................................................ 322

11.1.28 MADDL—Message Address Low Register(Gigabit LAN—D25:F0)........................................................................ 322

11.1.29 MADDH—Message Address High Register(Gigabit LAN—D25:F0)........................................................................ 322

11.1.30 MDAT—Message Data Register(Gigabit LAN—D25:F0)........................................................................ 322

11.1.31 FLRCAP—Function Level Reset Capability(Gigabit LAN—D25:F0)........................................................................ 323

11.1.32 FLRCLV—Function Level Reset Capability Length andVersion Register (Gigabit LAN—D25:F0) ................................................ 323

11.1.33 DEVCTRL—Device Control Register (Gigabit LAN—D25:F0) ....................... 32411.2 Gigabit LAN Capabilities and Status Registers (CSR)............................................. 324

11.2.1 GBECSR_00—Gigabit Ethernet Capabilities and Status Register 00 ............ 325

x Intel® C610 Series Chipset and Intel® X99 ChipsetPlatform Controller Hub (PCH) Datasheet

11.2.2 GBECSR_18—Gigabit Ethernet Capabilities and Status Register 18 ............32511.2.3 GBECSR_20—Gigabit Ethernet Capabilities and Status Register 20 ............32511.2.4 GBECSR_2C—Gigabit Ethernet Capabilities and Status Register 2C ............32611.2.5 GBECSR_F00—Gigabit Ethernet Capabilities and Status Register F00 .........32611.2.6 GBECSR_F10—Gigabit Ethernet Capabilities and Status Register F10 .........32611.2.7 GBECSR_5400—Gigabit Ethernet Capabilities and Status Register 5400......32711.2.8 GBECSR_5404—Gigabit Ethernet Capabilities and Status Register 5404......32711.2.9 GBECSR_5800—Gigabit Ethernet Capabilities and Status Register 5800......32711.2.10 GBECSR_5B54—Gigabit Ethernet Capabilities and Status Register 5B54 .....327

12 LPC Interface Bridge Registers (D31:F0)................................................................32912.1 PCI Configuration Registers (LPC I/F—D31:F0) ....................................................329

12.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) ............................33012.1.2 DID—Device Identification Register (LPC I/F—D31:F0).............................33012.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) ...............................33112.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)......................................33112.1.5 RID—Revision Identification Register (LPC I/F—D31:F0)...........................33212.1.6 PI—Programming Interface Register (LPC I/F—D31:F0)............................33212.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0) ...................................33212.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0) ..................................33212.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0) ..........................33312.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0) ................................33312.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0) ...........................33312.1.12 CAPP – Capability List Pointer Register (LPC I/F—D31:F0) ........................33312.1.13 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0) .........................33412.1.14 ACPI_CNTL—ACPI Control Register (LPC I/F—D31:F0) .............................33412.1.15 GPIOBASE—GPIO Base Address Register (LPC I/F—D31:F0) .....................33512.1.16 GC—GPIO Control Register (LPC I/F—D31:F0) ........................................33512.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0) ..............................................................................33612.1.18 SIRQ_CNTL—Serial IRQ Control Register

(LPC I/F—D31:F0) ..............................................................................33612.1.19 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register

(LPC I/F—D31:F0) ..............................................................................33712.1.20 LPC_IBDF—IOxAPIC Bus:Device:Function

(LPC I/F—D31:F0) ..............................................................................33812.1.21 LPC_HnBDF – HPET n Bus:Device:Function

(LPC I/F—D31:F0) ..............................................................................33812.1.22 LPC_I/O_DEC—I/O Decode Ranges Register

(LPC I/F—D31:F0) ..............................................................................33912.1.23 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) ..............................33912.1.24 GEN1_DEC—LPC I/F Generic Decode Range 1 Register

(LPC I/F—D31:F0) ..............................................................................34012.1.25 GEN2_DEC—LPC I/F Generic Decode Range 2 Register

(LPC I/F—D31:F0) ..............................................................................34112.1.26 GEN3_DEC—LPC I/F Generic Decode Range 3 Register

(LPC I/F—D31:F0) ..............................................................................34112.1.27 GEN4_DEC—LPC I/F Generic Decode Range 4 Register

(LPC I/F—D31:F0) ..............................................................................34212.1.28 ULKMC—USB Legacy Keyboard / Mouse

Control Register(LPC I/F—D31:F0) ........................................................34212.1.29 LGMR—LPC I/F Generic Memory Range Register

(LPC I/F—D31:F0) ..............................................................................34312.1.30 BIOS_SEL1—BIOS Select 1 Register

(LPC I/F—D31:F0) ..............................................................................34412.1.31 BIOS_SEL2—BIOS Select 2 Register

(LPC I/F—D31:F0) ..............................................................................345

Intel® C610 Series Chipset and Intel® X99 Chipset xiPlatform Controller Hub (PCH) Datasheet

12.1.32 BIOS_DEC_EN1—BIOS Decode Enable Register (LPC I/F—D31:F0).................................................................. 345

12.1.33 BIOS_CNTL—BIOS Control Register (LPC I/F—D31:F0) .............................................................................. 347

12.1.34 FDCAP—Feature Detection Capability ID Register(LPC I/F—D31:F0) .............................................................................. 347

12.1.35 FDLEN—Feature Detection Capability Length Register(LPC I/F—D31:F0) .............................................................................. 348

12.1.36 FDVER—Feature Detection Version Register(LPC I/F—D31:F0) .............................................................................. 348

12.1.37 FVECIDX—Feature Vector Index Register(LPC I/F—D31:F0) .............................................................................. 348

12.1.38 FVECD—Feature Vector Data Register(LPC I/F—D31:F0) .............................................................................. 348

12.1.39 Feature Vector Space.......................................................................... 34912.1.40 RCBA—Root Complex Base Address Register

(LPC I/F—D31:F0) .............................................................................. 35012.2 DMA I/O Registers........................................................................................... 351

12.2.1 DMABASE_CA—DMA Base and Current Address Registers ........................ 35212.2.2 DMABASE_CC—DMA Base and Current Count Registers ........................... 35212.2.3 DMAMEM_LP—DMA Memory Low Page Registers ..................................... 35312.2.4 DMACMD—DMA Command Register ...................................................... 353

12.3 DMASTA—DMA Status Register ......................................................................... 35312.3.1 DMA_WRSMSK—DMA Write Single Mask Register.................................... 35412.3.2 DMACH_MODE—DMA Channel Mode Register ......................................... 35412.3.3 DMA Clear Byte Pointer Register ........................................................... 35512.3.4 DMA Master Clear Register................................................................... 35512.3.5 DMA_CLMSK—DMA Clear Mask Register ................................................ 35512.3.6 DMA_WRMSK—DMA Write All Mask Register........................................... 356

12.4 Timer I/O Registers ......................................................................................... 35612.4.1 TCW—Timer Control Word Register ....................................................... 35712.4.2 SBYTE_FMT—Interval Timer Status Byte Format Register......................... 35912.4.3 Counter Access Ports Register .............................................................. 359

12.5 8259 Interrupt Controller (PIC) Registers ........................................................... 36012.5.1 Interrupt Controller I/O MAP ................................................................ 36012.5.2 ICW1—Initialization Command Word 1 Register ...................................... 36112.5.3 ICW2—Initialization Command Word 2 Register ...................................... 36112.5.4 ICW3—Master Controller Initialization Command

Word 3 Register ................................................................................. 36212.5.5 ICW3—Slave Controller Initialization Command

Word 3 Register ................................................................................. 36212.5.6 ICW4—Initialization Command Word 4 Register ...................................... 36312.5.7 OCW1—Operational Control Word 1 (Interrupt Mask)

Register ............................................................................................ 36312.5.8 OCW2—Operational Control Word 2 Register .......................................... 36412.5.9 OCW3—Operational Control Word 3 Register .......................................... 36412.5.10 ELCR1—Master Controller Edge/Level Triggered Register ......................... 36512.5.11 ELCR2—Slave Controller Edge/Level Triggered Register ........................... 366

12.6 Advanced Programmable Interrupt Controller (APIC)............................................ 36712.6.1 APIC Register Map .............................................................................. 36712.6.2 IND—Index Register ........................................................................... 36712.6.3 DAT—Data Register ............................................................................ 36812.6.4 EOIR—EOI Register ............................................................................ 36812.6.5 ID—Identification Register ................................................................... 36912.6.6 VER—Version Register......................................................................... 36912.6.7 REDIR_TBL—Redirection Table Register ................................................. 370

12.7 Real Time Clock Registers................................................................................. 372

xii Intel® C610 Series Chipset and Intel® X99 ChipsetPlatform Controller Hub (PCH) Datasheet

12.7.1 I/O Register Address Map ....................................................................37212.7.2 Indexed Registers ...............................................................................372

12.8 Processor Interface Registers ............................................................................37512.8.1 NMI_SC—NMI Status and Control Register .............................................37512.8.2 NMI_EN—NMI Enable (and Real Time Clock Index)

Register.............................................................................................37612.8.3 PORT92—Init Register .........................................................................37612.8.4 COPROC_ERR—Coprocessor Error Register .............................................37712.8.5 RST_CNT—Reset Control Register .........................................................377

12.9 Power Management Registers............................................................................37812.9.1 Power Management PCI Configuration Registers

(PM—D31:F0).....................................................................................37812.9.2 APM I/O Decode Register .....................................................................38612.9.3 Power Management I/O Registers .........................................................386

12.10 System Management TCO Registers ...................................................................40212.10.1 TCO_RLD—TCO Timer Reload and Current Value Register.........................40212.10.2 TCO_DAT_IN—TCO Data In Register......................................................40312.10.3 TCO_DAT_OUT—TCO Data Out Register .................................................40312.10.4 TCO1_STS—TCO1 Status Register.........................................................40312.10.5 TCO2_STS—TCO2 Status Register.........................................................40412.10.6 TCO1_CNT—TCO1 Control Register .......................................................40512.10.7 TCO2_CNT—TCO2 Control Register .......................................................40612.10.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers......................................40712.10.9 TCO_WDCNT—TCO Watchdog Control Register .......................................40712.10.10SW_IRQ_GEN—Software IRQ Generation Register ...................................40712.10.11TCO_TMR—TCO Timer Initial Value Register ...........................................407

12.11 General Purpose I/O Registers...........................................................................40812.11.1 GPIO_USE_SEL—GPIO Use Select Register .............................................40912.11.2 GP_IO_SEL—GPIO Input/Output Select Register .....................................40912.11.3 GP_LVL—GPIO Level for Input or Output Register....................................40912.11.4 GPO_BLINK—GPO Blink Enable Register.................................................41012.11.5 GP_SER_BLINK—GP Serial Blink Register ...............................................41012.11.6 GP_SB_CMDSTS—GP Serial Blink Command

Status Register...................................................................................41012.11.7 GP_SB_DATA—GP Serial Blink Data Register ..........................................41112.11.8 GPI_NMI_EN—GPI NMI Enable Register .................................................41112.11.9 GPI_NMI_STS—GPI NMI Status Register ................................................41212.11.10GPI_INV — GPIO Signal Invert Register .................................................41212.11.11GPIO_USE_SEL2—GPIO Use Select 2 Register.........................................41312.11.12GP_IO_SEL2—GPIO Input/Output Select 2 Register .................................41312.11.13GP_LVL2—GPIO Level for Input or Output 2 Register ...............................41412.11.14GPIO_USE_SEL3—GPIO Use Select 3 Register.........................................41412.11.15GP_IO_SEL3—GPIO Input/Output Select 3 Register .................................41512.11.16GP_LVL3—GPIO Level for Input or Output 3 Register ...............................41512.11.17GPI_INV2 — GPIO Signal Invert Register 2.............................................41612.11.18GP_RST_SEL1 — GPIO Reset Select Register ..........................................41612.11.19GP_RST_SEL2 — GPIO Reset Select Register ..........................................41712.11.20GP_RST_SEL3 — GPIO Reset Select Register ..........................................417

12.12 GPIO Serial Expander MMIO Registers ................................................................41812.12.1 GSX_CxCAP — GSX Capabilities Register 1 .............................................41812.12.2 GSX_CxCAP2 — GSX Capabilities Register 2 ...........................................41812.12.3 GSX_CxGPILVL — GSX Input Level Register DW0....................................41912.12.4 GSX_CxGPILVL_DW1 — GSX Input Level Register DW1............................41912.12.5 GSX_CxGPOLVL — GSX Output Level Register DW0.................................41912.12.6 GSX_CxGPOLVL_DW1 — GSX Output Level Register DW1 ........................42012.12.7 GSX_CxCMD — GSX Command Register.................................................420

Intel® C610 Series Chipset and Intel® X99 Chipset xiiiPlatform Controller Hub (PCH) Datasheet

13 SATA Controller Registers (D31:F2)....................................................................... 42113.1 PCI Configuration Registers (SATA–D31:F2)........................................................ 421

13.1.1 VID—Vendor Identification Register (SATA—D31:F2)............................... 42313.1.2 DID—Device Identification Register (SATA—D31:F2) ............................... 42313.1.3 PCICMD—PCI Command Register (SATA–D31:F2) ................................... 42313.1.4 PCISTS—PCI Status Register (SATA–D31:F2) ......................................... 42413.1.5 RID—Revision Identification Register (SATA—D31:F2) ............................. 42413.1.6 PI—Programming Interface Register (SATA–D31:F2)............................... 42513.1.7 SCC—Sub Class Code Register (SATA–D31:F2)....................................... 42613.1.8 BCC—Base Class Code Register (SATA–D31:F2) ..................................... 42613.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F2).................................................................................. 42613.1.10 HTYPE—Header Type Register (SATA–D31:F2) ....................................... 42613.1.11 PCMD_BAR—Primary Command Block Base Address

Register (SATA–D31:F2) ..................................................................... 42713.1.12 PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F2).................................................................................. 42713.1.13 SCMD_BAR—Secondary Command Block Base Address

Register (SATA–D31:F2) ..................................................................... 42713.1.14 SCNL_BAR—Secondary Control Block Base Address

Register (SATA–D31:F2) ..................................................................... 42813.1.15 BAR—Legacy Bus Master Base Address Register

(SATA–D31:F2).................................................................................. 42813.1.16 ABAR/SIDPBA1—AHCI Base Address Register/Serial ATA

Index Data Pair Base Address (SATA–D31:F2)........................................ 42813.1.17 SVID—Subsystem Vendor Identification Register

(SATA–D31:F2).................................................................................. 42913.1.18 SID—Subsystem Identification Register (SATA–D31:F2) .......................... 42913.1.19 CAP—Capabilities Pointer Register (SATA–D31:F2).................................. 43013.1.20 INT_LN—Interrupt Line Register (SATA–D31:F2) .................................... 43013.1.21 INT_PN—Interrupt Pin Register (SATA–D31:F2)...................................... 43013.1.22 IDE_TIM—IDE Timing Register (SATA–D31:F2) ...................................... 43013.1.23 SIDETIM—Slave IDE Timing Register (SATA–D31:F2).............................. 43113.1.24 SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F2).................................................................................. 43113.1.25 SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F2).................................................................................. 43113.1.26 IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F2).................................................................................. 43213.1.27 PID—PCI Power Management Capability Identification

Register (SATA–D31:F2) ..................................................................... 43213.1.28 PC—PCI Power Management Capabilities Register

(SATA–D31:F2).................................................................................. 43213.1.29 PMCS—PCI Power Management Control and Status

Register (SATA–D31:F2) ..................................................................... 43313.1.30 MSICI—Message Signaled Interrupt Capability

Identification Register (SATA–D31:F2) .................................................. 43413.1.31 MSIMC—Message Signaled Interrupt Message

Control Register (SATA–D31:F2) .......................................................... 43413.1.32 MSIMA— Message Signaled Interrupt Message

Address Register (SATA–D31:F2) ......................................................... 43513.1.33 MSIMD—Message Signaled Interrupt Message

Data Register (SATA–D31:F2) .............................................................. 43513.1.34 MAP—Address Map Register (SATA–D31:F2) .......................................... 43513.1.35 PCS—Port Control and Status Register (SATA–D31:F2)............................ 43613.1.36 SCLKCG—SATA Clock Gating Control Register ........................................ 43813.1.37 SGC—SATA General Configuration Register ............................................ 43813.1.38 SIRI—SATA Initialization Registers Index............................................... 439

xiv Intel® C610 Series Chipset and Intel® X99 ChipsetPlatform Controller Hub (PCH) Datasheet

13.1.39 SIRD—SATA Initialization Register Data .................................................43913.1.40 SATACR0—SATA Capability Register 0 (SATA–D31:F2).............................44013.1.41 SATACR1—SATA Capability Register 1 (SATA–D31:F2).............................44013.1.42 FLRCID—FLR Capability ID Register (SATA–D31:F2) ................................44113.1.43 FLRCLV—FLR Capability Length and Version Register (SATA–D31:F2).........44113.1.44 FLRC—FLR Control Register (SATA–D31:F2) ...........................................44213.1.45 ATC—APM Trapping Control Register (SATA–D31:F2)...............................44213.1.46 ATS—APM Trapping Status Register (SATA–D31:F2) ................................44213.1.47 SP—Scratch Pad Register (SATA–D31:F2) ..............................................44313.1.48 BFCS—BIST FIS Control/Status Register (SATA–D31:F2)..........................44313.1.49 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2).......................44413.1.50 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2).......................444

13.2 Bus Master IDE I/O Registers (D31:F2)...............................................................44513.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2).........................44513.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2)..............................44613.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

Register (D31:F2) ...............................................................................44713.2.4 AIR—AHCI Index Register (D31:F2) ......................................................44713.2.5 AIDR—AHCI Index Data Register (D31:F2).............................................447

13.3 Serial ATA Index/Data Pair Superset Registers.....................................................44813.3.1 SINDX—Serial ATA Index Register (D31:F2) ...........................................44813.3.2 SDATA—Serial ATA Data Register (D31:F2) ............................................448

13.4 AHCI Registers (D31:F2) ..................................................................................45213.4.1 AHCI Generic Host Control Registers (D31:F2) ........................................45213.4.2 Port Registers (D31:F2) .......................................................................460

14 SATA Controller Registers (D31:F5) .......................................................................47514.1 PCI Configuration Registers (SATA–D31:F5) ........................................................475

14.1.1 VID—Vendor Identification Register (SATA—D31:F5) ...............................47614.1.2 DID—Device Identification Register (SATA—D31:F5) ...............................47614.1.3 PCICMD—PCI Command Register (SATA–D31:F5) ...................................47714.1.4 PCISTS — PCI Status Register (SATA–D31:F5) .......................................47714.1.5 RID—Revision Identification Register (SATA—D31:F5) .............................47814.1.6 PI—Programming Interface Register (SATA–D31:F5) ...............................47814.1.7 SCC—Sub Class Code Register (SATA–D31:F5) .......................................47914.1.8 BCC—Base Class Code Register (SATA–D31:F5)......................................47914.1.9 PCMD_BAR—Primary Command Block Base Address

Register (SATA–D31:F5) ......................................................................47914.1.10 PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F5) ..................................................................................47914.1.11 SCMD_BAR—Secondary Command Block Base Address

Register (SATA D31:F5).......................................................................48014.1.12 SCNL_BAR—Secondary Control Block Base Address

Register (SATA D31:F5).......................................................................48014.1.13 BAR — Legacy Bus Master Base Address Register

(SATA–D31:F5) ..................................................................................48014.1.14 SIDPBA — SATA Index/Data Pair Base Address Register

(SATA–D31:F5) ..................................................................................48114.1.15 SVID—Subsystem Vendor Identification Register

(SATA–D31:F5) ..................................................................................48114.1.16 SID—Subsystem Identification Register (SATA–D31:F5)...........................48114.1.17 CAP—Capabilities Pointer Register (SATA–D31:F5) ..................................48114.1.18 INT_LN—Interrupt Line Register (SATA–D31:F5).....................................48214.1.19 INT_PN—Interrupt Pin Register (SATA–D31:F5) ......................................48214.1.20 IDE_TIM—IDE Timing Register (SATA–D31:F5) .......................................48214.1.21 SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F5) ..................................................................................482

Intel® C610 Series Chipset and Intel® X99 Chipset xvPlatform Controller Hub (PCH) Datasheet

14.1.22 SDMA_TIM—Synchronous DMA Timing Register (SATA–D31:F5).................................................................................. 483

14.1.23 IDE_CONFIG—IDE I/O Configuration Register (SATA–D31:F5).................................................................................. 483

14.1.24 PID—PCI Power Management Capability IdentificationRegister (SATA–D31:F5) ..................................................................... 484

14.1.25 PC—PCI Power Management Capabilities Register (SATA–D31:F5).................................................................................. 484

14.1.26 PMCS—PCI Power Management Control and StatusRegister (SATA–D31:F5) ..................................................................... 485

14.1.27 MAP—Address Map Register (SATA–D31:F5) .......................................... 48614.1.28 PCS—Port Control and Status Register (SATA–D31:F5)............................ 48614.1.29 SATACR0— SATA Capability Register 0 (SATA–D31:F5) ........................... 48714.1.30 SATACR1— SATA Capability Register 1 (SATA–D31:F5) ........................... 48714.1.31 FLRCID— FLR Capability ID Register (SATA–D31:F5)............................... 48814.1.32 FLRCLV— FLR Capability Length and

Value Register (SATA–D31:F5)............................................................. 48814.1.33 FLRCTRL— FLR Control Register (SATA–D31:F5)..................................... 48814.1.34 ATC—APM Trapping Control Register (SATA–D31:F5) .............................. 48914.1.35 ATC—APM Trapping Control Register (SATA–D31:F5) .............................. 489

14.2 Bus Master IDE I/O Registers (D31:F5) .............................................................. 48914.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5) ........................ 49014.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5) ............................. 49014.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

Register (D31:F5)............................................................................... 49114.3 Serial ATA Index/Data Pair Superset Registers .................................................... 492

14.3.1 SINDX—SATA Index Register (D31:F5).................................................. 49214.3.2 SDATA—SATA Index Data Register (D31:F5).......................................... 492

15 sSATA Controller Registers (D17:F4) ..................................................................... 49715.1 PCI Configuration Registers (sSATA–D17:F4) ...................................................... 497

15.1.1 VID—Vendor Identification Register (sSATA—D17:F4) ............................. 49815.1.2 DID—Device Identification Register (sSATA—D17:F4).............................. 49915.1.3 PCICMD—PCI Command Register (sSATA–D17:F4) ................................. 49915.1.4 PCISTS — PCI Status Register (sSATA–D17:F4)...................................... 49915.1.5 RID—Revision Identification Register (sSATA—D17:F4)............................ 50015.1.6 PI—Programming Interface Register (sSATA–D17:F4) ............................. 50015.1.7 SCC—Sub Class Code Register (sSATA–D17:F4) ..................................... 50115.1.8 BCC—Base Class Code Register

(sSATA–D17:F4) ................................................................................ 50215.1.9 PMLT—Primary Master Latency Timer Register

(sSATA–D17:F4) ................................................................................ 50215.1.10 HTYPE—Header Type Register

(sSATA–D17:F4) ................................................................................ 50215.1.11 PCMD_BAR—Primary Command Block Base Address

Register (sSATA–D17:F4) .................................................................... 50215.1.12 PCNL_BAR—Primary Control Block Base Address Register

(sSATA–D17:F4) ................................................................................ 50315.1.13 SCMD_BAR—Secondary Command Block Base Address

Register (sSATA D17:F4)..................................................................... 50315.1.14 SCNL_BAR—Secondary Control Block Base Address

Register (sSATA D17:F4)..................................................................... 50315.1.15 BAR—Legacy Bus Master Base Address Register

(sSATA–D17:F4) ................................................................................ 50415.1.16 ABAR/SIDPBA1—AHCI Base Address Register/Serial ATA

Index Data Pair Base Address (sSATA–D17:F4) ...................................... 50415.1.17 SVID—Subsystem Vendor Identification Register

(sSATA–D17:F4) ................................................................................ 505

xvi Intel® C610 Series Chipset and Intel® X99 ChipsetPlatform Controller Hub (PCH) Datasheet

15.1.18 SID—Subsystem Identification Register (sSATA–D17:F4) .........................50515.1.19 CAP—Capabilities Pointer Register (sSATA–D17:F4).................................50515.1.20 INT_LN—Interrupt Line Register (sSATA–D17:F4) ...................................50515.1.21 INT_PN—Interrupt Pin Register (sSATA–D17:F4).....................................50615.1.22 IDE_TIM—IDE Timing Register (sSATA–D17:F4)......................................50615.1.23 SIDETIM—Slave IDE Timing Register (sSATA–D17:F4).............................50615.1.24 SDMA_CNT—Synchronous DMA Control Register

(sSATA–D17:F4).................................................................................50715.1.25 SDMA_TIM—Synchronous DMA Timing Register

(sSATA–D17:F4).................................................................................50715.1.26 IDE_CONFIG—IDE I/O Configuration Register

(sSATA–D17:F4).................................................................................50715.1.27 PID—PCI Power Management Capability Identification

Register (sSATA–D17:F4) ....................................................................50815.1.28 PC—PCI Power Management Capabilities Register

(sSATA–D17:F4).................................................................................50815.1.29 PMCS—PCI Power Management Control and Status

Register (sSATA–D17:F4) ....................................................................50915.1.30 MSICI—Message Signaled Interrupt Capability

Identification Register (sSATA–D17:F4) .................................................50915.1.31 MSIMC—Message Signaled Interrupt Message

Control Register (sSATA–D17:F4) .........................................................51015.1.32 MSIMA— Message Signaled Interrupt Message

Address Register (sSATA–D17:F4) ........................................................51015.1.33 MSIMD—Message Signaled Interrupt Message

Data Register (sSATA–D17:F4) .............................................................51115.1.34 MAP—Address Map Register (sSATA–D17:F4) .........................................51115.1.35 PCS—Port Control and Status Register (sSATA–D17:F4)...........................51215.1.36 SCLKCG—sSATA Clock Gating Control Register .......................................51315.1.37 SGC—sSATA General Configuration Register ...........................................51315.1.38 SIRI—sSATA Initialization Registers Index..............................................51415.1.39 STRD—sSATA Initialization Register Data ...............................................51415.1.40 sSATACR0—sSATA Capability Register 0 (sSATA–D17:F4) ........................51515.1.41 sSATACR1—sSATA Capability Register 1 (sSATA–D17:F4) ........................51515.1.42 FLRCID—FLR Capability ID Register (sSATA–D17:F4)...............................51615.1.43 FLRCLV—FLR Capability Length and Version Register (sSATA–D17:F4) .......51615.1.44 FLRC—FLR Control Register (sSATA–D17:F4)..........................................51615.1.45 ATC—APM Trapping Control Register (sSATA–D17:F4) .............................51715.1.46 ATS—APM Trapping Status Register (sSATA–D17:F4) ..............................51715.1.47 SP Scratch Pad Register (sSATA–D17:F4)...............................................51715.1.48 BFCS—BIST FIS Control/Status Register (sSATA–D17:F4) ........................51815.1.49 BFTD1—BIST FIS Transmit Data1 Register (sSATA–D17:F4) .....................51915.1.50 BFTD2—BIST FIS Transmit Data2 Register (sSATA–D17:F4) .....................519

15.2 Bus Master IDE I/O Registers (D17:F4)...............................................................51915.2.1 BMIC[P,S]—Bus Master IDE Command Register (D17:F4).........................52015.2.2 BMIS[P,S]—Bus Master IDE Status Register (D17:F4)..............................52015.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

Register (D17:F4) ...............................................................................52115.2.4 AIR—AHCI Index Register (D17:F4) ......................................................52115.2.5 AIDR—AHCI Index Data Register (D17:F4).............................................522

15.3 Serial ATA Index/Data Pair Superset Registers.....................................................52215.3.1 SINDX—Serial ATA Index Register (D17:F4) ...........................................52215.3.2 SDATA—Serial ATA Data Register (D17:F4) ............................................523

15.4 AHCI Registers (D17:F4) ..................................................................................52615.4.1 AHCI Generic Host Control Registers (D17:F4) ........................................52715.4.2 Port Registers (D17:F4) .......................................................................533

Intel® C610 Series Chipset and Intel® X99 Chipset xviiPlatform Controller Hub (PCH) Datasheet

16 EHCI Controller Registers (D29:F0, D26:F0) .......................................................... 54716.1 USB EHCI Configuration Registers

(USB EHCI—D29:F0, D26:F0) ........................................................................... 54716.1.1 VID—Vendor Identification Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 54816.1.2 DID—Device Identification Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 54816.1.3 PCICMD—PCI Command Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 54916.1.4 PCISTS—PCI Status Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55016.1.5 RID—Revision Identification Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55116.1.6 PI—Programming Interface Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55116.1.7 SCC—Sub Class Code Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55116.1.8 BCC—Base Class Code Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55116.1.9 PMLT—Primary Master Latency Timer Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55216.1.10 HEADTYP—Header Type Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55216.1.11 MEM_BASE—Memory Base Address Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55216.1.12 SVID—USB EHCI Subsystem Vendor ID Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55316.1.13 SID—USB EHCI Subsystem ID Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55316.1.14 CAP_PTR—Capabilities Pointer Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55316.1.15 INT_LN—Interrupt Line Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55316.1.16 INT_PN—Interrupt Pin Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55416.1.17 PWR_CAPID—PCI Power Management Capability ID

Register (USB EHCI—D29:F0, D26:F0) .................................................. 55416.1.18 NXT_PTR1—Next Item Pointer #1 Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55416.1.19 PWR_CAP—Power Management Capabilities Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55516.1.20 PWR_CNTL_STS—Power Management Control/

Status Register (USB EHCI—D29:F0, D26:F0) ........................................ 55516.1.21 DEBUG_CAPID—Debug Port Capability ID Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55616.1.22 NXT_PTR2—Next Item Pointer #2 Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55616.1.23 DEBUG_BASE—Debug Port Base Offset Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55616.1.24 USB_RELNUM—USB Release Number Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55716.1.25 FL_ADJ—Frame Length Adjustment Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55716.1.26 PWAKE_CAP—Port Wake Capability Register

(USB EHCI—D29:F0, D26:F0) .............................................................. 55816.1.27 PDO– Port Disable Override ................................................................. 55816.1.28 RMHDEVR– RMH Device Removable Field............................................... 55916.1.29 LEG_EXT_CAP—USB EHCI Legacy Support Extended

Capability Register (USB EHCI—D29:F0, D26:F0) ................................... 559

xviii Intel® C610 Series Chipset and Intel® X99 ChipsetPlatform Controller Hub (PCH) Datasheet

16.1.30 LEG_EXT_CS—USB EHCI Legacy Support ExtendedControl / Status Register (USB EHCI—D29:F0, D26:F0) ...........................560

16.1.31 SPECIAL_SMI—Intel Specific USB 2.0 SMI Register (USB EHCI—D29:F0, D26:F0)...............................................................561

16.1.32 OCMAP—Over-Current Mapping Register ................................................56216.1.33 RMHWKCTL—RMH Wake Control Register ...............................................56416.1.34 ACCESS_CNTL—Access Control Register

(USB EHCI—D29:F0, D26:F0)...............................................................56416.1.35 EHCIIR1—EHCI Initialization Register 1

(USB EHCI—D29:F0, D26:F0)...............................................................56516.1.36 EHCIIR2—EHCI Initialization Register 2 (USB EHCI—D29:F0, D26:F0)........56516.1.37 FLR_CID—Function Level Reset Capability ID Register

(USB EHCI—D29:F0, D26:F0)...............................................................56616.1.38 FLR_NEXT—Function Level Reset Next Capability

Pointer Register (USB EHCI—D29:F0, D26:F0)........................................56616.1.39 FLR_CLV—Function Level Reset Capability Length and

Version Register (USB EHCI—D29:F0, D26:F0) .......................................56616.1.40 FLR_CTRL—Function Level Reset Control Register

(USB EHCI—D29:F0, D26:F0)...............................................................56616.1.41 FLR_STS—Function Level Reset Status Register

(USB EHCI—D29:F0, D26:F0)...............................................................56716.1.42 EHCIIR3—EHCI Initialization Register 3

(USB EHCI—D29:F0, D26:F0)...............................................................56716.1.43 EHCIIR4—EHCI Initialization Register 4

(USB EHCI—D29:F0, D26:F0)...............................................................56716.2 Memory-Mapped I/O Registers ..........................................................................568

16.2.1 Host Controller Capability Registers .......................................................56816.2.2 Host Controller Operational Registers ....................................................57116.2.3 USB 2.0-Based Debug Port Registers .....................................................581

17 xHCI Controller Registers (D20:F0)........................................................................58517.1 USB xHCI Configuration Registers

(USB xHCI—D20:F0)........................................................................................58517.1.1 VID—Vendor Identification Register

(USB xHCI—D20:F0) ...........................................................................58617.1.2 DID—Device Identification Register

(USB xHCI—D20:F0) ...........................................................................58617.1.3 PCICMD—PCI Command Register

(USB xHCI—D20:F0) ...........................................................................58717.1.4 PCISTS—PCI Status Register

(USB xHCI—D20:F0) ...........................................................................58717.1.5 RID—Revision Identification Register

(USB xHCI—D20:F0) ...........................................................................58817.1.6 PI—Programming Interface Register

(USB xHCI—D20:F0) ...........................................................................58817.1.7 SCC—Sub Class Code Register

(USB xHCI—D20:F0) ...........................................................................58917.1.8 BCC—Base Class Code Register

(USB xHCI—D20:F0) ...........................................................................58917.1.9 PMLT—Primary Master Latency Timer Register

(USB xHCI—D20:F0) ....