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PHY Lite for Parallel Interfaces IntelFPGA IP Core User Guide

Updated for Intel® Quartus® Prime Design Suite: 18.0

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Contents

About the PHY Lite for Parallel Interfaces IP Core.............................................................. 4Device Family Support.................................................................................................. 4Features..................................................................................................................... 4

Functional Description........................................................................................................ 6Top Level Interfaces..................................................................................................... 8Clocks.......................................................................................................................10

Clock Frequency Relationships............................................................................ 11Output Path...............................................................................................................12

Output Path Data Alignment............................................................................... 13Input Path.................................................................................................................14

Input Path Data Alignment................................................................................. 16Dynamic Reconfiguration.............................................................................................17

RTL Connectivity............................................................................................... 17Reconfiguration Features and Register Addressing................................................. 18Calibration Guidelines........................................................................................ 38

Getting Started................................................................................................................. 41Parameter Settings.....................................................................................................41

Read Latency....................................................................................................48Write Latency................................................................................................... 48

Signals..................................................................................................................... 49Clock and Reset Interface Signals........................................................................49Output Path Signals...........................................................................................49Input Path Signals.............................................................................................50Avalon Configuration Bus Interface Signals........................................................... 52

I/O Standards...................................................................................................................54Input Buffer Reference Voltage (VREF).......................................................................... 57

Calibrated VREF Settings....................................................................................58On-Chip Termination (OCT)..........................................................................................60

Design Guidelines............................................................................................................. 62Guidelines: Group Pin Placement.................................................................................. 62Reference Clock......................................................................................................... 63Reset........................................................................................................................63Constraining Multiple PHY Lite for Parallel Interfaces Interfaces to One I/O Bank.................63Dynamic Reconfiguration.............................................................................................63Timing...................................................................................................................... 64

Timing Components...........................................................................................64Timing Constraints and Files............................................................................... 64Timing Analysis.................................................................................................66Timing Closure Guidelines.................................................................................. 66

Design Example................................................................................................................ 68Generate the Design Example...................................................................................... 68

Design Example without Dynamic Reconfiguration................................................. 69Dynamic Reconfiguration Design Examples........................................................... 70

Contents

PHY Lite for Parallel Interfaces Intel FPGA IP Core User Guide2

Application Specific Design Example.................................................................................82Implementation using the PHY Lite for Parallel Interfaces IP Core......................................82

PHY Lite for Parallel Interfaces IP Core User Guide Document Archives........................... 86

Document Revision History for PHY Lite for Parallel Interfaces IP Core User Guide .........87

Contents


About the PHY Lite for Parallel Interfaces IP CoreThis user guide describes the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGAIP, PHY Lite for Parallel Interfaces Intel Arria® 10 FPGA IP, and PHY Lite for ParallelInterfaces Intel Cyclone® 10 GX FPGA IP cores. The PHY Lite for Parallel Interfaces IPcore is primarily used for building custom memory interface PHY blocks. You can usethis solution to interface with protocols such as DDR2, LPDDR2, LPDDR, TCAM, Flash,ONFI (Synchronous Mode), and Mobile DDR.

The IP core has a dedicated PHY clock tree in each I/O bank. The PHY clock tree isshorter which yields lower jitter and duty cycle distortion (DCD), enabling designs toachieve higher performance.

In addition, this IP core supports Dynamic Reconfiguration feature which enablesreconfiguration of the data and strobe delays. You can align the data and strobe viacalibration to achieve timing closure at high frequencies.

This IP core controls the strobe-based capture I/O elements. Each instance of the IPcore can support an interface up to 18 individual data/strobe capture groups. Eachgroup can contain up to 48 data I/Os as well as the strobe capture logic.

Related Information

PHY Lite for Parallel Interfaces IP Core User Guide Document Archives on page 86Provides a list of user guides for previous versions of the PHY Lite for ParallelInterfaces Intel FPGA IP core.

Device Family Support

The PHY Lite for Parallel Interfaces IP core supports Intel Stratix 10, Intel Arria 10,and Intel Cyclone 10 GX devices only.

For Arria V, Cyclone V, and Stratix V devices, use the ALTDQ_DQS2 Intel FPGA IP coreinstead.

Related Information

ALTDQ_DQS2 IP Core User GuideFor more information about the ALTDQ_DQS2 IP core

Features

The PHY Lite for Parallel Interfaces IP core:

• Supports input, output, and bidirectional data channels

• Supports DQS-group based data capture, with up to 48 I/Os (including strobes)per group and DQS gating/ungating circuitry for strobe-based interfaces

• Supports output delays via interpolator

ug_altera_phylite | 2018.05.07

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

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• Supports dynamic on-chip termination (OCT) control

• Supports quarter-rate to half-rate and half-rate to full-rate conversions.

• Supports input, output, and read/DQS/OCT enable paths

• Supports single data rate (SDR) and double data rate (DDR) at the I/Os

• Supports PHY clock tree

• Supports dynamically reconfigurable delay chains using Avalon-MM interface

• Supports process, voltage, and temperature (PVT) or non-PVT compensated inputand DQS delay chains

Note: The non-PVT compensated component of the input delay is set throughthe .qsf assignment in the Intel Quartus® Prime software.

About the PHY Lite for Parallel Interfaces IP Core



Functional DescriptionThe PHY Lite for Parallel Interfaces IP core utilizes the I/O subsystem in the IntelStratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices. The I/O subsystem islocated in the I/O columns of each Intel FPGA devices. For Intel Stratix 10 devices,each column consists of I/O banks and IOSSM. For Intel Arria 10 and Intel Cyclone 10GX devices, each column consists of I/O banks and I/O aux. The number of I/O banksvaries according to device packages. Each bank is a group of 48 I/O pins, organizedinto four I/O lanes with 12 pins for each lane. Each I/O lane contains the DDR-PHYinput and output path logic for 12 I/Os as well as a DQS logic block. All four lanes in abank can be combined to form a single data/strobe group or up to four groups in thesame interface. Under certain conditions, two groups from different interfaces can alsobe supported in the same bank.

Important: Intel Stratix 10 devices has separate LVDS I/O bank and 3 V I/O banks. The PHY Litefor Parallel Interfaces IP core utilizes only the LVDS I/O banks.

Figure 1. Intel Stratix 10 I/O Bank Structure

3A

3B

3C

3D

3I

3J

3K

3L

3M

3N

3E

3F

3G

3H

5A

5B

5C

5D

5I

5J

5K

5L

5M

5N

5E

5F

5G

5H

2A

2B

2C

2D

2E

2F

2G

2H

2I

2J

2K

2L

2M

2N

6A

6B

6C

SDM

I/O Lane

I/O Lane

I/O Center

I/O PLL

Hard MemoryController

andPHY Sequencer

I/O DLL

I/O DLL

Clock

Net

work

OCTI/O VR

I/O Lane

LVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer Pair




SERDES & DPASERDES & DPASERDES & DPASERDES & DPASERDES & DPASERDES & DPA




I/O Lane

Secure Device Manager (SDM)Shared LVDS I/O

3 V I/O LVDS I/O

I/O DLL

I/O DLL







Figure 2. Intel Arria 10 I/O Bank Structure

2L

2K

2J

2I

2H

2G

2F

2A

3H

3G

3F

3E

3D

3C

3B

3A

Trans

ceive

r Bloc

k

Trans

ceive

r Bloc

k

TransceiverBlock

I/OColumn

BankControl

I/OColumn

IndividualI/O Banks



I/O Lane



I/O Lane

I/O Center

I/O PLL Hard Memory Controllerand

PHY Sequencer

I/O DLL I/O CLK

OCT VR



I/O Lane



I/O Lane

Figure 3. Intel Cyclone 10 GX I/O Bank Structure

2L

2K

2J

2A

3A

3B

Trans

ceive

r Bloc

k

3 V I/O

LVDS I/O



I/O Lane



I/O Lane

I/O Center

I/O PLL Hard Memory Controllerand

PHY Sequencer

I/O DLL I/O CLK

OCT VR



I/O Lane



I/O Lane

Functional Description



Intel Arria 10 and Intel Cyclone 10 GX devices do not have separate LVDS I/O and 3 VI/O banks.

Related Information

• Design Guidelines on page 62For more information about placement restrictions

• Intel Arria 10 External Memory Interfaces IP User GuideFor more information about the architecture

• Intel Stratix 10 External Memory Interfaces IP User GuideFor more information about the architecture

• Intel Cyclone 10 External Memory Interfaces IP User GuideFor more information about the architecture

• Constraining Multiple PHY Lite for Parallel Interfaces Interfaces to One I/O Bank onpage 63

Top Level Interfaces

The PHY Lite for Parallel Interfaces IP core consists of the following ports:

• Clocks and reset

• Core data and control (broken down into input and output paths)

• I/O (broken down into input and output paths)

• Avalon-MM configuration bus (available only when Dynamic Reconfigurationfeature is enabled)

Figure 4. Top-Level InterfaceThis figure shows the top-level diagram of the PHY Lite for Parallel Interfaces IP core interface.

PLLI/O Lane

I/O Lane

Tile Control

I/O Lane

I/O LaneVCO/Interpolator

phy_clkphy_clk_phs

core_clk_out

strobe_in/out/io

data_in/out/ioData to/from Core

Group

ref_clk

Reference ClockCore Clock

PHY ClockInterface Clock

Legend

Intel FPGA Core Logic

(From external oscillator)

(From /to external devices)

Intel FPGA Device

PHY Lite for Parallel Interfaces IP Core

Related Information

• Output Path on page 12For more information about the output path

• Input Path on page 14For more information about the input path




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• Signals on page 49For more information about core data, control, and I/O interfaces signals




Clocks

The PHY Lite for Parallel Interfaces IP core uses a reference clock that is sourced froma dedicated clock pin to the PLL inside the IP core. This PLL provides four clockdomains for the output and input paths.

Table 1. PHY Lite for Parallel Interfaces IP Core Clock Domains

Clock Domain Description

Core clock This clock is generated internally by the IP core and it is used for all transfers between the FPGAcore fabric and I/O banks. The clock phase alignment circuitry ensures that this clock is kept inphase with the PHY clock for core-to-periphery and periphery-to-core transfers.

PHY clock This clock is used internally by the IP core for PHY circuitry running at the same frequency asthe core clock.

VCO clock This clock is generated internally by the PLL. It is used by both the input and output paths togenerate PVT compensated delays in the interpolator.

Interface clock This is the clock frequency of the external device connected to the FPGA I/Os .

Table 2. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Core SupportedInterface FrequencyUse the Timing Analyzer to perform timing closure to ensure your design fulfilled all timing constraints with thesupported frequencies indicated in the table.

Core ClockRate

Speed Grade –1 (MHz) Speed Grade –2 (MHz) Speed Grade –3 (MHz)

Min Max Min Max Min Max

Full 100 333 100 300 100 233

Half 100 667 100 600 100 467

Quarter 100 1200 100 1200 100 933

Table 3. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP Core SupportedInterface FrequencyUse the Timing Analyzer to perform timing closure to ensure your design fulfilled all timing constraints with thesupported frequencies indicated in the table.

Core ClockRate

Speed Grade –1 (MHz) Speed Grade –2 (MHz) Speed Grade –3 (MHz)

Min Max Min Max Min Max

Full 100 333 100 266 100 233

Half 100 667 100 533 100 466

Quarter 100 1200 100 1067 100 933

Table 4. PHY Lite for Parallel Interfaces Intel Cyclone 10 GX FPGA IP Core SupportedInterface FrequencyUse the Timing Analyzer to perform timing closure to ensure your design fulfilled all timing constraints with thesupported frequencies indicated in the table.

Core Clock Rate Speed Grade –5 (MHz) Speed Grade –6 (MHz)

Min Max Min Max

Full 100 266 100 233

Half 100 533 100 466

Quarter 100 1067 100 933




Clock Frequency Relationships

The following equations describe the relationships between the clock domainsavailable in the PHY Lite for Parallel Interfaces IP core.

Core Clock Rate = Interface clock frequency / Core clock frequency

VCO frequency Multiplier Factor = VCO clock frequency(1) / Interface clock frequency

(1) You can obtain this value from the VCO clock frequency parameter under General Tab in theIP parameter editor.




Output Path

The output path consists of a FIFO and an interpolator.

Figure 5. Output PathThis figure shows the output path for the PHY Lite for Parallel Interfaces IP core.

Write FIFO data_io data_out

oe_outoct_out

Interpolator

interpolator_clk

data_from_coreoe_from_core

phy_clk

VCO clock

output_strobe_inoutput_strobe_en

strobe_outstrobe_io

Table 5. Blocks in Output PathThis table lists the blocks in the output path.

Block Description

Write FIFO Serializes the output data from the core with a serialization factor of up to 8 (in DDR quarter-rate).

Interpolator Works with the FIFO block to generate the desired output delay. You can dynamically configurethe delay through the Avalon-MM interface. For more information, refer to DynamicReconfiguration section.

The following figures show the waveform diagrams for the output path.




Figure 6. Output Path Write Latency 0

Figure 7. Output Path Write Latency 3

Related Information

• Output Path Signals on page 49For more information about output path signals

• Dynamic Reconfiguration on page 17

Output Path Data Alignment

The data_from_core and oe_from_core signals are arranged in time slices, whichare broken down into the individual pins in the group. The first time slice is on theLSBs of the buses, which matches the Intel FPGA PHY interface (AFI) bus ordering ofthe External Memory Interfaces IP core.

Example of time slices with individual pins correlation:

time(n),time(n-1),time(n-2),... time(0)

Where time0 = pin(n),pin(n-1),pin(n-2),...pin0




Figure 8. Example Output for Quarter Rate DDR

Related Information

• Dynamic Reconfiguration on page 17

• External Memory Interface Handbook Volume 3: Reference Material (AFI 3.0Specification)

Input Path

The input path of the IP core consists of a data path, a strobe path, and a read enablepath.

Table 6. Blocks in Data, Strobe, and Read Enable PathsThis table lists the information about these paths.

Path Description

Data Path Consists of a PVT compensated delay chain, a DDIO and a read FIFO.• PVT compensated delay chain—Allows per-bit deskew. You can only control the PVT compensated

delay chain over Avalon-MM interface. For more information, refer to Dynamic Reconfiguration.• DDIO and read FIFO—Responsible for deserialization with a factor of up to 8 (in DDR quarter-rate).

The transfer between the DDIO and the read FIFO is a zero-cycle transfer.The IP core supports SDR input by dropping every other bit of data going to the core.

Strobe Path Consists of pstamble_reg (a gating component) and a PVT compensated delay chain.• pstamble_reg—This gating circuitry ensures that only clock edges associated with valid input data are

used.• PVT compensated delay chain—Provides a phase offset between the strobe and the data (for

example, center aligning edge-aligned inputs).

Read EnablePath

Consists of VFIFO, DQS_EN FIFO, and an interpolator.• VFIFO—takes the rdata_en signal from the core and delays it separately for two outputs, one for

the read enable on the read FIFO, and one for the strobe enable. These delays are calculated atgeneration time based on the read latency that you provide. Individual control is not necessary, but ifyou are modifying these delays you can do so individually using dynamic reconfiguration.

• DQS_EN FIFO and interpolator—used for the strobe enable delay, the DQS_EN FIFO and interpolatorare identical to the Write FIFO and interpolator circuitry in the output path. The DQS_EN FIFO andinterpolator are configured to match the output delay for a group with no additional output delay(Write latency = 0). During dynamic reconfiguration, the DQS_EN FIFO and interpolator can be usedfor fine grained control of the strobe enable signal. Both of these delays are controlled by the Readlatency parameter for the group.




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Figure 9. Input PathThis figure shows the input path of the IP core.

Read FIFO DDIO Delay Chain (PVT)

data_to_core data_in

phy_clkstrobe_in

dqs

Delay Chain (PVT)

dqs_cleanpstamble_reg

DQS_EN FIFO

Interpolator

interpolator_clk

dqs_enable

phy_clk_phs

VFIFO

read_enable

dqs_enablerdata_en

phy_clk

rdata_valid

data_io

strobe_iostrobe_in_n

6

1 2

34

5 56

n n = sequence number. This represent read operationsequence.

To Intel FPGA core PHY Lite for Parallel Interfaces IP Core To external interface

Table 7. Read Operation SequenceA read operation is performed as listed in this table.

Read OperationSequence Number

Operation

1 The core asserts the rdata_en signal (and the external device is issued a read command)

2 The strobe enable is delayed through VFIFO and DQS_EN FIFO by the programmed read latency(which should match the latency of the external device)

3 The strobe signal is gated by the strobe enable signal as valid data enters the read path

4 The strobe is optionally delayed to create a phase offset between the strobe and the input data(for example, 90° phase shift for DDR center-alignment)

5 The data is clocked into the DDIO and read FIFO by the strobe

6 The VFIFO asserts the read enable on the read FIFO and the rdata_valid signal to the coresimultaneously. This outputs the captured data and the associated valid signal to the core.




Figure 10. Input Path WaveformThis figure shows a waveform diagram of the input path.

Related Information

Input Path Signals on page 50For more information about input path signals

Input Path Data Alignment

The bus ordering of data_to_core, rdata_en, and rdata_valid is identical to theordering of the output path. That is, the LSBs of the bus hold the first time slice ofdata received.

The rdata_valid delay is always set by the IP core to match the rdata_enalignment. For example, quarter-rate delays are multiples of four external memoryclock cycles (one quarter rate clock cycle).

Figure 11. Example Input (Quarter Rate DDR) - AlignedThe waveform shows an example of aligned reads on the input path of the PHY Lite for Parallel Interfaces IPcore. At the first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows data of 4'hf,which represents all incoming data are aligned. The group_0_rdata_valid bus shows the data of 4'hf, whichrepresents all incoming data are valid. Therefore, the incoming read data on the group_0_data_to_core busmatches the data seen on the group_0_data_io bus.

Reading from an unaligned memory address is called unaligned reads. Unalignedreads will result in unaligned rdata_valid and data_to_core with data andvalid signals packed to the LSBs. This request causes the IP core to do two or moreread operations.




Figure 12. Example Input (Quarter Rate DDR) - UnalignedThe waveform shows an example of unaligned reads on the input path of the PHY Lite for Parallel Interfaces IPcore.

The data from an unaligned read operation comes in two phases. At the first rising edge of the core_clk_outsignal, the group_0_rdata_en bus shows value of 4'he, which shows there are 6 bytes of incoming data fromgroup_0_data_io bus. On the subsequent clock cycle, the group_0_rdata_en bus shows value of 4'h1,which shows there are 2 bytes of incoming data from group_0_data_io bus.

The valid data are transfer to the IP core through the group_0_data_to_core bus. At first rising edge of thecore_clk_out signal, group_0_rdata_valid bus shows a value of 4'h7, which represents the first 6 bytesof the data from the group_0_data_to_core bus are valid and the last 2 bytes are invalid. On thesubsequent clock cycle, group_0_rdata_valid bus shows the value of 4'h1, which shows the last 2 bytes ofthe data from the group_0_data_to_core bus are valid.

Dynamic Reconfiguration

Because of the asynchronous nature of the PHY, you must perform calibration toachieve timing closure at a high frequency. At a high level, calibration involvesreconfiguring input and output delays in the PHY to align data and strobes. You canmodify these delays using an Avalon-MM interface by enabling dynamicreconfiguration in the PHY Lite for Parallel Interfaces IP core.

Important: When the dynamic reconfiguration feature is enabled in Intel Stratix 10 devices, themaximum Avalon-MM interface speed is 167 MHz.

Related Information

• Calibrated VREF Settings on page 58

• Timing Closure: Dynamic Reconfiguration on page 66

RTL Connectivity

The PHY Lite for Parallel Interfaces IP core exposes the Avalon-MM master and Avalon-MM slave interfaces when you enable the dynamic reconfiguration feature. If thegenerated IP core is the only PHY Lite for Parallel Interfaces IP core (with dynamicreconfiguration) or External Memory Interface IP core in the I/O column, connect onlythe Avalon-MM slave interface with a master in the core. Otherwise, connect Avalon-MM master and slave interfaces as described in the following section.

Daisy Chain

The I/O column provides a single physical Avalon-MM interface. All IP cores in the I/Ocolumn that require Avalon-MM interface access the same physical Avalon-MMinterface. The system-level RTL for the column reflects this resource limitation byusing a daisy chain to connect all dynamically reconfigurable IP cores in an I/Ocolumn.

The PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP core exposes a 31-bitAvalon-MM address, followed by a 4-bit interface ID. For PHY Lite for ParallelInterfaces Intel Arria 10 FPGA IP and PHY Lite for Parallel Interfaces Intel Cyclone 10GX FPGA IP cores, the Avalon-MM address is 28 bits where the top 4-bits are the ID ofthe interface to be addressed in the daisy chain. These bits are only required for the




daisy chain arbitration in RTL simulation, so they are not synthesized duringcompilation. If only one interface is addressed from the IP core, it is sufficient toconnect these bits as the interface’s ID.

Important: For Intel Stratix 10 devices with multiple PHY Lite for Parallel Interfaces and ExternalMemory Interface with Debug Component IP cores, you are required to specify the IPcore that is directly connected to the Avalon MM bus master, a using the FirstPHYLite Instance in the Avalon Chain parameter.

Figure 13. Logical RTL View to Physical Column PlacementThis figure shows an example of a daisy chain consisting of the External Memory Interface and PHY Lite forParallel Interfaces IP cores before and after placement.

Notice that all core controllers must go through the arbitration logic that you createdin the FPGA core logic to connect to an interface on the daisy chain. The end of thedaisy chain should have its master output interface tied to 0.

Note: The Fitter rearranges the Avalon address pins during compilation, therefore use thepostfit netlist for proper simulation of the merged I/O column instead of prefit netlist.

Reconfiguration Features and Register Addressing

Each reconfigurable feature of the interface has a set of control registers with anassociated memory address to store the reconfigurable settings; however, this addressis placement dependent. If PHY Lite for Parallel Interfaces IP cores and the ExternalMemory Interface IP cores share the same I/O column, you must track the addressesof the interface lanes and the pins.

There are two sets of control registers that store the reconfiguration feature settings:

• Control/Status registers (CSR) - you can only read the values of these registers.The values are set through the IP core parameters. The CSR registers contain thedefault setting in the IP core.

• Avalon® Memory-Mapped registers - you can read and write to these registersusing Avalon interface.

PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Core Control RegistersAddresses

The following tables show the register bits to construct the control register addressesfor each feature.




Table 8. Control Register Address for Pin Output Delay Feature

Bit Description Avalon MM Register CSR Register

Value Access Type Value AccessType

[31] Reserved 1'b0 RW 1'b0 RO

[30:27] Specify the PHY Lite forParallel Interfaces IP coreinterface ID.

Depending on theInterface ID

parameter in theParameter Editor.

RW Depending on theInterface ID


RO

[26:24] Specify the Avaloncontroller calibration busbase address.

3'h3 RW 3'h3 RO

[23:21] Reserved 3'h0 RW 3'h0 RO

[20:13] Specify the lane addressof an interface. This valueis depending on theresource fitting processduring compilation.

You can query thisin the Parameter

Table LookupOperation Sequenceas described in the Address Lookup on

page 34.

RW You can query thisin the Parameter


page 34.

RO

[12:8] Specify the address forthe physical location of apin within a lane.


Table LookupOperation Sequenceas described in the Address Lookup onpage 34 or based

on your pinassignment setting

in the .qsf file.


Table LookupOperation Sequenceas described in the Address Lookup onpage 34 or based

on your pinassignment setting

in the .qsf file.

RO

[7:0] Reserved 8'hD0 RW 8'hE8 RO

Table 9. Address Register for Pin Input Delay Feature



[31] Reserved 1'h0 RW N/A RO




RW N/A RO


3'h3 RW N/A RO

[23:21] Reserved 3'h0 RW N/A RO




page 34.

RW N/A RO

[12:9] Reserved 4'hC RW N/A RO

continued...






[8:7] Select DQ pin sets toaccess.

• 2'h1: DQ 0 toDQ 5

• 2'h2: DQ 6 toDQ11

RW N/A RO

[6:4] Select the specific DQ pinto access.

• 3'h0: DQ 0 andDQ 6




• 3'h4: DQ 4 andDQ 10

• 3'h5: DQ 5 andDQ 11

RW N/A RO


Table 10. Address Register for Strobe Input Delay Feature







RW N/A RO


3'h3 RW N/A RO





page 34.

RW N/A RO

[12:0] Reserved 13'h18E0 RW N/A RO

Table 11. Address Register for Strobe Enable Phase Feature



[31] Reserved 1'h0 RW 1'h0 RO






RO

continued...







3'h3 RW 3'h3 RO





page 34.



page 34.

RO

[12:0] Reserved 13'h18F0 RW 13'h1998 RO

Table 12. Address Register for Strobe Enable Delay Feature









RO


3'h3 RW 3'h3 RO





page 34.



page 34.

RO

[12:0] Reserved 13'h1808 RW 13'h19A8 RO

Table 13. Address Register for Read Valid Delay Feature









RO


3'h3 RW 3'h3 RO

continued...










page 34.



page 34.

RO

[12:0] Reserved 13'h180C RW 13'h19A4 RO

PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for ParallelInterfaces Intel Cyclone 10 GX IP Cores Address Registers


Table 14. Address Register for Pin Output Delay Feature


Value Access Type Value Access Type







RO


3'h4 RW 3'h4 RO

[20:13] Specify the lane address ofan interface. This value isdepending on the resourcefitting process duringcompilation.

You can query this inthe Parameter TableLookup Operation

Sequence asdescribed in the

Address Lookup onpage 34.

RW You can query this inthe Parameter TableLookup Operation



RO

[12:8] Specify the address for thephysical location of a pinwithin a lane.



Address Lookup onpage 34 or based onyour pin assignmentsetting in the .qsf

file.




file.

RO












RW N/A RO


3'h4 RW N/A RO





RW N/A RO



• 2'h1: DQ 0 to DQ5

• 2'h2: DQ 6 toDQ11

RW N/A RO

[6:4] Select the specific DQ pin toaccess.





• 3'h4: DQ 4 andDQ 10

• 3'h5: DQ 5 andDQ 11

RW N/A RO









RW N/A RO


3'h4 RW N/A RO



Sequence as

RW N/A RO

continued...






described in the Address Lookup on

page 34.

[12:0] Reserved 13'18E0 RW N/A RO










RO


3'h4 RW 3'h3 RO








RO

[12:0] Reserved 13h'18F0 RW 13'h1998 RO










RO


3'h4 RW 3'h4 RO








RO












RW Dependingon the

InterfaceID

parameter inthe

ParameterEditor.

RO

[23:21] Specify the Avalon controllercalibration bus base address.

3'h4 RW 3'h4 RO





RW You canquery this in

theParameter

Table LookupOperation

Sequence asdescribed inthe AddressLookup onpage 34.

RO


PHY Lite for Parallel Interfaces Intel Cyclone 10 FPGA IP Core Address Registers











RO


3'h4 RW 3'h4 RO








RO






RO

continued...







file.


file.









RW N/A RO


3'h4 RW N/A RO





RW N/A RO



• 2'h1: DQ 0 to DQ5

• 2'h2: DQ 6 toDQ11

RW N/A RO






• 3'h4: DQ 4 andDQ 10

• 3'h5: DQ 5 andDQ 11

RW N/A RO












RW N/A RO


3'h4 RW N/A RO





RW N/A RO

[12:0] Reserved 13'18E0 RW N/A RO










RO


3'h4 RW 3'h3 RO








RO

[12:0] Reserved 13h'18F0 RW 13'h1998 RO










RO

continued...







3'h4 RW 3'h4 RO








RO









RW Dependingon the

InterfaceID

parameter inthe

ParameterEditor.

RO

[23:21] Specify the Avalon controllercalibration bus base address.

3'h4 RW 3'h4 RO





RW You canquery this in

theParameter

Table LookupOperation

Sequence asdescribed inthe AddressLookup onpage 34.

RO





[31] Reserved 1'b0 RW 1'b0 RO






RO


3'h3 RW 3'h3 RO

continued...














RO





file.




file.

RO






[30:27] Specify the PHY Lite forParallel Interfaces IP core

interface ID.



RW N/A RO

[26:24] Specify the Avaloncontroller calibration bus

base address.

3'h3 RW N/A RO


[20:13] Specify the lane address ofan interface. This value isdepending on the resource

fitting process duringcompilation.




RW N/A RO



• 2'h1: DQ 0 to DQ5

• 2'h2: DQ 6 toDQ11

RW N/A RO





RW N/A RO

continued...







• 3'h4: DQ 4 andDQ 10

• 3'h5: DQ 5 andDQ 11







interface ID.



RW N/A RO


base address.

3'h3 RW N/A RO







RW N/A RO

[12:0] Reserved 13'hCE0 RW N/A RO










RO


3'h3 RW 3'h3 RO









RO

continued...






[12:9] Reserved 4'hC RW 13'h1998 RO


• 2'h1: DQ 0 to DQ5

• 2'h2: DQ 6 toDQ11

RW

[6:0] Reserved 7'h70 RW






interface ID.





RO


base address.

3'h3 RW 3'h3 RO










RO







interface ID.





RO


base address.

3'h3 RW 3'h3 RO










RO





Control Registers Description

When you generate a read operation to the control registers addresses, the Avaloninterface returns a set of values from the control registers. The following tables showthe definition of the bits for each control register.

Table 32. Control Register Description

Feature Bit Description

Pin Output Delay [31:13] Reserved (2)

[12:0] Phase valueStrobe minimum setting: Refer to Table 36 on page40Strobe maximum setting: Refer to Table 36 on page40Incremental Delay: 1/128th VCO clock periodThe CSR value for DQS is set through the OutputStrobe Phase parameter during IP coreinstantiation.For Intel Arria 10 and Intel Cyclone 10 GX devices,this value is for DQS output strobe. For Intel Stratix10 devices, this value is for both DQ and DQS outputstrobe.Note: The pin output delay switches from the CSR

register value to the Avalon register valueafter the first Avalon write. It is only reset tothe CSR register value on a reset of theinterface.

Pin Input Delay [31:13] Reserved (2)

[12] Enable bit to select access to Avalon register or CSRregister.0 = Delay value is 0. CSR register is not available forthis feature.1 = Select delay value from Avalon register

[11:9] Reserved (2)

[8:0] Delay valueMinimum Setting: 0Maximum Setting: 511 VCO clock periodsIncremental Delay: 1/256th VCO clock period

Strobe Input Delay [31:13] Reserved (2)

[12] Enable bit to select access to Avalon register or CSRregister.0 = Delay value is 0. CSR register is not available forthis feature.1 = Select delay value from Avalon registerModifying these values must be done on all lanes in agroup.

[11:10] Reserved(2)

[9:0] Delay valueMinimum Setting: 0Maximum Setting: 1023 VCO clock periods

continued...

(2) Reserved bit ranges must be zero




Feature Bit Description

Incremental Delay: 1/256th VCO clock periodModifying these values must be done on all lanes in agroup.

Strobe Enable Phase [31:16] Reserved (2)

[15] Enable bit to select access to Avalon register or CSRregister.0 = Select delay value from CSR register. The CSRvalue is set through the Capture Strobe PhaseShift parameter during IP core instantiation.1 = Select delay value from Avalon registerModifying these values must be done on all lanes in agroup.

[14:13] Reserved(2)

[12:0] Bit [12:0]: Phase valueMinimum Setting: Refer to Table 36 on page 40Maximum Setting: Refer to Table 36 on page 40Incremental Delay: 1/128th VCO clock periodModifying these values must be done on all lanes in agroup.

Strobe Enable Delay [31:16] Reserved(2)

[15] Enable bit to select access to Avalon register or CSRregister.0 = Select delay value from CSR register1 = Select delay value from Avalon registerModifying these values must be done on all lanes in agroup.

[14:6] Reserved(2)

[5:0] Delay valueMinimum Setting: 0 external clock cyclesMaximum Setting: 63 external memory clock cyclesIncremental Delay: 1 external memory clock cycleModifying these values must be done on all lanes in agroup.

Read Valid Delay [31:16] Reserved(2)

[15] Enable bit to select access to Avalon register or CSRregister.0 = Select delay value from CSR register1 = Select delay value from Avalon registerModifying these values must be done on all lanes in agroup.

[14:7] Reserved

[6:0] Delay valueMinimum Setting: 0 external clock cyclesMaximum Setting: 127 external memory clock cyclesIncremental Delay: 1 external memory clock cycleModifying these values must be done on all lanes in agroup.

Internal VREF Code [31:6] Reserved

Bit [5:0]: VREF CodeRefer to Table 49 on page 58




Important: For more information about performing various clocking and delay calculations,depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.

Address Lookup

If you do not set the pin locations in the .qsf file, the lane addresses and pinplacement to an interface changes every time you compile your design in IntelQuartus Prime software. However, the PHY Lite for Parallel Interfaces IP core is alwaysgenerated as if the IP core is the only IP core in a column, with lane addressesstarting from 0. You need to determine the lane and pin addresses in order todynamically reconfigure the calibration settings in the IP core.

Figure 14. Lane and Pin Placement Dependent AddressesThis figure shows two examples of a placed group with two lanes, 16 data pins and a differential strobe.

Lane Address 0

Lane Address 1

PHY Lite for Parallel Interfaces Intel FPGA IP

strobe_iostrobe_io_ndata_io[0]data_io[1]data_io[2]data_io[3]data_io[4]data_io[5]data_io[6]data_io[7]data_io[8]data_io[9]

data_io[10]data_io[11]data_io[12]data_io[13]data_io[14]data_io[15]

Example 1

Lane Address 8

Lane Address 9


strobe_iostrobe_io_n

data_io[0]

data_io[1]

data_io[2]

data_io[3]

data_io[4]

data_io[5]

data_io[6]

data_io[7]

data_io[8]

data_io[9]

data_io[10]data_io[11]

data_io[12]

data_io[13]data_io[14]

data_io[15]

Example 2

To provide a unified way to look up reconfigurable feature addresses for a specificinterface both before and after placement, the address information is stored inmemory in the I/O column. This memory is addressable over the same Avalon-MM busused for feature reconfiguration.

You can cache lookups 1 to 4 (8-bytes of information) to have pin and lanetranslations in one look-up.

Table 33. Memory Lookup ComponentsThis table lists the two main components of the memory lookup.

Component Description

Global parameter table Stores pointers to the individual interface parameter tables. The global parameter tablelists all interfaces in the column (both the External Memory Interfaces and PHY Lite forParallel Interfaces IP cores).

Set of individual interfaceparameter tables

Contain interface specific information. This is where pin-level and lane-level address look-ups are performed.




http://www.altera.com/literature/ug/PHYLite_delay_calculations.xlsx

Figure 15. Memory Overview in Intel Stratix 10 Devices

Group 0 Pin 1 Group 0 Pin 0

num_lanes[1:0],num_pins[5:0]

Needed for pin address lookups

Needed for simplifying strobe feature logic address lookups

One per Interface

num_lanes[1:0] starts counting at 0. For example, 0 = 1 lane, 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes

Lane address table information: Group X Lane Y = lane_addr[7:0]

Pin address table information: Group X Pin Y = lane_addr[7:0],0xF,pin[3:0] for data and lane_addr[7:0],0xE,pin[3:0] for strobe

B

C

D

D

C

B

Number of Groups

Number of Groups

1’b0,id[3:0],27’h5000000 + pt_ptr1’b0,id[3:0],27’h5000000 + pt_ptr 28’d4

Parameter Table (PHY Lite Specific) 1’b0,id[3:0],27’h5000000 + pt_ptr +

18’h0,group_offset[5:2],2’b00 + lane_ptr[15:0],pin_ptr[15:0]

1’b0,id[3:0],27’h5000000 + lane_ptr + lane_num

Lane Address Table (PHY Lite Specific)

Group 0 Lane 0

1’b0,id[3:0],27’h5000000 + pin_ptr + 17’h0,pin_num[5:0],1’b0

Pin Address Table(PHY Lite Specific)

32-bits (4 Byte Addresses)

1’b0,id[3:0],27’h5000000

Global Parameter Table(One per column, same as EMIF)

1’b0,id[3:0],27’h5000000 + 28’h24 4’b1000,id[3:0], pt_ptr[23:0]

PT_VER[15:0],IP_VER[15:0]Number of Groups

4'h8,id[3:0],8'h00,interface_table_ptr[15:0]A

The MSB of the interface pointer entry in the global parameter table is 1 for PHY Lite interfaces.

A

1

2

3

4

5

6

Address Offset

1’b0,id[3:0],27’h5000000 + pt_ptr 28’d8

21’d0,num_grps,2’b00 + 28h’C

group_offset = grp_num -1

lane_offset[31:16],pin_offset[15:0]

Below are the steps to determine the lane and pin addresses from the lookup tables(the sequence corresponds to the sequence in Memory Overview in Intel Stratix 10Devices):

Table 34. Parameter Table Lookup Operation SequenceThe base address for PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP core is 27'h5000000.

Legend in Memory

Overview inIntel Stratix 10

Devices

Description

1 Search for Interface Parameter Table in Global Parameter Table (cache once per interface)• 1'b0,id3:0],27'h5000000 + 28'h24 to 1'b0,id3:0],27'h5000000 + 28'h3C

• 1 to 11 look-ups

2 Retrieve number of groups in the interface (cache once per interface)• 1'b0,id[3:0],27'h5000000 + 12'h0,pt_ptr[15:0] + 28'h4

• You can skip this sequence if the number of groups is saved in the core during compilation (forexample, hard coded in RTL logic)

3 Retrieve group information (cache once per group)• 1'b0,id[3:0],27'h5000000 + 12'h0,pt_ptr[15:0] + 28'h8 + grp_num

• Not always necessary

4 Retrieve Lane/Pin Address Offsets for group (cache once per group)• 1'b0,id[3:0],27'h5000000 + 12'h0,pt_ptr[15:0]

+ 18'h0,group_offset[5:2],2'b00 + 21'd0, grp_num, 2'b00 + 28'hC

5 Perform lane/pin address translation (cache once per pin)

continued...




Legend in Memory

Overview inIntel Stratix 10

Devices

Description

• 1'b0,id[3:0],27'h5000000 + 12'h000,lane_ptr[15:0] + lane_num

• 1'b0,id[3:0],27'h5000000 + 12'h000,pin_ptr[15:0] + 17'h0,pin_num[5:0],1'b0

6 Read/Write Avalon Calibration Bus• 1'b0,id[3:0],27'h5000000 + read_from_step_4 + intra_lane_addr

Figure 16. Memory Overview in Intel Arria 10 and Intel Cyclone 10 GX Devices

Group 0 Pin 1 Group 0 Pin 0

num_lanes[1:0],num_pins[5:0]

Needed for pin address lookups

Needed for simplifying strobe feature logic address lookups

One per Interface

num_lanes[1:0] starts counting at 0. For example, 0 = 1 lane, 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes

Lane address table information: Group X Lane Y = lane_addr[7:0]

Pin address table information: Group X Pin Y = lane_addr[7:0],0xF,pin[3:0] for data and lane_addr[7:0],0xE,pin[3:0] for strobe

B

C

D

D

C

B

Number of Groups

Number of Groups

id[3:0],24’h00E000 + pt_ptr

id[3:0],24’h00E000 + pt_ptr 28’d4

Parameter Table (PHY Lite Specific)

id[3:0],24’h00E000 + pt_ptr +22’d0,num_grps[7:2],2’b00 + 28 d8

lane_ptr[15:0],pin_ptr[15:0]

id[3:0],24’h00E000 + lane_ptr

Lane Address Table (PHY Lite Specific)

Group 0 Lane 0

id[3:0],24’h00E000 + pin_ptr

Pin Address Table(PHY Lite Specific)

32-bits (4 Byte Addresses)

id[3:0],24’h00E000

Global Parameter Table(One per column, same as EMIF)

id[3:0],24'00E018 4’b1000,id[3:0], pt_ptr[23:0]

PT_VER[15:0],IP_VER[15:0]Number of Groups

4'h8,id[3:0],8'h00,interface_table_ptr[15:0]A

The MSB of the interface pointer entry in the global parameter table is 1 for PHY Lite interfaces.

A

1

2

3

4

5

6

Below are the steps to determine the lane and pin addresses from the lookup tables(the sequence corresponds to the sequence in Figure 16 on page 36):

Table 35. Parameter Table Lookup Operation SequenceThe base address for PHY Lite for Parallel Interfaces Intel Arria 10 and PHY Lite for Parallel Interfaces IntelCyclone 10 GX FPGA IP cores are 24'h00E000.

Legend in Figure16 on page 36

Description

1 Search for Interface Parameter Table in Global Parameter Table (cache once per interface)

continued...




Legend in Figure16 on page 36

Description

• id3:0],24'h00E000 + 28'h18 to id3:0],24'h00E0000 + 28'h2C

• 1 to 11 look-ups

2 Retrieve number of groups in the interface (cache once per interface)• id[3:0],24'h00E000 + 4'h0,pt_ptr[23:0] + 4'h4

• You can skip this sequence if the number of groups is saved in the core during compilation (forexample, hard coded in RTL logic)

3 Retrieve group information (cache once per group)• id[3:0],24'h00E000 + 4'h0,pt_ptr[23:0] + 24'h4 + grp_num

• Not always necessary

4 Retrieve Lane/Pin Address Offsets for group (cache once per group)• id[3:0],24'h00E000 + pt_ptr + 22'd0,num_grps[7:2],2'b00 + 28'd8

5 Perform lane/pin address translation (cache once per pin)• id[3:0],24'h00E000 + 12'h000,lane_ptr[15:0] + lane_num

• id[3:0],24'h00E000 + 12'h000,pin_ptr[15:0] + 17'h0,pin_num[5:0], 1'b0

6 Read/Write Avalon Calibration Bus• id[3:0],24'h800000 + read_from_step_4 + intra_lane_addr

Strobes

The first pins listed in the pin address lookup table are the strobes. They are alsoidentified by bits[7:4] = 0xE. For separate strobes, the input strobe pin placementalways take precedence. For differential and complementary strobes, the positive pinis the lower index.

Note: You can modify the output phase of differential strobes by writing to either the positiveor negative pin. Only one write is necessary. This is also the case for output-onlycomplementary strobes.

Parameter Table Example

These figures show examples of designs containing two PHY Lite for Parallel InterfacesIP cores, each with one bidirectional group composed of 4 data bits and one strobe.Both interfaces are in the same I/O column and therefore their tables must bemerged.




Figure 17. Parameter Table Example for Intel Stratix 10 Devices

Figure 18. Parameter Table Example for Intel Arria 10 and Intel Cyclone 10 GX DevicesPHY Lite for Parallel Inter faces IP core 0 PHY Lite for Parallel Inter faces IP core 1Addr Data

Merged Column Parameter TableAddr Data Addr Data

00000001 00000001 0000000100000001 00000001 0000000100000001 00000001 0000000100000008 00000008 000000080003D090 0003D090 0003D090 00000064 00000064 0000008480000044 81000044 8100004400000000 00000000 8000006400000000 00000000 0000000000000000 8100005C 8000005C00000000 00000000 8100007C00000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000013800 00013800 0001380000000001 00000001 00000001

E04C 00000005

E000E004E008E00CE010E014E018E01CE020E024E028E02CE030E034E038E03CE040E044E048

00000005 00000005E050 00540058 00540058 00540058E054 00000000 00000000 00000039E058 00F100E0 00F100E0 39F339E4E05C 00F300F2

00000400800C01001401801C02002402802C03003403803C04004404804C050054058

00F300F2 39F739FBE060 000000F4

05C060 000000F4 000039FA

000138000000000100000005007400780000003A3AF13AE43AFA3AF900003AF8

00000400800C01001401801C02002402802C03003403803C04004404804C05005405805C06006406806C07007407807C080

Pin pointer

1 group with 5 pins and 1 lane in the interface

Lane pointer

Interface pointer

strobe_io = lane 0x00,pin 0data_io = lane 0x00, pin 1data_io = lane 0x00, pin 2data_io = lane 0x00, pin 3data_io = lane 0x00, pin 4

Number of groupGroup 0 – 5 pins, 1 lane

PHY Lite for Parallel

PHY Lite


for Parallel Interfaces IP core 1


Interfaces IP core 0

strobe_io = lane 0x3A, pin 4data_io = lane 0x3A, pin 1data_io = lane 0x3A, pin 9data_io = lane 0x3A, pin 10data_io = lane 0x3A, pin 8

Important: There is no guarantee of the ordering of the interface parameter tables in the mergedtable. You must perform a search to locate a specific interface parameter.

For more information about the contents of the parameter table, refer to Figure 16 onpage 36.

Calibration Guidelines

The PHY Lite for Parallel Interfaces IP core allows you to dynamically reconfigure thefeatures of the interface. However, performing calibration is an application specificprocess. This section provides some general guidelines for calibrating the Intel Stratix10, Intel Arria 10, and Intel Cyclone 10 GX I/O architecture.




Strobe Enable Windowing

The read pointer in the read FIFO buffer gets reset when reads are far apart (80 coreclock cycles). However, the data inside the FIFO is not cleared. Therefore, analternating pattern should be used to find the end to the strobe enable window toavoid reading stale data in the FIFO.

The strobe enable signal turns itself off on the last negative edge of the strobe.Therefore, while finding the enable window, use extra dummy pulses (either extendedstrobe or reads from memory without asserting the rdata_en signal) to clear thestrobe enable.




Output and Strobe Enable Minimum and Maximum Phase Settings

When dynamically reconfiguring the interpolator phase settings, the values must bekept within the ranges below to ensure proper operation of the circuitry.

Table 36. Output and Strobe Enable Minimum and Maximum Phase Settings for IntelStratix 10Intel Arria 10Intel Cyclone 10 GX Devices.

VCOMultiplication

FactorCore Rate Minimum Interpolator Phase Maximum Interpolator

Phase

Output Bidirectional Bidirectional withOCT Enabled

1 Full 0x080 0x100 0x100 0xA80

Half 0x080 0x100 0x100 0xBC0

Quarter 0x080 0x100 0x100 0xA00

2 Full 0x080 0x100 0x180 0x1400

Half 0x080 0x100 0x180 0x1400

Quarter 0x080 0x100 0x180 0x1400

4 Full 0x080 0x100 0x280 0x1FFF

Half 0x080 0x100 0x280 0x1FFF

Quarter 0x080 0x100 0x280 0x1FFF

8 Full 0x080 0x100 0x480 0x1FFF

Half 0x080 0x100 0x480 0x1FFF

Quarter 0x080 0x100 0x480 0x1FFF

For more information about performing various clocking and delay calculations,depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.




http://www.altera.com/literature/ug/PHYLite_delay_calculations.xlsx

Getting StartedYou can instantiate the PHY Lite for Parallel Interfaces IP core from IP Catalog in IntelQuartus Prime software. Intel provides an integrated parameter editor that allows youto customize this IP core to support a wide variety of applications.

This IP core is located in Libraries Basic Functions I/O of the IP catalog.

Related Information

• Introduction to Intel FPGA IP CoresProvides general information about all Intel FPGA IP cores, includingparameterizing, generating, upgrading, and simulating IP cores.

• Creating Version-Independent IP and Qsys Simulation ScriptsCreate simulation scripts that do not require manual updates for software or IPversion upgrades.

• Project Management Best PracticesGuidelines for efficient management and portability of your project and IP files.

Parameter Settings

Table 37. PHY Lite for Parallel Interfaces IP Core Parameter SettingsThis table lists the parameter settings for the PHY Lite for Parallel Interfaces IP core for Intel Stratix 10, IntelArria 10, and Intel Cyclone 10 GX devices.

GUI Name Values DefaultValues

Description

Parameter

Number of groups 1 to 18 1 Number of data and strobe groups in theinterface. The value is set to 1 by default.

General Tab- these parameters are set on a per interface basis

Clocks

Interface clock frequency 100 MHz - 1200MHz

533.0 MHz External memory clock frequency.Note: To achieve timing closure at 533 MHz

and above, use dynamic reconfigurationto calibrate the interface. Compile yourdesign with Intel Quartus Prime withaccurate board skew information for finaltiming analysis.

Use recommended PLLreference clock frequency

On, Off On If you want to calculate the PLL reference clockfrequency automatically for best performance,turn on this option.If you want to specify your own PLL referenceclock frequency, turn off this option.

continued...




https://www.altera.com/documentation/mwh1409960636914.html#mwh1409958250601

https://www.altera.com/documentation/mwh1409960636914.html#mwh1409958301774

https://www.altera.com/documentation/mwh1409960181641.html#esc1444754592005





Description

PLL reference clock frequency Dependent ondesired memoryclock frequency

133.25 MHz PLL reference clock frequency. You must feed aclock of this frequency to the PLL referenceclock input of the memory interface.Note: There is no minimum range, but the

maximum output frequency is 1600 MHz,limited by the clock network. Theminimum range for the ref_clk signalis 10 MHz but the maximum isdependent on the speed grade.

VCO clock frequency Calculatedinternally by PLL

1066.0 MHz The frequency of this clock is calculatedinternally by the PLL based on the interfaceclock and the core clock rate.

Clock rate of user logic Full, Half, Quarter Quarter Determines the clock frequency of user logic inrelation to the memory clock frequency. Forexample, if the memory clock sent from theFPGA to the memory device is toggling at 800MHz, a "Quarter rate" interface means that theuser logic in the FPGA runs at 200 MHz.

Specify additional outputclocks based on existing PLL

On, Off Off Exposes additional output clocks from theexisting PLL.

Output ClocksNote: These parameters are available only if the Specify additional output clocks based on existing PLL parameter

is turned on

Number of additional clocks 0 to 4 0 Specifies the number of additional clocks to beexposed.

outclk[4:0] (Reserved) — — PLL output clocks with the flag (Reserved) in theQSYS GUI are reserved for PHY Lite for ParallelInterfaces IP core internal functionality.

Desired Frequency — 133.25 MHz Specifies the output clock frequency of thecorresponding output clock port, outclk[], inMHz. The minimum and maximum valuesdepend on the device used. The PLL only readsthe numerals in the first six decimal places.

Actual Frequency — 133.25 MHz Allows you to select the actual output clockfrequency from a list of achievable frequencies.

Phase shift units ps or degrees ps Specifies the phase shift unit for thecorresponding output clock port, outclk[], inpicoseconds (ps) or degrees.

Phase shift — 469.0 ps Specifies the requested value for the phaseshift. The default value is 0 ps.

Actual phase shift — 469.0 ps Allows you to select the actual phase shift froma list of achievable phase shift values. Thedefault value is the closest achievable phaseshift to the desired phase shift.

Desired duty cycle 0.0–100.0 50.0 % Specifies the requested value for the duty cycle.

Actual duty cycle — 50.0 % Allows you to select the actual duty cycle from alist of achievable duty cycle values. The defaultvalue is the closest achievable duty cycle to thedesired duty cycle.

Dynamic Reconfigurationcontinued...

Getting Started




Description

Use dynamic reconfiguration On, Off Off Exposes an Avalon-MM interface, allowing youto control the configuration of the PHY Lite forParallel Interfaces IP core settings.

First PHYLite Instance in theAvalon Chain

On, Off On Select this parameter if this IP core instance isthe first instance in the Avalon chain, connectedto the master.This parameter is only available when you selectUse dynamic reconfiguration .Important: Do not select this parameter if

there is an External MemoryInterfaceIP core that connected toJTAG, available in the samecolumn.

Only available in PHY Lite for Parallel InterfacesIntel Stratix 10 FPGA IP core.

Interface ID — 0 The ID used to identify this interface in the I/Ocolumn over the Avalon-MM bus.

I/O Settings

I/O standard SSTL-12SSTL-125SSTL-135SSTL-15

SSTL-15 Class ISSTL-15 Class IISSTL-18 Class ISSTL-18 Class II1.2-V-HSTL Class

I1.2-V-HSTL Class

II1.5-V-HSTL Class

I1.5-V-HSTL Class

II1.8-V-HSTL Class

I1.8-V-HSTL Class

II1.2-V POD

1.2-V1.5-V1.8-VNone

SSTL-15 ClassI

Specifies the I/O standard of the interface'sstrobe and data pins written to the .qip file ofthe IP instance. When you choose None, theI/O standard is unspecified in the generated IP.

Group <x> - these parameters are set on a per group basis

Group <x> Parameter Settings

Copy parameters from anothergroup

On, Off Off Select this option when you want to copy theparameter settings from another group.Set Number of groups to more than 1 toenable this option.

Group 1 - 17 1 Choose the group index that you want as theparameter settings source. The changes madeto the source is updated automatically to all thetarget groups.

continued...

Getting Started




Description

You can only choose the group index which theparameter settings are not copied from anothergroup.Set Number of groups to more than 1 toenable this option.

Group <x> Pin SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Pin type Input, Output,Bidirectional

Bidirectional Direction of data pins. This value is set toBidirectional by default.

Pin width 1 to 48 9 Number of pins in this data/strobe group.A data width up to 48 is achievable if no strobeis used in the group. The number of strobes iscontrolled by the Use output strobe, Strobeconfiguration and Use separate capturestrobe parameters.

DDR/SDR DDR, SDR DDR Double/single data rate.

Group <x> Input Path SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Read latency 1 to 63 externalinterface clock

cycles

7 Expected read latency of the external device inmemory clock cycles.For example, a design with an external clockfrequency of 533 MHz in half-rate has a validread latency range of 5 to 63 external interfaceclock cycles.Refer to Table 38 on page 48 for minimumread latency settings based on FPGA core clockrate .

Swap capture strobe polarity On, Off Off Internally swap the negative and positivecapture strobe input pins. This feature is onlyavailable for complementary strobeconfigurations.

Capture strobe phase shift 0, 45, 90, 135,180

90 Internally phase shift the input strobe relative toinput data.

Group <x> Output Path SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Write latency 0 to 3 (maximumvalue is

dependent on therate)

0 Additional delay added to the output data inmemory clock cycles.Refer to Table 39 on page 48 for write latencysettings based on FPGA core clock rate.

Use output strobe On, Off On Use an output strobe.

Output strobe phase 0, 45, 90, 135,180

90 Phase shift of the output strobe relative to theoutput data.

Group <x> General Data SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Data configuration Single ended,Differential

(available only forIntel Arria 10 andIntel Cyclone 10

GX devices)

Single ended Selects the type of data. Single ended data typeuses one pin. Differential data type uses 2 pins.PHY Lite for Parallel Interfaces Intel Stratix 10FPGA IP core does not support differential datapins.Refer to I/O Standards on page 54 for a list ofsupported I/O standards.

continued...

Getting Started




Description

Group <x> General Strobe SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Strobe configuration Single ended,Differential,

Complementary

Single ended Select the type of strobe. A single ended strobeuses one pin, which reduces the maximumpossible number of data pins in the group to 47.Differential/complementary strobe types use 2pins, which reduces the maximum possiblenumber of data pins in the group to 46.Note: The differential strobe configuration uses

a differential input buffer, whichproduces a single clock for the captureDDIO and read FIFO. Thecomplementary strobe configurationuses two single-ended input buffers andclocks the data into the capture DDIOand read FIFO using both clocks (asrequired by protocols such as QDRII).The output path functionality is thesame.

Refer to I/O Standards on page 54 for a list ofsupported I/O standards.

Use separate strobes On, Off Off Separate the bidirectional strobe into input andoutput strobe pins. Use separate strobes is onlyavailable for a bidirectional data group with theoutput strobe enabled.

Group <x> OCT SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

OCT enable size 0 - 15 (IntelStratix 10devices)

0 - 4 (Intel Arria10 and Intel

Cyclone 10 GXdevices)

1 Specifies the delay between the OCT enablesignal assertion and the dqs_enable signalassertion. You must set a value that is largeenough to ensure that the OCT is turn on beforesampling input data.Note: For Intel Quartus Prime software version

prior to 17.0, refer to related informationfor known issue.

Expose termination ports On, Off Off Turn on to expose the series and paralleltermination ports to connect separate OCTblock.To enable this option, turn off Use Default OCTValues parameter and select a value for InputOCT Value or Output OCT Value parameters.

Use Default OCT Values — Use default OCT values based on the I/Ostandard parameter setting.

Input OCT Value No termination,<n> ohm with

calibration

Notermination

Specifies the group's data and strobe inputtermination values to be written to the .qip ofthe IP instance. The list of legal values isdependent on the I/O standard parametersetting. Refer to I/O Standards on page 54.This option is available when the Use DefaultOCT Values option is disabled.

Output OCT Value No termination,<n> ohm with

calibration, <n>with no

calibration

Notermination

Specifies the group's data and strobe inputtermination values to be written to the .qip ofthe IP instance. The list of legal values isdependent on the I/O standard parametersetting. Refer to I/O Standards on page 54supported termination values.

continued...

Getting Started




Description

This option is available when the Use DefaultOCT Values option is disabled.

Group <x> Timing SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Generate Input DelayConstraints for this group

On, Off On Instructs SDC to generate set_input_delayconstraints for this group.

Input Strobe Setup DelayConstraint

Constraint in ns 0.03 ns Specifies the group's input setup delayconstraint against the input strobe.

Input Strobe Hold DelayConstraint

Constraint in ns 0.03 ns Specifies the group's input hold delay constraintagainst the input strobe.

Inter Symbol Interference ofthe Read Channel

Constraint in ns 0.09 ns Specifies the Inter Symbol Interference valuefor DQS signal of read channel.Specify a positive value to decrease the setupand hold slack by half of the entered value.

Generate Output DelayConstraints for this group

On, Off On Instructs SDC to generate set_output_delayconstraints for this group.

Output Strobe Setup DelayConstraint

Constraint in ns 0.03 ns Specifies the group's output setup delayconstraint against the input strobe.

Output Strobe Hold DelayConstraint

Constraint in ns 0.03 ns Specifies the group's output hold delayconstraint against the input strobe.

Inter Symbol Interference ofthe Write Channel

Constraint in ns 0.09 ns Specifies the Inter Symbol Interference valuefor DQS signal of write channel.Specify a positive value to decrease the setupand hold slack by half of the entered value.

Group <x> Dynamic Reconfiguration Timing SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Dynamic Reconfiguration ReadDeskew Algorithm

DQ Per-BitDeskew, DQ

Group Deskew,Custom Dekew

DQ Per-BitDeskew

Specifies the Read Deskew algorithm for TimingAnalyzer to use when performing I/O timinganalysis:• DQ Per-Bit Deskew: Each DQ pin is adjusted

independently to minimize the skew withinthe DQ bits. DQS signal is adjusted to center-align to the de-skewed DQ bus. Each DQ bitmay have different delay chain settings.

• DQ Group Deskew: DQS signal is adjustedcenter-align to the DQ bus without de-skewing individual DQ bits. All DQ bits withinthe same group has same delay chainsettings.

• Custom Dekew: DQS is aligned based on therecoverable setup and hold slack youdefined.

You must select Use dynamic reconfigurationoption to enable this parameter.

Setup Slack Recoverable ofCustom Read Deskew

Algorithm

Constraint in ns 0.0 ns Specifies the amount of positive setup slackavailable based on your custom read deskewalgorithm.This parameter is available with the conditions:

continued...

Getting Started




Description

• Use dynamic reconfiguration is turn on• Pin type is set to Input or Bidirectional

and• Dynamic Reconfiguration Read Deskew

Algorithm is set to Custom Deskew

Hold Slack Recoverable ofCustom Read Deskew

Algorithm

Constraint in ns 0.0 ns Specifies the amount of positive hold slackavailable based on your custom read deskewalgorithm.This parameter is available with the conditions:• Use dynamic reconfiguration is turn on• Pin type is set to Input or Bidirectional

and• Dynamic Reconfiguration Read Deskew


Dynamic ReconfigurationWrite Deskew Algorithm

DQ Per-BitDeskew, DQ

Group Deskew,Custom Dekew

DQ Per-BitDeskew

Specifies the Write Deskew algorithm for TimingAnalyzer to use when performing I/O timinganalysis:• DQ Per-Bit Deskew: DQS signal is centered to

each individual DQ bits. Each DQ bit mayhave different delay chain settings.

• DQ Group Deskew: DQS signal is centered tothe DQ bus group. All DQ bits within thesame group has same delay chain settings.

• Custom Dekew: DQS is aligned based on therecoverable setup and hold slack youdefined.

You must select Use dynamic reconfigurationoption to enable this parameter.

Setup Slack Recoverable ofCustom Write Deskew

Algorithm

Constraint in ns 0.0 ns Specifies the amount of positive setup slackavailable based on your custom write deskewalgorithm.This parameter is available with the conditions:• Use dynamic reconfiguration is turn on• Pin type is set to Output or Bidirectional

and• Dynamic Reconfiguration Write Deskew


Hold Slack Recoverable ofCustom Write Deskew

Algorithm

Constraint in ns 0.0 ns Specifies the amount of positive hold slackavailable based on your custom write deskewalgorithm.This parameter is available with the conditions:• Use dynamic reconfiguration is turn on• Pin type is set to Output or Bidirectional

and• Dynamic Reconfiguration Write Deskew


Related Information

KDB link to Unsupported OCT enable size values for Arria 10 Altera PHYLite.Applicable to Quartus Prime software version prior to 17.0.

Getting Started



https://www.altera.com/support/support-resources/knowledge-base/solutions/rd08172016_561.html

Read Latency

Table 38. Minimum Read LatencyThis table is applicable to Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices.

Core Clock Rate VCO Multiplier Factor Read Latency (External Memory ClockCycle)

Full rate 1 4

2 4

4 3

8 3

Half rate 1 5

2 5

4 4

8 4

Quarter rate 1 7

2 7

4 7

8 7

Write Latency

Table 39. Maximum Write LatencyThis table is applicable to Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices.

Core Clock Rate VCO Multiplier Factor Write Latency (External Memory ClockCycle)

Full rate 1 0

2 0

4 0

8 0

Half rate 1 1

2 1

4 1

8 1

Quarter rate 1 3

2 3

4 3

8 2

Getting Started



Signals

Clock and Reset Interface Signals

Table 40. Clock and Reset Interface Signals

Signal Name Direction Width Description

ref_clk Input 1 Reference clock for the PLL. The reference clock must besynchronous with strobe_in to ensure the dqs_enable signalis in-sync with strobe_in.

reset_n Input 1 Resets the interface. This signal is asynchronous.

interface_locked Output 1 Interface locked signal from PHY Lite for Parallel Interfaces IPcore to Intel FPGA core. This signal indicates that the PLL and PHYcircuitry are locked.Data transfer should starts after the assertion of this signal.

core_clk_out Output 1 Use this core clock in the core-to-periphery transfer of soft logicdata and control signals.The core_clk_out frequency depends on the interfacefrequency and clock rate of user logic parameter.

Output Path Signals

Table 41. Output Path SignalsOutput path signals are signals that are available when you set the Pin Type parameter to either Output orBidirectional.


oe_from_core Input Quarter-rate: 4 x PIN_WIDTHHalf-rate: 2 x PIN_WIDTHFull-rate: 1 x PIN_WIDTH

Output enable signal from Intel FPGAcore. Synchronous to the core_clkoutput from the IP core.

data_from_core Input

Quarter rate-DDR: 8 x PIN_WIDTHHalf-rate DDR: 4 x PIN_WIDTHFull-rate DDR: 2 x PIN_WIDTHQuarter-rate SDR: 4 x PIN_WIDTHHalf-rate SDR: 2 x PIN_WIDTHFull-rate SDR: 1 x PIN_WIDTH

Data signal from Intel FPGA core.Synchronous to the core_clkoutput from the IP core.

strobe_out_in Input Quarter-rate: 8Half-rate: 4Full-rate: 2

Strobe signal from Intel FPGA core.Synchronous to the core_clkoutput from the IP core.Note: This path is always DDR.

strobe_out_en Input Quarter-rate: 4Half-rate: 2Full-rate: 1

Strobe output enable from Intel FPGAcore. Synchronous to the core_clkoutput from the IP core.

data_out/data_io Output/Bidirectional

• 1 to 48 if data configuration isSingle Ended

• 1 to 24 if data configuration isDifferential (Intel Arria 10 and Intel

Cyclone 10 GX devices)

Data output from PHY Lite for ParallelInterfaces IP core. Synchronous tothe strobe_out or strobe_iooutput from the IP core.If the Pin Type parameter is set toOutput, the data_out signals areused. If the Pin Type parameter isset to Bidirectional, the data_iosignals are used.

continued...

Getting Started




Note: PHY Lite for Parallel InterfacesIntel Stratix 10 FPGA IP coredoes not support differentialdata pins.

data_out_n/data_io_n

Output/Bidirectional

1 to 24 Negative data output from PHY Litefor Parallel Interfaces IP core isenabled when data configuration isset to Differential. Data issynchronous to the strobe_out orstrobe_io output from the IP core.If the Pin Type is set to Output, thedata_out_n ports are used. If thepin type is set to Bidirectional, thedata_io_n ports are used.Note: PHY Lite for Parallel Interfaces

Intel Stratix 10 FPGA IP coredoes not support differentialdata pins.

strobe_out/strobe_io


1 Positive output strobe fromPHY Litefor Parallel Interfaces IP core. If thePin Type is set to Output, thestrobe_out signal is used. If thePin Type is set to Bidirectional thestrobe_io signal is used. The UseSeparate Strobes parameter forcesthe use of the strobe_out signalwith a Bidirectional Pin Type.

strobe_out_n/strobe_io_n


1 Negative output strobe fromPHY Litefor Parallel Interfaces IP core.This is used if the StrobeConfiguration is set to Differentialor Complementary.If the Pin Type is set to Output, thestrobe_out_n signal is used. If thePin Type is set to Bidirectional, thestrobe_io_n signal is used. TheUse Separate Strobes parameterforces the use of the strobe_out_nsignal with a Bidirectional PinType.

Input Path Signals

Table 42. Input Path SignalsInput path signals are signals that are available when you set the Pin Type parameter to Input orBidirectional.


data_to_core Output Quarter-rate DDR: 8 x PIN_WIDTHHalf-rate DDR: 4 x PIN_WIDTHFull-rate DDR: 2 x PIN_WIDTH

Quarter-rate SDR: 4 x PIN_WIDTHHalf-rate SDR: 2 x PIN_WIDTHFull-rate SDR: 1 x PIN_WIDTH

Valid on rdata_valid. Synchronousto the core_clk output from thePHY Lite for Parallel Interfaces IP

core.

rdata_en Input Quarter-rate: 4Half-rate: 2Full-rate: 1

This signal is set to high for thenumber of expected read words after

a read command is issued.

continued...

Getting Started




Synchronous to the core_clkoutput from thePHY Lite for Parallel

Interfaces IP core.

rdata_valid Output Quarter-rate: 4Half-rate: 2Full-rate: 1

Delayed by READ_LATENCY withmargin and aligned to the core clockrate. For example, in quarter-rate,the delay is a multiple of 4 external

clock cycles.Synchronous to the core_clk

output from the PHY Lite for ParallelInterfaces IP core.

data_in/

data_io

Input/Bidirectional

1 to 48 if data configuration is SingleEnded

1 to 24 if data configuration is Differential(Intel Arria 10 and Intel Cyclone 10 GX

devices)

Data input from pin. Synchronous tothe strobe_in or strobe_io input.The first data_in must be associatedwith positive edge of strobe_in/

strobe_io.If the pin type is set to Input, thedata_in ports are used. If the pintype is set to bidirectional, the

data_io ports are used.Note: PHY Lite for Parallel Interfaces

Intel Stratix 10 FPGA IP coredoes not support differential

data pins.

data_in_n/

data_io_n

Input/Bidirectional

1 to 24 Negative data input from pin enabledwhen data configuration is set to

Differential. Data is synchronous tothe strobe_in or strobe_io input.

If the pin type is set to Input, thedata_in_n ports are used. If the pin

type is set to bidirectional, thedata_io_n ports are used.

Note: PHY Lite for Parallel InterfacesIntel Stratix 10 FPGA IP coredoes not support differential

data pins.

strobe_in/strobe_io

Input/Bidirectional

1 Positive strobe from pin. If the pintype is set to Input, the strobe_insignal is used. If the pin type is set toBidirectional, the strobe_io signal

is used.

strobe_in_n/strobe_io_n

Input/Bidirectional

1 Negative strobe from pin. This isused if the Strobe Configurationparameter is set to Differential orComplementary. If the pin type is

set to Input, the strobe_in_nsignal is used. If the pin type is set to

Bidirectional, the strobe_io_nsignal is used.

Getting Started



Avalon Configuration Bus Interface Signals

The PHY Lite for Parallel Interfaces IP core exposes the Avalon-MM slave and Avalon-MM master interfaces when you perform dynamic reconfiguration. Connect the Avalon-MM slave to either a master in the core or the master interface of either an PHY Litefor Parallel Interfaces IP core or the External Memory Interface IP core to be placed inthe same column. You can only connect the master interface to the slave interface of aPHY Lite for Parallel Interfaces IP core or External Memory Interface IP core to beplaced in the same column.

Table 43. Avalon-MM Master Interface Signals


avl_clk Input 1 Avalon interface clock.Maximum Avalon-MM interface clock for PHY Lite for Parallel

Interfaces Intel Stratix 10 FPGA IP core is 167 MHz.

avl_reset_n Input 1 Reset input synchronous to avl_clk.

avl_read Input 1 Read request from io_aux. This signal is synchronous to theavl_clk input.

avl_write Input 1 Write request from io_aux. This signal is synchronous to theavl_clk input.

avl_byteenable Input 4 Controls which bytes should be written on avl_writedata.

avl_writedata Input 32 Write data from io_aux. This signal is synchronous to theavl_clk input.

avl_address Input 31 (IntelStratix 10devices)

28 (Intel Arria10 and Intel


Address from io_aux. This signal is synchronous to theavl_clk input.

avl_readdata Output 32 Read data to io_aux. This signal is synchronous to theavl_clk input.

avl_writedata Input 32 Write data from io_aux. This signal is synchronous to theavl_clk input.

avl_readdata_valid Output 1 Indicates that read data has returned.

avl_waitrequest Output 1 Stalls upstream logic when it is asserted.

Table 44. Avalon-MM Slave Interface Signals


avl_out_clk Output 1 Connect this signal to the input Avalon interface of anotherPHY Lite for Parallel Interfaces IP core or the Arria 10 External

Memory Interfaces IP.

avl_out_reset_n Output 1 Connect this signal to the input Avalon interface of anotherPHY Lite for Parallel Interfacess IP core or the External

Memory Interfaces Intel Arria 10 FPGA IP.

avl_out_read Output 1 Indicates read transaction.

avl_out_write Output 1 Indicates write transaction.

continued...

Getting Started




avl_out_byteenable Output 4 Controls which bytes should be written onavl_out_writedata.

avl_out_writedata Output 32 The data packet associated with the write transaction.

avl_out_address Output 31 (IntelStratix 10devices)

28 (Intel Arria10 and Intel


Avalon address (in byte granularity). Value is identical toavl_address but with zeroes padded on the LSBs.

avl_out_readdata Input 32 The data packet associated withavl_out_readdata_valid.

avl_out_readdata_valid

Input 1 Indicates that read data has returned.

avl_out_waitrequest Input 1 Stalls upstream logic when it is asserted.

Related Information

Dynamic Reconfiguration on page 17For more information about connecting these signals

Getting Started



I/O StandardsThe PHY Lite for Parallel Interfaces IP core allows you to set I/O standards on the pinsassociated with the generated configuration. The I/O standard controls the availablestrobe configurations and OCT settings for all groups.

When you select an I/O standard in the I/O standard parameter, the referenceclock assigns the I/O standard as a single-ended input. For a differential referenceclock, override the single-ended Intel Quartus Prime IP File (.qip) setting in the .qsffile with the command below.

set_instance_assignment -name IO_STANDARDS LVDS -to ref_clk -entity topset_location_assignment <PIN_NUMBER> -to ref_clkset_location_assignment <PIN_NUMBER> -to "ref_clk(n)"

Differential reference clock only supports LVDS input buffer.

If you want to assign I/O standards manually at the system level (in the .qsf file),then set the I/O standard to none in the IP Parameter Editor, which do not output anyI/O standard related .qip assignments from the IP generation.

Table 45. I/O Standards and Termination Values for Intel Stratix 10 Devices

I/O Standard Valid InputTerminations (Ω)

Valid OutputTerminations

(Ω)

RZQ(Ω)

Differential/Complementary I/OSupport

Important: PHY Lite for Parallel Interfaces Intel

Stratix 10 FPGA IP core does notsupport differential data pins.

SSTL-12 60, 120 40, 60,240 240 Yes

SSTL-125 40, 60, 120 34, 40 240 Yes

SSTL-135 40, 60, 120 34, 40 240 Yes

SSTL-15 40, 60, 120 34, 40 240 Yes

SSTL-15 Class I 50 50 100 Yes

SSTL-15 Class II 50 25 100 Yes

SSTL-18 Class I 50 50 100 Yes

SSTL-18 Class II 50 25 100 Yes

1.2-V HSTL Class I 50 50 100 Yes

1.2-V HSTL Class II 50 25 100 Yes





continued...








Valid OutputTerminations

(Ω)

RZQ(Ω)


Important: PHY Lite for Parallel Interfaces Intel

Stratix 10 FPGA IP core does notsupport differential data pins.

1.2-V POD 34, 40, 48, 60, 80,120, 240

34, 40, 48,60

240 Yes

1.2-V — — — No

1.5-V — — — No

1.8-V — — — No

Table 46. I/O Standards and Termination Values for Intel Arria 10 Devices


(3)

Valid OutputCalibrated/

UncalibratedTerminations

(Ω)(3)

RZQ(Ω) (4)


SSTL-12 (5) 60, 120 40, 60 240 Yes

SSTL-125 (5) 60, 120 34, 40 240 Yes

SSTL-135 (5) 60, 120 34, 40 240 Yes

SSTL-15 (5) 60, 120 34, 40 240 Yes

SSTL-15 Class I (6) 0, 50 0, 50 100 Yes

SSTL-15 Class II(6) 0, 50 0, 25 100 Yes

SSTL-18 Class I(6) 0, 50 0, 50 100 Yes

SSTL-18 Class II(6) 0, 50 0, 25 100 Yes

1.2-V HSTL Class I(6) 0, 50 0, 50 100 Yes

1.2-V HSTL Class II(6) 0, 50 0, 25 100 Yes

1.5-V HSTL Class I(6) 0, 50 0, 50 100 Yes


1.8-V HSTL Class I(6) 0, 50 0, 50 100 Yes


1.2-V POD 34, 40, 48, 60, 80,120, 240

34, 40, 48,60

240 Yes

continued...

(3) 0 is equivalent to no termination.

(4) RZQ pin is not required for uncalibrated output terminations.

(5) Use this I/O standard if input termination is required with interface frequency more than 533MHz.

(6) Use this I/O standard if input termination is required with interface frequency equal or lessthan 533 MHz. For more information, refer to KDB found in the Related Links section: Theinterface frequency is too high for this I/O standard.

I/O Standards




(3)



(Ω)(3)

RZQ(Ω) (4)


1.2-V — — — No

1.5-V — — — No

1.8-V — — — No

Table 47. I/O Standards and Termination Values for Intel Cyclone 10 GX Devices

I/O Standard Valid InputTerminations

(Ω) (3)



(Ω)(3)

RZQ(Ω) (4)


SSTL-12 (7) 60, 120 40, 60 240 Yes

SSTL-125 (7) 60, 120 34, 40 240 Yes

SSTL-135 (7) 60, 120 34, 40 240 Yes

SSTL-15 (7) 60, 120 34, 40 240 Yes

SSTL-15 Class I (8) 0, 50 0, 50 100 Yes

SSTL-15 Class II(8) 0, 50 0, 25 100 Yes

SSTL-18 Class I(8) 0, 50 0, 50 100 Yes

SSTL-18 Class II(8) 0, 50 0, 25 100 Yes

1.2-V HSTL Class I(8) 0, 50 0, 50 100 Yes


1.5-V HSTL Class I(8) 0, 50 0, 50 100 Yes


1.8-V HSTL Class I(8) 0, 50 0, 50 100 Yes


1.2-V POD 34, 40, 48, 60, 80,120, 240

34, 40, 48,60

240 Yes

1.2-V — — — No

1.5-V — — — No

1.8-V — — — No

(3) 0 is equivalent to no termination.

(4) RZQ pin is not required for uncalibrated output terminations.

(7) Use this I/O standard if input termination is required with interface frequency more than 533MHz.

(8) Use this I/O standard if input termination is required with interface frequency equal or lessthan 533 MHz. For more information, refer to KDB link: The interface frequency is too high forthis I/O standard.

I/O Standards



Related Information

• On-Chip I/O Termination in Intel Arria 10 Devices

• On-Chip I/O Termination in Intel Cyclone 10 GX Devices

• On-Chip I/O Termination in Intel Stratix 10 Devices

• KDB link: Selected input mode termination value for data bus is not valid. Pleaseselect a value of 50 ohm or higher.

Input termination limitation for PHY Lite for Parallel Interfaces IP Core.

• KDB link: The interface frequency is too high for this I/O standardI/O standards limitation for PHY Lite for Parallel Interfaces IP core

Input Buffer Reference Voltage (VREF)

The POD I/O standard allows configurable VREF. By default, the externally providedVREF is used and using an internal VREF requires the following .qsf assignments:

set_instance_assignment -name VREF_MODE <mode> -to <pin_name>

Note: The VREF settings are at the lane level, so all pins using a lane must have the sameVREF settings (including GPIOs).

Table 48. VREF_MODE Description

VREF Mode Description

EXTERNAL Use the external VREF. This is the default.

CALIBRATED Use internal VREF generated using VREF codes from the Avalon-MM reconfiguration bus.

VCCIO_45 Use internal VREF generated using static VREF code. VREF is 45% of VCCIO






I/O Standards



https://www.altera.com/documentation/sam1403483633377.html#sam1403482130941

https://www.altera.com/documentation/vua1487061384661.html#sam1403482130941


https://www.altera.com/support/support-resources/knowledge-base/emif/2016/my-new-answer/why-do-i-see-_the-interface-frequency-is-too-high-for-this-i-o-s.html

Figure 19. VREF

Input Buffer

+

-Vref

R

R

VCCIO

Internal VREF

6 bits binary weighted resistors dividor

6 bits Static VREF Code

6 bits calibrated VREF code from Avalon-MM bus

VREF Calibration Block

+

-

VCCIO

Rt

External VREF

Resistor Ladder

Calibrated VREF Settings

Table 49. Calibrated VREF SettingsThis table lists the calibrated VREF settings that you can set over the Avalon-MM calibration bus. This table isapplicable to all Intel FPGA devices.

avl_writedata[5:0] % of VCCIO

000000 60.00%

000001 60.64%

000010 61.28%

000011 61.92%

000100 62.56%

000101 63.20%

000110 63.84%

000111 64.48%

001000 65.12%

001001 65.76%

001010 66.40%

continued...

I/O Standards




001011 67.04%

001100 67.68%

001101 68.32%

001110 68.96%

001111 69.60%

010000 70.24%

010001 70.88%

010010 71.52%

010011 72.16%

010100 72.80%

010101 73.44%

010110 74.08%

010111 74.72%

011000 75.36%

011001 76.00%

011010 76.64%

011011 77.28%

011100 77.92%

011101 78.56%

011110 79.20%

011111 79.84%

100000 80.48%

100001 81.12%

100010 81.76%

100011 82.40%

100100 83.04%

100101 83.68%

100110 84.32%

100111 84.96%

101000 85.60%

101001 86.24%

101010 86.88%

101011 87.52%

101100 88.16%

101101 88.80%

101110 89.44%

continued...

I/O Standards




101111 90.08%

110000 90.72%

110001 91.36%

110010 92.00%

110011 -> 111111 Reserved

Related Information

Dynamic Reconfiguration on page 17

On-Chip Termination (OCT)

PHY Lite for Parallel Interfaces IP core provides valid OCT settings for each group(refer to I/O Standards on page 54). These settings are written to the .qip of theinstance during generation. If you select an I/O standard that supports OCT in theGeneral tab, you can use the OCT blocks provided in the Intel Stratix 10, Intel Arria10, and Intel Cyclone 10 GX devices.

You can instantiate the OCT block in one of two ways:

• Using RZQ_GROUP assignment in the assignment editor, or

• Manual insertion of OCT block

RZQ_GROUP Assignment

The RZQ_GROUP assignment creates the OCT Intel FPGA IP core without modifying theRTL.

The Fitter searches for the rzq pin name in the netlist. If the pin does not exist, theFitter creates the pin name along with the OCT Intel FPGA IP core and itscorresponding connections. This allows you to create a group of pins to be calibratedby an existing or non-existing OCT and the Fitter ensures the legality of the design.You must associate the terminated pins of the PHY Lite for Parallel Interfaces IP coreinstance with an RZQ pin at the system level manually.

Example:

set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <altera_phylite_data_or_strobe_pin>

Note: Repeat for each data and strobe pin with calibrated termination.

If you know the location of the RZQ pin, then use the following .qsf assignments toset the RZQ pin to the desired location.

Example:

set_location_assignment <rzq_capable_pin_location> –to < rzq_pin_name>

Note: Repeat for each RZQ pin. The RZQ pin can be shared by groups in the same columnwith I/O standards that require the same RZQ value (refer to I/O Standards on page54).

I/O Standards



Manual Insertion of OCT Block

Alternately, you can expose the termination ports of PHY Lite for Parallel Interfaces IPcore instance by de-selecting the Use Default OCT Values under Group <x> OCTSettings, select the available OCT values for Input OCT Value and Output OCTValue, and select the Expose termination ports. For the input and output OCTvalues, refer to I/O Standards on page 54. You can then connect the termination portsto a OCT Intel FPGA IP core either in power-up or user mode.

Figure 20. RTL View of PHY Lite for Parallel Interfaces IP Interfacing with OCT IntelFPGA IP Core in User Mode

group_0_data_in[3:0]

cal_requestrefclk

rstnoctrzqin0

group_0_strobe_in

calibration_requestclockresetrzqin

oct_test_ip

group_0_data_in[3:0]group_0_parallelterminationcontrol[15:0]

4’h0group_0_rdata_en[3:0]group_0_seriesterminationcontrol[15:0]

phylite_test_ip

group_0_strobe_in32’h0group_1_data_from_core[31:0]

16’h0group_1_oe_from_core[15:0]group_1_parallelterminationcontrol[15:0]

group_1_seriesterminationcontrol[15:0]4’h0group_1_strobe_out_en[3:0]8’h0group_1_strobe_out_en[7:0]

ref_clkreset_n

group_1_data_out[3:0]group_1_strobe_outinterface_locked

oct_0_parallel_termination_control[15:0]

oct_0_series_termination_control[15:0]

u1

u0

Related Information

How can the PHY Lite IP RZQ pin location be assigned?

I/O Standards



https://www.altera.com/support/support-resources/knowledge-base/emif/2017/how-do-i-place-the-phylite-ip-rzq-pin-at-a-user-chosen-pin-locat.html

Design Guidelines

Guidelines: Group Pin Placement

Follow these guidelines to place the PHY Lite for Parallel Interfaces IP core group pins.

1. All groups in a PHY Lite for Parallel Interfaces IP core must be placed across acontiguous set of lanes. The number of lanes depends on the number of pins usedby the group.

2. Two groups, from either the same or different PHY Lite for Parallel Interfaces IPcore, cannot share an I/O lane.

3. For PHY Lite for Parallel Interfaces IP core instance that spans more than one I/Obank, all groups in the interface must be placed across a contiguous set of bankswithin an I/O column. The number of I/O banks required depends on the memoryinterface width.

4. Pins that are not used in an I/O bank are available as general purpose I/O (GPIO)pins.

5. To constrain groups from separate PHY Lite for Parallel Interfaces IP core instancesinto the same I/O bank, the instances must share the same reference clock andreset sources, the same external memory frequencies, and the same voltagesettings. The number of I/O banks must be at least as many as the number of PHYLite for Parallel Interfaces IP core interfaces.

6. A reference clock network can only span across maximum of 6 I/O banks.

7. You cannot share the OCT termination block across the I/O column. You canassociate the terminated pins of the PHY Lite for Parallel Interfaces IP coreinstance with an RZQ pin through RZQ_GROUP assignment.

Table 50. Group Pin PlacementPHY Lite for Parallel Interfaces IP core does not support DQS for X4.

Number of Pins in Group Valid DQS Group in a Bank Valid Index in a Bank

1-12 DQS for X8/X9 0-11/12-23/24-35/36-47

13-24 DQS for X16/X18 0-23/24-47

25-48 DQS for X32/X36 0-47

Related Information

Pin-Out Files for Intel FPGA DevicesFor specific DQS group numbers refer to the specific device pin-out file




https://www.altera.com/support/literature/lit-dp.html




Reference Clock

You are recommended to source the reference clock to the PHY Lite for ParallelInterfaces IP core from a dedicated clock pin. Use the clock pin in one of the I/Obanks used by the PHY Lite for Parallel Interfaces IP core. You must use contiguousI/O banks to implement multiple interfaces (consisting of a combination of ExternalMemory Interface and PHY Lite for Parallel Interfaces IP cores). If you use the samereference clock for these interfaces, place the reference clock in any of the contiguousI/O banks.

Important: In previous versions of the PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP core,the IOPLL output may experience additional jitter. The additional jitter occurs if yousource the reference clock from a cascaded PLL output, global clock, or core clock. Tocompensate for the jitter, the designs require additional constraints. This issue hasbeen fixed in Intel Quartus Prime version 17.1.

Related Information

• Guideline: I/O Standards Supported for I/O PLL Reference Clock Input Pin

• Clock Networks and PLLs in Intel Arria 10 Devices - PLL CascadingFor more information about PLL cascading in Intel Arria 10 devices.

• How do I compensate for the jitter of PLL cascading or non-dedicated clock pathfor Arria 10 PLL reference clock?

Reset

You can source the reset to the PHY Lite for Parallel Interfaces IP core from anexternal pin or from the core. If you source the reset from an external pin, you mustconfigure the I/O standard of the reset signal in the .qsf file with the followingcommand:

set_location_asignment <PIN_NUMBER> -to <signal_name>

Constraining Multiple PHY Lite for Parallel Interfaces Interfaces toOne I/O Bank

To constrain groups from separate PHY Lite for Parallel Interfaces IP core instancesinto the same I/O bank, the instances must share the same reference clock and resetsources, the same external memory frequencies and the same voltage settings.

Related Information

Functional Description on page 6

Dynamic Reconfiguration

If you are using the dynamic reconfiguration feature, all interfaces of the ExternalMemory Interfaces and PHY Lite for Parallel Interfaces IP cores in the same I/Ocolumn must share the reset signal. Multiple IP cores requiring Avalon core accessrequire daisy chain connectivity.

Design Guidelines




https://www.altera.com/documentation/sam1403483633377.html#mcn1414660625084

https://www.altera.com/support/support-resources/knowledge-base/tools/2017/fb470823.html

https://www.altera.com/support/support-resources/knowledge-base/tools/2017/fb470823.html

Related Information

Daisy Chain on page 17Describes the daisy chain connectivity

Timing

The Intel Quartus Prime software generates the required timing constraints to analyzethe timing of the PHY Lite for Parallel Interfaces IP core on the all Intel FPGA devices.

Timing Components

Table 51. Timing Components

Circuit Category Timing Paths Source Destination Description

Source synchronousand optionallycalibrated (9)

Read Path MemoryDevice

DQ CaptureRegister

Source synchronous timing paths—paths whereclock and data signals are passed from thetransmitting devices to the receiving devices.Optionally calibrated paths—paths with delayelements that are dynamically reconfigurable toachieve timing closure, especially at higherfrequency, and to maximize the timing margins.You can calibrate these paths by implementingan algorithm and turning on the optionaldynamic reconfiguration feature. An example ofthe calibrated path is the FPGA to memorydevice write path, in which you can dynamicallyreconfigure the delay elements to, for instance,compensate the skew due to process voltagetemperature variation.

Source synchronousand optionallycalibrated (9)

Write Path FPGADQ/DQS

MemoryDevice

Internal FPGA Core to PHYLite forParallel

Interfaces IPPath

CoreRegisters

Write FIFO The internal FPGA paths are paths in the FPGAfabric. The Timing Analyzer reports thecorresponding timing margins.

Internal FPGA PHY Lite forParallel

Interfaces IPto Core

Read FIFO Core Registers

Timing Constraints and Files

To successfully constrain the timing for PHY Lite for Parallel Interfaces IP core, the IPcore generates a set of timing files. You can locate these timing files in the<variation_name> directory:

• <variation_name> .sdc

• <variation_name> _ip_parameters.tcl

• <variation_name> _pin_map.tcl

• <variation_name>_parameters.tcl

• <variation_name>_report_timing.tcl

• <variation_name>_report_timing_core.tcl

(9) Can be optionally calibrated by using dynamic reconfiguration.

Design Guidelines



<variation_name>.sdc

You can find the location of the <variation_name>.sdc file in the .qip or .qsys,which is generated during the IP generation. The <variation_name> .sdc allows theFitter to optimize timing margins with timing driven compilation and allows the TimingAnalyzer to analyze the timing of your design.

The IP core uses <variation_name>.sdc for the following operations:

• Creating clocks on PLL inputs

• Creating generated clocks

• Calling derive_clock_uncertainty

• Creating set_output_delay and set_input_delay constraints to analyze thetiming of the read and write paths

<variation_name>_parameter.tcl

The <variation_name>_parameters.tcl file is a script that lists the following PHYLite for Parallel Interfaces IP core parameters used in the .sdc file and report timingscripts:

• Jitter

• Simultaneous switching noise

• Calibration uncertainties

<variation_name>_ip_parameters.tcl

The <variation_name>_ip_parameters.tcl file lists the PHY Lite for ParallelInterfaces IP core parameters and is read by the <variation_name>.sdc.

<variation_name>_pin_map.tcl

The <variation_name>_pin_map.tcl is a TCL library of functions and proceduresthat <variation_name>.sdc uses.

<variation_name>_report_timing.tcl

The <variation_name>_report_timing.tcl file is a script that contains timinganalysis flow and reports the timing slack for your variation. This script runsautomatically during calibration (during static timing analysis) by sourcing thefollowing files:

• <variation_name>_ip_parameters.tcl

• <variation_name>_parameters.tcl

• <variation_name>_pin_map.tcl

• <variation_name>_report_timing_core.tcl

You can also run <variation_name>_report_timing.tcl with the Report DDRfunction in the Timing Analyzer. This script runs for every instance of the samevariation.

Design Guidelines



Note: You can only use the Report DDR function if you enable the dynamic reconfigurationfeature.

<variation_name>_report_timing_core.tcl

The <variation_name>_report_timing_core.tcl file is a script that<variation_name>_report_timing.tcl uses to calculate the timing slack foryour variation. <variation_name>_report_timing_core.tcl runs automaticallyduring compilation.

Timing Analysis

Table 52. Timing AnalysisThis table lists the timing analysis performed in the I/O and FPGA for the PHY Lite for Parallel Interfaces IPcore.

Location Description

I/O The PHY Lite for Parallel Interfaces IP core generation creates the appropriate generated clock settings forthe read strobe on the read path and the write strobe of the write path, according to their strobe type(singled-ended, complementary, or differential) and their interface type (SDR or DDR) in the followingformat:• Clock name for read strobe—<pin_name>_IN.• Clock name for the write path—<pin_name> for positive strobe.• Clock name for the write path—<pin_name>_neg for negative strobe.The set_false_path, set_input_delay and set_output_delay constraints are also generated toensure proper timing analysis of the PHY Lite for Parallel Interfaces IP core.

FPGA The PHY Lite for Parallel Interfaces IP core generation creates the clock settings for the user core clockand the periphery clock in the following formats:• user core clock—<variation_name>_usr_clk

• periphery clock— <variation_name>_phy_clk*The user core clock is for user core logic and the periphery clock is the clock for the PHY Lite for ParallelInterfaces IP core periphery hardware. With these clock settings, the Timing Analyzer analyzes the timingof this IP core interface transfer and within core transfer correctly.

Timing Closure Guidelines

Timing Closure: Dynamic Reconfiguration

You can dynamically reconfigure the delay elements in the I/O to optimize process,voltage, temperature variations by implementing a calibration algorithm that modifiesthe input and output delays.

Related Information

Dynamic Reconfiguration on page 17

Timing Closure: Non Edge-Aligned Input Data

If the input data is not edge-aligned, use the following equation to calculate the newInput Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraintvalues:

New Input Strobe Setup Delay Constraint Value = Clock to data skew - InputStrobe Phase Shift (nanosecond)

Design Guidelines



New Input Strobe Hold Delay Constraint Value = Clock to data skew + InputStrobe Phase Shift (nanosecond)

For example, if the memory speed is 800 MHz and the clock to data skew value is 0.1with input data phase shift of 90°:

New Input Strobe Setup Delay Constraint value = 0.1-1.25*(90/360) =-0.2125ns.

New Input Strobe Hold Delay Constraint value = 0.1 + 1.25*(90/360) = 0.4125ns

Important: Ensure that you make the changes in the Input Strobe Setup Delay Constraint andInput Strobe Hold Delay Constraint parameters.

I/O Timing Violation

It can be difficult to achieve timing closure for I/O paths at high frequency. Use thedynamic reconfiguration feature to calibrate the I/O path.

Related Information

Dynamic Reconfiguration on page 17For more information about using the dynamic reconfiguration feature to calibratethe I/O path

Internal FPGA Path Timing Violation

If timing violations are reported at the internal FPGA paths (such as<instance_name>_usr_clk or <instance_name>_phy_clk_*), consider thefollowing guidelines:

If setup time violation is reported, lower the clock rate of the user logic from full-rateto half-rate, or from half-rate to quarter-rate. This reduces the frequency requirementof the IP core-to-core data transfer.

If hold time violation is observed, you may increase hold uncertainty value to equal orhigher than the violation amount in the .sdc file. This will provide a more stringentconstraint during design fitting. Following is an example to increase the holduncertainty.

If $::quartus(nameofexecutable) != “quartus_sta”

set_clock_uncertainty -from [<instance_name>_phy_clk_*] -to [<instance_name>_phy_clk_*] -hold 0.3 -add

set_clock_uncertainty -from [<instance_name>_usr_clk] -to [<instance_name>_usr_clk] -hold 0.3 -add

However, increasing the hold uncertainty value may cause setup timing violation atslow corner.

Design Guidelines



Design ExampleThe PHY Lite for Parallel Interfaces IP core is able to generate a design example thatmatches the same configuration chosen for the IP. The design example is a simpledesign that does not target any specific application; however you can use the designexample as a reference on how to instantiate the IP core and what behavior to expectin a simulation.

Note: The .qsys files are for internal use during design example generation only. You shouldnot edit the files.

Generate the Design Example

You can generate a design example by clicking Generating Example Design in theIP Parameter Editor.

The software generates a user defined directory in which the design example filesreside.

There are two variants of design example available for PHY Lite for Parallel InterfacesIP core:

• Variant without dynamic reconfiguration design example

• Variant with dynamic reconfiguration design example

Table 53. PHY Lite for Parallel Interfaces IP Core Design Example Variants

Design Example Variant Design Files Description

Dynamic Reconfiguration OFF ed_synth.qsys (synthesisonly)

Consists of configurablePHY Lite forParallel Interfaces IP core instance.

ed_sim.qsys (simulationonly)

Consists of sim_ctrl, agent, addr/cmdand PHY Lite for Parallel Interfaces IPcore instances.Perform read and write transactionverification.

ON ed_synth.qsys (synthesisonly)

Consists of IOAUX andPHY Lite forParallel Interfaces IP core instances.You need to instantiate NIOS andAVL_Controller manually or createuser logic to perform addresstranslation.

phylite_debug_kit.qsys(synthesis only)

Consists of NIOS, AVL_Controller, APIfunctions, IOAUX and PHY Lite forParallel Interfaces IP core instances.

continued...







Design Example Variant Design Files Description

A recommended example design toperform dynamic reconfiguration.This design example does notsupport simulation.

ed_sim.qsys (simulationonly)

Consists of sim_ctrl, agent, addr/cmd, cfg_ctrl, avl_ctrl and PHY Litefor Parallel Interfaces IP coreinstances.This design example demonstratesdynamic reconfiguration and usesFSM to perform calibration.

Design Example without Dynamic Reconfiguration

When the Enable dynamic reconfiguration option is not selected, Intel QuartusPrime software generates a design example of PHY Lite for Parallel Interfaces IP corewithout a dynamic reconfiguration module.

This design example consists of simulation and synthesis design files.

Generate the Hardware Design Example

The make_qii_design.tcl generates a synthesizable hardware design examplealong with a Quartus project, ready for compilation.

To generate synthesizable design example, run the following script at the end of IPgeneration:

quartus_sh -t make_qii_design.tcl

To specify an exact device to use, run the following script:

quartus_sh -t make_qii_design.tcl [device_name]

This script generates a qii directory containing a project called ed_synth.qpf. Youcan open and compile this project with the Intel Quartus Prime software.

Generate the Simulation Design Example

The make_sim_design.tcl generates a simulation design example along with tool-specific scripts to compile and elaborate the necessary files.

To generate the design example for a Verilog or a mixed-language simulator, run thefollowing script at the end of IP generation:

quartus_sh -t make_sim_design.tcl VERILOG

To generate the design example for a VHDL-only simulator, run the following script:

quartus_sh -t make_sim_design.tcl VHDL

This script generates a sim directory containing one subdirectory for each supportedsimulation tools. Each subdirectory contains the specific scripts to run simulation withthe corresponding tool.

Design Example



The simulation design example provides a generic example of the core and I/Oconnectivity for your IP configuration. Functionally, the simulation iterates over eachgroup in your configured IP and performs basic reads/writes to an associated agent(one per group) in the testbench. A simple one group PHY Lite for Parallel InterfacesIP core instantiation in the testbench is used for basic address and command outputsto the agent. A side bus between the sim_ctrl and the agents is used to check thatthe reads and writes are valid.

Figure 21. High-Level View of the Simulation Design Example with One GroupSide read/write command

Side read/write data

DRAM clockWrite commandRead commandAgent select

data

strobedata

sim_ctrl

DRAM clock

Latency Delays

DRAM clockCore clock

PHY Lite DUT

PHY Lite ADDR/CMD


Read/Write command

Core clockRead/Write

enable


Agent (one per group in DUT)

Dynamic Reconfiguration Design Examples

When you select the Use dynamic reconfiguration option and click on GenerateExample Design, Intel Quartus Prime software generates two design examples:

• Dynamic reconfiguration with debug kit design example.

• Dynamic reconfiguration with configuration control module.

Note: The dynamic reconfiguration design examples are not supported in Intel Stratix 10devices.

Dynamic Reconfiguration with Debug Kit

This design example provides you a synthesizable system capable to perform dynamiccalibration for PHY Lite for Parallel Interfaces IP core in Intel Arria 10 and Intel Cyclone10 GX devices.

The design example includes:

• A fully configurable PHY Lite for Parallel Interfaces IP core

• An Avalon controller to perform address translation

• A NIOS II processor to perform dynamic calibration for PHY Lite for ParallelInterfaces IP core

• A set of application program interface (API) to configure delay chains for PHY Litefor Parallel Interfaces Interface IP core

Design Example



Figure 22. Dynamic Reconfiguration with Debug Kit Design Example

Avalon Controller Bus

Avalon Controller Bus

PHY Lite for Parallel Interfaces DUTAVL_CTRLNIOS II


Table 54. Dynamic Reconfiguration with Debug Kit Design Example Generated FilesThe example design folders are named differently in Intel Arria 10 and Intel Cyclone 10 GX devices.

• For Intel Arria 10, the example design folder is named as phylite_0_example design.

• For Intel Cyclone 10 GX, the example design folder is named as phylite_c10gx_0_example_design.

Example Design Files Description

<example_design_folder>/readme.txt This file provide simple instructions to generate and use theexample design.

<example_design_folder>/hello_world.c This is the main test program.

<example_design_folder>/phylite_debug_kit.qsys

This is the system design file.

<example_design_folder>/phylite_dynamic_reconfigurations.c

This file contains the set of APIs use in the test program.

<example_design_folder>/phylite_dynamic_reconfiguration.h

This is the header file for the APIs.

<example_design_folder>/phylite_niosii_bridge.v<example_design_folder>/phylite_niosii_bridge_hw.tcl

This is an interconnect module between PHY Lite for ParallelInterfaces IP core and NIOS II processor.

<example_design_folder>/issp.tcl This is the In-System Source and Probes module. Use thisfile to reset the system and to probe the status of theinterface_locked signal and dynamic calibration donestatus from NIOS II processor.

Table 55. API Functions in Dynamic Reconfiguration Debug Kit Design Example

API Function Argument Return Value Description

hw_get_num_groups ID Integer Read fromAVL_CTRL_REG_NUM_GROUPS registerfor the specified ID.

hw_get_group_info ID, GROUP_NUM 16'h0000,num_lanes[7:0],num_pins[7:0]

Read from AVL_CTRL_REG_GROUP_INFO register for the specified ID andgroup number.The return values are the number oflanes and number of pins available forthe specified ID and group number.

hw_get_num_lanes ID, GROUP_NUM Integer Read from the AVL_CTRL_REG_GROUP_INFO register for the specified ID andgroup number.The return values are the number oflanes available for the specified ID andgroup number.

continued...

Design Example




hw_get_num_pins ID, GROUP_NUM Integer Read from the AVL_CTRL_REG_GROUP_INFO register for the specified ID andgroup number.The return values are the number ofpins available for the specified ID andgroup number.

hw_get_input_delay ID, GROUP_NUM,PIN_NUM, CSR

Integer Read from the AVL_CTRL_REG_IDELAYregister for the specified ID, groupnumber, and pin ID.Specified CSR to:• 0 to read from Avalon Controller

register• 1 to read from CSR register

hw_get_output_delay ID, GROUP_NUM,PIN_NUM, CSR

Integer Read from the AVL_CTRL_REG_ODELAYregister for the specified ID, groupnumber and pin number.Specified CSR to:• 0 to read from Avalon Controller


hw_get_strobe_input_delay ID, GROUP_NUM,PIN_NUM, CSR

Integer Read from theAVL_CTRL_REG_DQS_DELAY delayregister for the specified ID, groupnumber and pin number.Specified CSR to:• 0 to read from Avalon Controller


hw_get_strobe_enable_delay ID, GROUP_NUM,PIN_NUM, CSR

Integer Read from theAVL_CTRL_REG_DQS_EN_DELAYregister for the specified ID, groupnumber and pin number.Specified CSR to:• 0 to read from Avalon Controller


hw_get_strobe_enable_phase ID, GROUP_NUM,PIN_NUM, CSR

Integer Read from theAVL_CTRL_REG_DQS_EN_PHASE_SHIFTregister for the specified ID, groupnumber and pin number.Specified CSR to:• 0 to read from Avalon Controller


hw_get_read_valid_enable_delay

ID, GROUP_NUM,PIN_NUM, CSR

Integer Read from theAVL_CTRL_REG_RD_VALID_DELAYregister for the specified ID, groupnumber and pin number.Specified CSR to:• 0 to read from Avalon Controller


hw_set_input_delay ID, GROUP_NUM,PIN_NUM, inputdelay value (integer)

— Write to AVL_CTRL_REG_IDELAY registerfor the specified ID, group number andpin number.

continued...

Design Example




Refer to Table 32 on page 32 for validvalue range.

hw_set_output_delay ID, GROUP_NUM,PIN_NUM, outputdelay value (integer)

— Write to AVL_CTRL_REG_ODELAYregister for the specified ID, groupnumber and pin number.Refer to Table 32 on page 32 for validvalue range.

hw_set_strobe_input_delay ID, GROUP_NUM,PIN_NUM, strobeinput delay value(integer)

— Write to AVL_CTRL_REG_DQS_DELAYregister for the specified ID, groupnumber and pin number.Refer to Table 32 on page 32 for validvalue range.

hw_set_strobe_enable_delay ID, GROUP_NUM,PIN_NUM, strobeenable delay value(integer)

— Write toAVL_CTRL_REG_DQS_EN_DELAYregister for the specified ID, groupnumber and pin number.Refer to Table 32 on page 32 for validvalue range.

hw_set_strobe_enable_phase ID, GROUP_NUM,PIN_NUM, strobeenable phase value(integer)

— Write toAVL_CTRL_REG_DQS_EN_PHASE_SHIFTregister for the specified ID, groupnumber and pin number.Refer to Table 32 on page 32 for validvalue range.

hw_set_read_valid_enable_delay

ID, GROUP_NUM,PIN_NUM, read validenable delay value(integer)

— Write toAVL_CTRL_REG_RD_VALID_DELAYregister for the specified ID, groupnumber and pin number.Refer to Table 32 on page 32 for validvalue range.

Design Example



Avalon Controller

The example design provides an Avalon controller to simplify the access to thedynamic reconfiguration registers of an interface. The Avalon controller is useful whenthere are multiple groups or instantiation of the PHY Lite for Parallel Interfaces IPcore.

Figure 23. Avalon Controller

Avalon Controller

Avalon Interface Input(from user logic)

Avalon Interface Output(to PHY Lite instance daisy chain)

The input interface is as follows:

avl_in_address[31:0] =8'h00,interface_id[3:0],grp[4:0],pin[5:0],csr[0],register[7:0]

Note: There is no look-up stage here. The Avalon controller automatically looks up andcaches all the necessary data.

Note: A single controller can support multiple interfaces in an I/O column.

Table 56. Avalon Controller RegistersThis table lists the available registers in the Avalon controller. For more information, refer to Table 32 on page32.

Register[7:0] Pin[5:0]

Csr[0] RegisterAccessType

Data onavl_readd

ata /writedata

Description

AVL_CTRL_REG_NUM_GROUPS 0 0: Access toAvalon

register.

Avalonregister:

ROCSR

register:N/A

24'h000000,num_grps[7:0]

Number of groups withinan interface.

AVL_CTRL_REG_GROUP_INFO 0 0: Access toAvalon

register.

Avalonregister:

ROCSR

register:N/A

16'h0000,num_lanes[7:0],num_pins[7:

0]

Number of pins within agroup.

AVL_CTRL_REG_IDELAY 0-47 0: Access toAvalon

register.

Avalonregister:

RWCSR

register:N/A

23'h000000,dq_delay[8:0]

Pin input delay. Use thisregister to set pin PVT

compensated inputdelay.

continued...

Design Example



Register[7:0] Pin[5:0]

Csr[0] RegisterAccessType

Data onavl_readd

ata /writedata

Description

AVL_CTRL_REG_ODELAY 0-47 0: Access toAvalon

register.1: Access toCSR register.

Only readoperation is

allowed.

Avalonregister:

RWCSR

register:RO

19'h00000,output_delay[12:

0]

Pin output delay. Usethis register to read andset the pin output delay.

AVL_CTRL_REG_DQS_DELAY 0: DQSA

1: DQSB

(10)

0: Access toAvalon

register.

Avalonregister:

RWCSR

register:N/A

22'h000000,dqs_delay[9:0]

Strobe input delay of apin. Use this register to

set the strobe PVTcompensated input

delay.

AVL_CTRL_REG_DQS_EN_DELAY 0 0: Access toAvalon



allowed.

CSRregister:

N/ACSR

register:RO

26'h0000000,dqs_en_delay[5

:0]

Strobe enable inputdelay of a pin. Use this

register to set the strobeenable delay.

AVL_CTRL_REG_DQS_EN_PHASE_SHIFT 0: DQSA

1: DQSB

(10)

0: Access toAvalon



allowed.

CSRregister:

N/ACSR

register:RO

19'h00000,phase[1

2:0]

Strobe enable inputphase of aister to set the

strobe enable phase.

AVL_CTRL_REG_RD_VALID_DELAY 0 0: Access toAvalon



allowed.

CSRregister:

N/ACSR

register:RO

25'h0000000,rd_vld_delay[6:

0]

Read val to set the readvalid delay.

Note: The example Avalon controller does not currently support VREF reconfiguration.

Related Information

Functional Description on page 77

Generate the Dynamic Reconfiguration with Debug Kit Design Example

1. In Intel Quartus Prime, select File New Project Wizard to create a newproject directory and specify phylite_debug_kit as the project name.

2. Select device and instantiate PHY Lite for Parallel Interfaces IP core and turn onthe Use dynamic reconfiguration option.

3. Click Generate Example Design.

(10) Strobe logic B is only used by the negative pin of complementary strobes

Design Example



4. In your example design directory, open the phylite_debug_kit.qsys file andclick Generate HDL to generate the .qsys design example files.

5. In Intel Quartus Prime, right click on the design example project and selectSettings.

6. In Files tab, browse to the <generated design example folder/phylite_debug_kit> and add in phylite_debug_kit.qip file into yourproject.

7. Select Start Compilation to compile the design example project.

8. In Intel Quartus Prime, select Tools Nios II Software Build Tool for Eclipse.Create a new workspace when prompted.

9. In Nios II - Eclipse software, select File New Nios II Application and BSPfrom Template.

10. In the Nios II Application and BSP from Template window, selectphylite_debug_kit_sopcinfo file in SOPC Information File nameparameter to load the CPU settings.

11. Specify a project name in the Project name parameter.

12. Select Hello World for the Project Template.

13. Click Finish to generate the project.

14. Copy hello_world.c, phylite_dynamic_reconfiguration.c, andphylite_dynamic_reconfiguration.h files from the generated exampledesign folder into your Eclipse project folder. You can refresh the Nios II Eclipsewindow by pressing F5 to make sure these files are added into your Eclipseproject.

15. In the Nios II Eclipse window, click Project Build Project to generate .elffile.

16. Run the following command in Nios II Command Shell to convert the .elf fileinto .hex.

elf2hex --input=<elf_filename>.elf --base=0x40000 --end=0x7ffff --width=32 --output=phylite_debug_kit_inst_mem.hex

17. Copy and add the phylite_debug_kit_inst_mem.hex file into the ed_synthproject folder.

18. Add the following command in the ed_synth.qsf to include thephylite_debug_kit_inst_mem.hex in your project compilation.

set_global_assignment -name MISC_FILEphylite_debug_kit_inst_mem.hex

19. Compile the ed_synth project file to generate .sof file to run the exampledesign on your hardware.

Design Example



Run the Dynamic Reconfiguration with Debug Kit Design Example

1. Download the phylite_debug_kit.sof file into the FPGA.

2. From the Quartus installation directory, double click on the Nios II CommandShell.bat to launch the Intel Nios® II command shell (command shell A). Repeatthe same step to launch a second command shell (command shell B).

3. In command shell B, use the following command to run Nios II terminalapplication for result printouts.

nios2-terminal --cable=<jtag_cable_num>

4. Use the following command in command shell A to reset the system and start thedynamic reconfiguration application.

quartus_stp -t issp.tcl phylite_debug_kit.qpf

Dynamic Reconfiguration Using Finite State Machine

This design example provides you a synthesizable system capable to perform dynamiccalibration for PHY Lite for Parallel Interfaces IP core in Intel Arria 10 and Intel Cyclone10 GX devices.

Features

• Perform dynamic reconfiguration using Avalon controller

• Read and write transactions monitoring

• Delay values monitoring

Software Requirements

• Intel Quartus Prime software

• Active-HDL, ModelSim* - Intel FPGA Edition, NCsim or VCS Simulator


This design example introduces the cfg_ctrl and avl_ctrl blocks, which work withthe sim_ctrl module to demonstrate the basic functionality of the PHY Lite forParallel Interfaces IPs Avalon-MM based reconfiguration. The agent is also modified toinsert delays on the data and clocks, which the new modules will compensate for.

NOTE: The cfg_ctrl module performs a simplistic reconfiguration of the interfacethat stops at the first working delay values. The design example only supportsimulation. A robust calibration algorithm should sweep over the entire valid range ofdelays to choose the correct value for the application.

Design Example



Figure 24. Dynamic Reconfiguration Using Finite State Machine Design ExampleThis figure shows a high-level view of the simulation design example with one group.

Side read/write command

Side read/write data

DRAM clock

Write commandRead commandAgent select

strobeData

sim_ctrl

DRAM clock

Latency Delays


PHY Lite DUT

PHY Lite ADDR/CMD


Read/Write command

Core clock

Read/Write enable


Agent (one per group in DUT)

cfg_ctrl avl_ctrlAvalon Bus

Dynamic Reconfiguration Only

Reconfiguration Flow Control

Avalon Bus

ref_clk_gen reset_gen

ref_clk

ref_clk

reset_n

reset_n

ref_clk

Driver

Strobe

Core clock

Lock

DataLock

Data

Table 57. Design Components Description

Component Description

ref_clk_gen Generates clock to reset_gen, PHY Lite for Parallel Interfaces ADDR/CMD(ref_clk), and PHY Lite for Parallel Interfaces DUT (ref_clk) blocks.

reset_gen Generates reset to PHY Lite for Parallel Interfaces ADDR/CMD and PHY Lite forParallel Interfaces DUT blocks.

sim_ctrl • Generates read/write commands to PHY Lite for Parallel Interfaces ADDR/CMDblock.

• Generates side read/write commands and data to Agent block.• Generates strobe and data to Driver block.

Driver Generates strobe and data for each group and to PHY Lite for ParallelInterfaces_DUT block.

PHY Lite for Parallel InterfacesADDR/CMD

Passing read/write commands and command clock from sim_ctrl to Agent.

Agent FIFO to store data from PHY Lite for Parallel Interfaces DUT and side read/writedata from sim_ctrl block.

cfg_ctrl This is configuration control block which performs read and write delay calibrationbefore test begin.The calibration results is passed to the PHY Lite for Parallel Interfaces DUTthrough Avalon Controller.Contains 4 FSMs:1. Main FSM – cfg_ctrl state2. Write Strobe FSM – Calibration state for Output Strobe3. Read Strobe FSM – Calibration state for Input Strobe4. Read Enable FSM – Calibration state for Strobe Enable and Input Data

avl_ctrl The Avalon controller is used to perform address translation to store delaysettings from the calibration done by cfg_ctrl block.

Design Example



Figure 25. Design Example Functional Flow

a)

b)

c)

d)

Start

Dynamically reconfigure data group's settings

Function name: reconfigure_grp

Reset cfg_ctrl module

Dynamically reconfigure write strobe settingFunction name: reconfigure_grp_write

Repeat step b) and c) until pass

Function name: reconfigure_grp_readDynamically reconfigure read strobe setting

Write data to DUT and read back to verify data is correct

Pin Type?

e) Done

a)

b)c)

d)

Dynamically reconfigure write strobe settingFunction name: reconfigure_grp_write

Write data to DUT and read back to verify data is correct

Repeat step b) and c) until passe) Done

Simulation ends

Simulation ends

Read from Pin Output Delay CSR registerWrite to DUT and read back

If fail, update Pin Output Delay Avalon register

Read from Strobe PVT Compensated Input Delay CSR register

a)

b)c)d) Repeat step b) and c) until passe) Done

Read from Pin Output Delay CSR registerWrite to DUT and read backIf fail, update Pin Output Delay Avalon register

Write to Agent and read backIf fail, update Strobe PVT Compensated Input Delay Avalon register

Write data to Agent and read back to verify data is correct

Output InputBidirectional

Dynamically reconfigure read enable and input data settings

a)b)

e) Get number of data pinf) Write to Agent and read back

g) If fail, update Pin PVT Compensated Input Delay Avalon register

h) Repeat f) and g) until passi) Done

c) If data[0] is mismatched, update Strobe Enable Phase Avalon register

Function name: reconfigure_grp_read_en_and_dataRead from Strobe Enable Phase CSR registerWrite to Agent and read back

d) Repeat step b) and c) until data[0] is matched

Related Information

Avalon Controller on page 74

Design Example



Generate the Dynamic Reconfiguration with Configuration Control Module Design Example

1. In Intel Quartus Prime software, instantiate PHY Lite for Parallel Interfaces IP core.

2. Customize parameter settings per your requirement and turn on the Usedynamic reconfiguration option.

3. Click Generate Example Design. Specify a directory name to generate thedesign example.

4. To generate Verilog or mixed-language simulation files, go to the design exampledirectory and run the following script in Nios II Command Shell.

quartus_sh -t make_sim_design.tcl VERILOG

5. To generate VHDL simulation files, go to the design example directory and run thefollowing script in Nios II Command Shell.

quartus_sh -t make_sim_design.tcl VHDL

Run the Dynamic Reconfiguration with Configuration Control Design Example

Follow these steps to compile and simulate the design:

1. Change the working directory to <Example Design>\sim\ed_sim\sim\<Simulator>.

2. Run the simulation script for the simulator of your choice. Refer to the table below.

Simulator Working Directory Steps

Modelsim <Example Design>\sim\ed_sim\sim\mentor

a. do msim_setup.tcl

b. ld_debug

c. Add desired signals into thewaveform window.

d. run -all

VCS <Example Design>\sim\ed_sim\sim\synopsys\vcs

a. sh vcs_setup.sh

VCSMX <Example Design>\sim\ed_sim\sim\synopsys\vcsmx

a. sh vcsmx_setup.sh

NCSim <Example Design>\sim\ed_sim\sim\cadence

a. sh ncsim_setup.sh

Aldec Example Design\sim\ed_sim\sim\aldec

a. do rivierapro_setup.tcl

b. ld_debug

c. Add desired signals into thewaveform window.

d. run -all

Design Example



Figure 26. Sample of Simulation Output

Design Example



Application Specific Design ExampleThis design example demonstrates the PHY Lite for Parallel Interfaces IP coreimplementation for a NAND Flash design in Intel Arria 10 devices.

The following figure shows the RTL view of the design example.

Figure 27. RTL Viewer for a NAND Flash Simple Design Based on the PHY Lite for ParallelInterfaces IP Core

Related Information

PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP Core NAND FLASH DesignExample

Implementation using the PHY Lite for Parallel Interfaces IP Core

You can configure the PHY Lite for Parallel Interfaces IP core to support multiplegroups (maximum 48 I/O pins each).

The following lists the possible implementations:

• Instantiates one PHY Lite for Parallel Interfaces IP core with two groups

— Bidirectional type for DQ and DQS signals

— Output type for Addr/Cmd signals

Note: Each group in the PHY Lite for Parallel Interfaces IP core can have 48 I/Os, and the IPsupports up to 18 groups.




https://www.altera.com/content/dam/altera-www/global/en_US/others/literature/ug/nand_flash_example_18_0.qar





Figure 28. General Tab Settings

Application Specific Design Example



Figure 29. Group 0 settings (Bidirectional type for DQ and DQS)




Figure 30. Group 1 settings (Output type for Addr/Cmd)

Related Information

PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP Core NAND FLASH DesignExample






PHY Lite for Parallel Interfaces IP Core User GuideDocument Archives

If an IP core version is not listed, the user guide for the previous IP core version applies.

IP Core Version User Guide

17.1 Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide

17.0 Altera PHYLite for Parallel Interfaces IP Core User Guide







https://www.altera.com/en_US/pdfs/literature/ug/archives/ug_altera_phylite-17-1.pdf

https://www.altera.com/en_US/pdfs/literature/ug/archives/ug_altera_phylite-17-0.pdf

https://www.altera.com/en_US/pdfs/literature/ug/archives/ug-altera-phylite-16.0.pdf






Document Revision History for PHY Lite for ParallelInterfaces IP Core User Guide

Document Version Intel QuartusPrime Version

Changes

2018.05.07 18.0 • Changed VCCN voltage supply name to VCCIO.• Renamed Addressing section to Reconfiguration Features and Register

Addressing.• Added Control Register Addresses tables for Intel Stratix 10, Intel Arria

10, and Intel Cyclone 10 GX devices.• Added Control Registers Description table for Intel Stratix 10, Intel

Arria 10, and Intel Cyclone 10 GX devices.• Added How can the PHY Lite IP RZQ pin location be assigned?

Knowledge Base Link in On-Chip Termination (OCT) section.• Added First PHYLite Instance in the Avalon Chain parameter to the

PHY Lite for Parallel Interfaces IP Core Parameter Settings table.• Made Example Design Avalon Controller section as a sub-section in

Dynamic Reconfiguration with Debug Kit Design Example.• Updated Avalon Controller Registers table with register descriptions.• Renamed Pin Output Phase feature to Pin Output Delay.• Updated the minimum interface frequency recommended for dynamic

reconfiguration to 533 MHz in the PHY Lite for Parallel Interfaces IPCore Parameter Settings table.

• Updated all IP names as per Intel rebranding.

Date Version Changes

November 2017 2017.11.30 • Added information about Intel FPGA PHYLite for Parallel Interfaces in IntelStratix 10 and Intel Cyclone 10 GX devices.

• Added note to Reference Clock on page 63 about using cascaded PLL as areference clock in Intel Arria 10 devices and a link to the KDB.

• Rebranded to Intel FPGA PHYLite for Parallel Interfaces IP core.

June 2017 2017.06.16 • Added a note for the I/O Column for Arria 10 Devices figure.• Updated Top-Level Interface diagram.• Updated OCT section.• Updated Guidelines: Group Pin Placement section.• Updated the reference clock source in the Reference Clock section.• Added Reset section.• Added a note on Report DDR function in

"<variation_name>_report_timing.tcl" section.• Updated Altera PHYLite for Parallel Interfaces IP Core Parameter Settings

table.— Removed Use core PLL reference clock connection parameter.— Added description for outclk (Reserved) parameter.— Updated OCT enable size values and description.— Added new parameter: Expose termination ports.

continued...








• Updated the description for ref_clk and interface_locked signals in theClock and Reset Interface Signals table.

• Updated the description for data_in and data_io signals in Input PathSignals table.

• Rebranded as Intel.

February 2017 2017.02.24 • Removed 30 and 40 Ohms termination values for SSTL-125, SSTL-135, andSSTL-15 I/O standards.

• Added a footnote to I/O Standards table recommending to use I/O standardsSSTL-15 Class I, SSTL-15 Class II, SSTL-18 Class I, SSTL-18 Class II, 1.2VHSTL Class I, 1.2V HSTL Class II, 1.5V HSTL Class I, 1.5V HSTL Class II,1.8V HSTL Class I, and 1.8V HSTL Class II for interface frequency equal orleass than 533 MHz and if input termination required.

• Added a footnote to I/O Standards table recommending to use I/O standardsSSTL-12, SSTL-125, SSTL-135, and SSTL-15 for interface frequency morethan 533 MHz and if input termination required.

October 2016 2016.10.28 • Added OCT section.• Clarified that output terminations can be calibrated and uncalibrated in I/O

Standards table.• Added footnote to clarify that uncalibrated output terminations do not require

RZQ pin in I/O Standard table.• Clarified ONFI device support is for synchronous mode only.• Updated Altera PHYLite for Parallel Interfaces IP Core supported Interface

Frequency table.• Clarified that reference clock using differential I/O standards support LVDS

input buffer only.• Updated I/O standards table with Valid Input Termination values.• Added new guidelines to Group Pin Placement section.• Updated Avalon Address for following features in the Address Map table:

— Pin PVT Compensated Input Delay— Strobe PVT compensated input delay— Strobe enable phase

• Added Altera PHYLite NAND Flash design example in Application SpecificDesign Example section.

• Removed IP Migration for Arria V, Cyclone V, and Stratix V section.

May 2016 2016.05.02 • Change External memory clock domain to Interface clock domain.• Removed VCO Frequency Multiplication Factor table.• Updated equation to calculate values for Input Strobe Setup Delay

Constraint and Input Strobe Hold Delay Constraint parameters.• Updated Address Map table with values to enable Avalon address and CSR

address.• Added a note to show the location of the Altera PHYLite for Parallel Interfaces

IP core in IP Catalog.• Updated values for OCT enable size parameter.• Added reference link to I/O Standards table in Data configuration

parameter description.• Added VCO clock frequency parameter in Parameter Settings table.• Updated Minimum Read Latency and Maximum Write Latency tables.• Updated PHYLite_delay_calculations.xlsx file.• Added issp.tcl file description in Dynamic Reconfiguration with Debug Kit

Design Example Generated Files table.• Updated steps to generate Dynamic Reconfiguration with Debug Kit design

example.• Added functional description, simulation steps and result to Dynamic

Reconfiguration with Configuration Control Module Design Example.• Added Altera PHYLite for Parallel Interfaces IP Core Document Archives

section.

continued...

Document Revision History for PHY Lite for Parallel Interfaces IP Core User Guide




December 2015 2015.12.11 • Changed Input Path Waveform figure label from "Intrinsic output delay atcurrent in and out rates and frequency" to "Intrinsic input delay at current inand out rates and frequency".

November 2015 2015.11.02 • Added Altera PHYLite for Parallel Interface IP core uses cases.• Clarified the condition for reference clock restriction in Reference Clock

section.• Added description for <variation_name>_parameter.tcl,

<variation_name>_report_timing.tcl, and<variation_name>_report_parameter_core.tcl files intoTiming Constratins and Files section.

• Provided example timing constraint command for increasing hold timeuncertainty value.

• Added footnote to clarified functionality for DQS A and DQS B signals.• Added new parameters in the Altera PHYLite for Parallel Interfaces IP Core

Parameter Settings table:— Copy parameters from another group— Group— OCT enable size— Inter Symbol Interference of the Read Channel— Inter Symbol Interference of the Write Channel— Group <x> Dynamic Reconfiguration Timing Settings

• Added new dynamic reconfiguration with debug kit hardware example design.• Added Write Latencies table in Parameter Settings.• Updated Read Latencies table.• Changed instances of Quartus II to Quartus Prime.

June 2015 2015.06.12 • Updated Avalon Address R/W from 3'h2 to 3'h4 for all features in AddressMap table.

• Added new parameter Use core PLL reference clock connection and Dataconfiguration in Altera PHYLite for Parallel Interfaces IP Core ParameterSettings table.

• Updated values in VCO Frequency Multiplication Factor table.

January 2015 2015.01.28 Updated related information link to Functional Description for External MemoryInterfaces in Arria 10 Devices.

December, 2014 2014.12.30 • Updated the name of the IP core from Altera PHYLite for Memory to AlteraPHYLite for Parallel Interfaces.

• Updated the maximum clock frequency from 800 MHz to 1333.333 MHz.• Clarified that to achieve timing closure at 800 MHz and above, you must use

dynamic reconfiguration to calibrate the interface.• Added data_out_n/data_io_n signals to the Output Path Signals table.• Added data_in_n/data_io_n signals to the Input Path Signals table.• Updated data_out/data_io and data_in/data_io signals in the Input

Path Signals and Output Path Signals tables.• Updated Parameter Settings table to include Group <x> Timing Settings

information.• Updated Timing section to include Input Strobe Setup Delay Constrain

and Input Strobe Hold Delay Constrain parameters information.

August, 2014 2014.08.18 • Renamed the term megafunction to IP core.• Added information about output path data alignment, input path data

alignment, OCT, I/O standards, placement restrictions, timing, dynamicreconfiguration.

• Added the PHYLite_delay_calculations.xlsx file.• Replaced ALTERA_PHYLite_nand_flash_example_131a10.qar file with

nand_flash_example_14.0a10.qar file.

November, 2013 2013.11.29 Initial release.

Document Revision History for PHY Lite for Parallel Interfaces IP Core User Guide



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