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IVY BRIDGEThe Third Generation

Processor

First chip to use Intel's 22nm tri-gate transistors Mobile Ivy Bridge - First to bring 4 cores into a 35W TDP First to use tri-gate, also called 3D, transistors 37 percent faster & use less than half the power of 2D

transistors

IVY BRIDGE

3D Transistors

3-D Tri-Gate transistors form conducting channels on 3 sides of a vertical fin structure, providing "fully

depleted" operation

Transistors have now entered the third dimension

50% less power consumption PCI Express 3.0 support Max CPU multiplier of 63 (57 for Sandy Bridge) RAM support up to 2800MT/s in 200MHz increments Intel HD Graphics with DirectX 11, OpenGL 3.1, and

OpenCL 1.1 support Built-in GPU have up to 16 execution units (EUs) New random number generator & RdRand instruction,

codenamed Bull Mountain Multiple 4K video playback

Ivy Bridge features

Up to 20% increase in CPU performance.

Up to 30% increase in integrated GPU performance.

Intel's performance targets

Backwards compatible with existing LGA-1155 motherboards

The new chipset family falls under the 7-series banner. 14 total USB ports, 4 of which are USB 3.0 capable 16 PCIe (1x16, 2x8 or 1x8 + 2x4) gen 3 lanes Performance similar to Sandy Bridge CPU but consume

less power Greater performance while consuming the same

amount of power

Motherboard & Chipset Support

IVY BRIDGE

4-wide with support for fusion of both x86 instructions & decoded uOps

Structures within the chip are now better optimized for single threaded execution

The number of execution units hasn't changed in Ivy Bridge Ivy Bridge's divider has twice the throughput of the unit in

Sandy Bridge Inclusion of a very high speed digital random number

generator (DRNG) & supervisory mode execution protection (SMEP).

IVY BRIDGE

High quality/high perfromance DRNG Designed to be Standards compliant New instruction: RDRAND - Available at all privilege levels/operating

modes RDRAND is enumerated via CPUID.1.ECX Can generate high quality random numbers at 2 - 3Gbps

DIGITAL RANDOM NUMBER GENERATOR (DRNG)

Supervisory Mode Execute Protection (SMEP)

Ivy Bridge introduces SMEP to help prevent Escalation of Privilege (EoP) security attacks

Prevents execution out of untrusted application memory while operating at a more privileged level

If CR4.SMEP set to 1 & in supervisor mode (CPL<3), instructions may not be executed from a linear address for which the user mode flag is 1

Available in both 32- & 64- bit operating modes SMEP is enumerated via CPUID.7.0.EBX

Last level cache (L3) is still shared via a ring bus between all cores

Quad-core Ivy Bridge CPUs will support up to 8MB of L3 cache

The private L1/L2s haven't increased from their sizes in Sandy Bridge

The memory controller also remains relatively unchanged, aside from some additional flexibility

Mobile IVB supports DDR3L in addition to DDR3, enabling 1.35V memory instead of the standard1.5V DDR3

Cache, Memory Controller & Overclocking Changes

DDR3L support - Low voltage DDR3 (DDR3L) support in mobile SKUs

Power optimizations - DRAM ODT optimization in mobile to reduce active power

CPU / Graphics Overclocking - Increased max ratio support (ratio 57 => 63) - Dynamic overclocking: Allows ratio change without a reboot

DDR Overclocking: - Support for up to 2800 MT/s (up from 2133) - Finer grain steps in adjusting frequency - Added 200 MHz

Cache, Memory Controller &

Overclocking Changes

Intel claimed that it could see an 18% increase in performance at 1V compared to its 32nm process.

Intel's 22nm transistors can run at 75 - 80% of the voltage of their 32nm counterparts.

Ivy Bridge's process alone should account for some pretty significant power savings

There are a few architectural changes in IVB that will reduce power consumption.

Power Efficiency Improvements

Sandy Bridge introduced the System Agent refers to the display output, memory controller, DMI and PCI Express interfaces.

L3 cache was no longer included in the uncore and thus it wasn't a part of the System Agent.

The System Agent operates on a separate voltage plane than the rest of the chip.

Lower System Agent voltage options for the lower voltage SKUs, which in turn helps power optimize those SKUs.

Lower System Agent Voltages

Intel defines 3 different voltages for every Sandy Bridge CPU: LFM, nominal and turbo

LFM is the lowest frequency the CPU can run at (e.g. completely idle)

Nominal is the frequency it is specified to run at (e.g. 3.3GHz for a 2500K)

Turbo is the highest available turbo frequency (e.g. 3.7GHz for a 2500K).

Voltage Characterization:

Properly route interrupt requests to cores that are already awake vs those that are asleep in their lowest power states

IVB will allow prioritizing performance as well Interrupt handling can thus be handled similarly to

how it is today, or optimally for power savings.

Power Aware Interrupt Routing

Configurable TDP/ Low Power Mode

An Ivy Bridge notebook with an optional dock that could enhance the cooling capabilities of the machine

When undocked the notebook's processor would operate at a max TDP of 17W.

Ultra portable chassis on the go, and higher clock speeds while docked

Configurable TDP/ Low Power Mode

Ivy Bridge HD Graphics: Architecture

The Ivy Bridge GPU adds support for OpenCL 1.1, DirectX 11 & OpenGL 3.1

This will finally bring Intel's GPU feature set on par with AMD's

Ivy also adds three display outputs (up from 2 in Sandy Bridge).

Ivy Bridge improves anisotropic filtering quality Scatter & gather operations now execute 32x faster

than Sandy Bridge.

Ivy Bridge HD Graphics: Architecture

µArchitecture plus 22nm offers: - Up to ~1/2 power at same performance * ~Double the performance / watt

Co-issue: - Extended Co-issue on EU to many more operation - More IPC per unit area - therefore less power to leakage

L3$: - Less BW need from LL$ = Less Energy spent

Power Optimizations

Quick Sync is a extremely high performing hardware video transcode engine

Quick Sync leverages a combination of fixed function hardware, IVB's video decode engine and the EU array.

The increase in EUs and improvements to their throughput both contribute to increases in Quick Sync transcoding performance

The combination of all of this results in up to 2x the video transcoding performance of Sandy Bridge.

There's also the option of seeing less of a performance increase but delivering better image quality.

Quick Sync Performance Improved

Sandy Bridge brought about a significant increase in CPU performance

But Ivy seems almost entirely dedicated to addressing Intel's aspirations in graphics.

We might see this trend continue, get more effective architectures by the developments in fabrication technologies.

Conclusion

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