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Page 2: Intel® MAX® 10 FPGA Design Guidelines · 2020-01-20 · 1. Intel® MAX® 10 FPGA Design Guidelines 1.1. Intel® MAX® 10 FPGA Design Guidelines This application note provides a

Contents

1. Intel® MAX® 10 FPGA Design Guidelines.........................................................................41.1. Intel® MAX® 10 FPGA Design Guidelines...................................................................41.2. Before You Begin................................................................................................... 4

1.2.1. Read through the Device Overview of the FPGA............................................. 51.2.2. Estimate design requirements..................................................................... 51.2.3. Review available design tools...................................................................... 51.2.4. Review available IP.................................................................................... 5

1.3. Design Specifications............................................................................................. 61.3.1. Create detailed design specifications............................................................ 61.3.2. Create detailed functional verification or test plan.......................................... 61.3.3. Select IP that affects system design, especially I/O interfaces..........................61.3.4. Ensure your board design supports the OpenCore Plus tethered mode.............. 71.3.5. Review available system development tools...................................................7

1.4. Device Selection....................................................................................................71.4.1. Consider the available device variants.......................................................... 71.4.2. Estimate the required logic, memory, and multiplier density............................ 81.4.3. Consider vertical device migration availability and requirements.......................81.4.4. Review resource utilization reports of similar designs......................................81.4.5. Reserve device resources for future development and debugging..................... 81.4.6. Estimate the number of I/O pins that you require...........................................91.4.7. Consider the I/O pins you need to reserve for debugging................................ 91.4.8. Verify that the number of LVDS channels are enough......................................91.4.9. Verify the number of PLLs and clock routing resources.................................... 91.4.10. Determine the device speed grade that you require...................................... 91.4.11. Determine the number of images supported for the device.......................... 10

1.5. Board Design...................................................................................................... 101.5.1. Early Board Design...................................................................................101.5.2. Power Pin Connections..............................................................................131.5.3. Configuration Pin Connections....................................................................151.5.4. General I/O Pin Connections......................................................................18

1.6. I/O and Clock Planning......................................................................................... 211.6.1. Early Pin Planning and I/O Assignment Analysis........................................... 211.6.2. I/O Features and Pin Connections...............................................................221.6.3. Clock Planning.........................................................................................271.6.4. I/O Simultaneous Switching Noise..............................................................28

1.7. Design Entry....................................................................................................... 291.7.1. Use synchronous design practices.............................................................. 291.7.2. Consider the following recommendations to avoid clock signals problems:....... 301.7.3. Use IP cores with the parameter editor....................................................... 301.7.4. Review the information on dynamic reconfiguration feature........................... 301.7.5. Consider the Intel's recommended coding styles to achieve optimal

synthesis results......................................................................................301.7.6. Enable the chip-wide reset to clear all registers if required.............................311.7.7. Use device architecture-specific register control signals.................................311.7.8. Review recommended reset architecture..................................................... 311.7.9. Review the synthesis options available in your synthesis tool......................... 321.7.10. Consider resources available for register power-up and control signals.......... 32

Contents

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1.7.11. Consider Intel's recommendations for creating design partitions................... 331.7.12. Perform timing budgeting and resource balancing between partitions............ 331.7.13. Create a design floorplan for incremental compilation partitions....................34

1.8. Design Implementation.........................................................................................341.8.1. Synthesis and Compilation........................................................................ 341.8.2. Timing Optimization and Analysis...............................................................371.8.3. Formal Verification................................................................................... 401.8.4. Power Analysis and Optimization................................................................40

1.9. Document Revision History....................................................................................43

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1. Intel® MAX® 10 FPGA Design Guidelines

1.1. Intel® MAX® 10 FPGA Design Guidelines

This application note provides a set of checklists that consist of design guidelines,recommendations, and factors to consider when you create designs using MAX® 10FPGAs.

• Use this document to help you plan the FPGA and system early in the designprocess, which is crucial for a successful design.

• Follow Intel’s recommendations throughout the design process to achieve goodresults, avoid common issues, and improve your design productivity.

Figure 1. MAX 10Design Flow

Specifications Early Planning Design Entry

Design Specifications• IP Selection

Device Selection

Early Board DesignPlanning

Early Pin Planningand I/O Assignment

Hierarchical Team-basedDesign Planning

Design Implementation

Synthesisand Compilation

Timing Optimizationand Analysis

Functional TimingSimulation

Formal Verification

Power Analysisand Optimization

I/O and Clock Planning

I/O Features andPin Connections

Clock Planning

I/O SSN Considerations

Board Design

Power Pins Planning

Configuration PinsPlanning

1.2. Before You Begin

Before you begin planning and designing your FPGA system, familiarize yourself withthe FPGA device features, and the design tools and IP that are available for the MAX10 device family.

M10-GUIDELINES | 2017.05.03

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1.2.1. Read through the Device Overview of the FPGA

The Device Overview provides an overview of the capabilities and options available fora device family. Read through the document to familiarize yourself with the devicefamily offerings and general features.

Related Information

MAX 10 FPGA Device Overview

1.2.2. Estimate design requirements

Create a rough estimate of the design in the following terms:

• Basic functions of the product

• Similar previous designs

• General device requirements

1.2.3. Review available design tools

Consider the available design, estimators, system builders, and verification tools. Thefollowing items are some of the available tools provided by Intel:

• Quartus® Prime software for design, synthesis, simulation, and programming;including integration with Qsys, simulation tools, and verification tools.

• Qsys system integration tool—next-generation tool that automatically generatesinterconnect logic to connect intellectual property (IP) functions and subsystems.

• Mentor Graphics* ModelSim* - Intel FPGA Edition simulation software.

• TimeQuest Timing Analyzer for static timing analysis with support for Synopsys*Design Constraints (SDC) format.

• PowerPlay® Power Analyzer for power analysis and optimization.

• Signal Probe and Signal Tap II Logic Analyzer debugging tools.

• External Memory Interface Toolkit available in the Quartus Prime software.

Related Information

• Design Tools ServicesFor more information design tools

• Design Software SupportFor more information on software support

• AN 632: SOPC Builder to Qsys Migration GuidelinesFor a guideline to migrate from SOPC Builder to Qsys

1.2.4. Review available IP

Intel and its FPGA IP partners offer a large selection of parameterized blocks of IPcores optimized for Intel® FPGAs that you can implement to reduce yourimplementation and verification time.

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Related Information

All Intellectual Property

1.3. Design Specifications

Typically, the FPGA is an important part of the overall system and affects the rest ofthe system design. Use the following checklist to start your design process.

1.3.1. Create detailed design specifications

Before you create your logic design or complete your system design, perform thefollowing:

• Specify the I/O interfaces for the FPGA

• Identify the different clock domains

• Include a block diagram of basic design functions

• Consider a common design directory structure—if your design includes multipledesigners, a common design directory structure eases the design integrationstages.

• When performing any UFM write or erase operation, make sure you provide stablepower connection. Loss of power supply during a write or erase operation cancause damage to the device.

1.3.2. Create detailed functional verification or test plan

A functional verification plan ensures the team knows how to verify the system.Creating a test plan at an early stage helps you design for testability andmanufacturability.

For example, if you plan to perform built-in-self test (BIST) functions to driveinterfaces, you can plan to use a UART interface with a Nios® II processor inside theFPGA device.

Related Information

Review available on-chip debugging tools on page 11

1.3.3. Select IP that affects system design, especially I/O interfaces

Include intellectual property (IP) blocks in your detailed design specifications. Takingthe time to create these specifications improves design efficiency.

Related Information

All Intellectual PropertyFor a list of available IP offered by Intel and Intel FPGA IP partners

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1.3.4. Ensure your board design supports the OpenCore Plus tetheredmode

You can program your FPGA and verify your design in hardware before you purchasean IP license by using the OpenCore Plus feature available for many IP cores.OpenCore Plus supports the following modes:

• Untethered—your design runs for a limited time.

• Tethered—your design runs for the duration of the hardware evaluation period.This mode requires an Intel FPGA download cable connected to the JTAG port onyour board and a host computer that runs the Quartus Prime Programmer. If youplan to use this mode, ensure that your board design supports this mode.

1.3.5. Review available system development tools

Intel provides a complete suite of development tools for every stage of your design.

Whether you are creating a complex FPGA design as a hardware engineer, writingsoftware for an embedded processor as a software developer, modeling a digital signalprocessing (DSP) algorithm, or focusing on system design, Intel has a tool that canhelp.

Related Information

• Design Tools Services.

• Design Software Support.

1.4. Device Selection

Use the following checklist to determine the device variant, density, and packagecombination that is suitable for your design.

1.4.1. Consider the available device variants

The MAX 10 FPGA family consist of several device variants that are optimized fordifferent application requirements.

Select a device based on I/O pin count, LVDS channels, package offering, logic/memory/multiplier density, single/dual supply device options, PLLs, clock routing, andspeed grade.

Consider the following feature options:

• Compact

• Flash

• Analog-to-digital converter (ADC)

Related Information

MAX 10 FPGA Device Overview

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1.4.2. Estimate the required logic, memory, and multiplier density

MAX 10 devices offer a range of densities that provide different amounts of devicelogic resources. Determining the required logic density can be a challenging part ofthe design planning process. Devices with more logic resources can implement largerand potentially more complex designs but generally have a higher cost. Smallerdevices have lower static power utilization.

Related Information

MAX 10 Embedded Multipliers User Guide

1.4.3. Consider vertical device migration availability and requirements

Determine whether you want the flexibility of migrating your design to another devicedensity. Choose your device density and package to accommodate any possible futuredevice migration to allow flexibility when the design nears completion.

To verify the pin migration compatibility, use the Pin Migration View window in theQuartus Prime software Pin Planner. The Pin Migration View window helps youidentify the difference in pins that can exist between migration devices:

• If one device has pins for connection to VCC or GND but are I/O pins on a differentdevice, the Quartus Prime software ensures these pins are not used for I/O. Formigration, ensure that these pins are connected to the correct PCB plane.

• If you are migrating between two devices in the same package, connect the pinsthat are not connected to the smaller die to VCC or GND on the larger die in youroriginal design.

Related Information

I/O ManagementFor more information about verifying the pin migration compatibility

1.4.4. Review resource utilization reports of similar designs

If you have other designs that target an Intel device, you can use their resourceutilization as an estimate for your new design. Coding style, device architecture, andoptimization options used in the Quartus Prime software can significantly affectresource utilization and timing performance of a design.

To estimate resource utilization for certain configurations of Intel's FPGA IP designs,refer to the respective MAX 10 user guides.

1.4.5. Reserve device resources for future development and debugging

Select a device that meets your design requirements with some safety margin in caseyou want to add more logic later in the design cycle, upgrade, or expand your design.You may also want additional space in the device to ease design floorplan creation foran incremental or team-based design.

Related Information

Consider reserving resources for debugging on page 11

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1.4.6. Estimate the number of I/O pins that you require

Determine the required number of I/O pins for your application, considering thedesign’s interface requirements with other system blocks. You can compile anyexisting designs in the Quartus Prime software to determine how many I/O pins areused.

Other factors can also affect the number of I/O pins required for a design, includingsimultaneous switching noise (SSN) concerns, pin placement guidelines, pins used asdedicated inputs, I/O standard availability for each I/O bank, differences between I/Ostandards and speed for row and column I/O banks, and package migration options.

Related Information

• I/O and Clock Planning on page 21

• Board Design on page 10

1.4.7. Consider the I/O pins you need to reserve for debugging

Intel provides a complete design debugging environment that easily adapts to yourspecific design requirements. When planning to debugging, you should decide whichI/O pins you need to reserve for debugging.

Related Information

Consider the guidelines to plan for debugging tools on page 11

1.4.8. Verify that the number of LVDS channels are enough

Larger densities and package pin counts offer more full-duplex LVDS channels fordifferential signaling. Ensure that your device density-package combination includesenough LVDS channels.

1.4.9. Verify the number of PLLs and clock routing resources

Verify that your chosen device density package combination includes enough PLLs andclock routing resources for your design. GCLK resources are shared between certainPLLs, which can affect the inputs that are available for use.

Related Information

I/O and Clock Planning on page 21For more details and references regarding clock pins and global routing resources

1.4.10. Determine the device speed grade that you require

The device speed grade affects the device timing performance and timing closure, aswell as power utilization. One way to determine which speed grade your designrequires is to consider the supported clock rates for specific I/O interfaces.

You can use the fastest speed grade while prototyping to reduce compilation timebecause less time is spent optimizing the design to meet timing requirements. If thedesign meets the timing requirements, you can then move to a slower speed grade forproduction to reduce cost.

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When migrating to a device of different speed grade, check the timing report from thetiming analysis to ensure that there is no timing violation between different blockswithin the MAX 10 device, between MAX 10 devices and other devices on the board.

Always design with a sufficient timing margin so that your design can work on devicesof different speed grades.

Related Information

• External Memory Interface Spec EstimatorFor information about supported clock rates for memory interfaces using I/Opins on different sides of the device in different device speed grades

• MAX 10 FPGA Device DatasheetFor information about the available speed grades

1.4.11. Determine the number of images supported for the device

Select a device that support dual configuration images, two FPGA bitstreams, if dualconfiguration feature is needed in your design. All MAX 10 devices support the dualconfiguration feature, except 10M02 device.

1.5. Board Design

1.5.1. Early Board Design

Early planning allows the FPGA team to provide early information to PCB board andsystem designers.

1.5.1.1. Select a configuration scheme

Intel offers a wide range of configuration solutions to configure MAX 10 devices.

Related Information

MAX 10 FPGA Configuration User GuideFor information about the internal configuration scheme, and the necessary andoptional pin settings

1.5.1.2. Ensure board support the required features:

• Data decompression—if you enable data compression, the storage requirementand the programming time (writing to flash) are reduced. The configuration time(writing to CRAM) is increased.

• Design security—this feature utilizes a 128-bit security key to protect the designsfrom unauthorized copying, reverse engineering, and tampering. The devices candecrypt configuration bitstreams using the AES algorithm. Design security is notavailable for the JTAG configuration scheme.

• Dual configuration—this feature is supported only in self-download mode.

• SEU mitigation—dedicated circuitry in the devices perform cyclic redundancy check(CRC) error detection and check for SEU errors automatically. To detect SEUerrors, use the CRC_ERROR pin to flag errors and design your system to takeappropriate action. If you do not enable the CRC error detection feature, you canalso use the CRC_ERROR pin as a design I/O pin.

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Related Information

MAX 10 FPGA Configuration User Guide

1.5.1.3. Plan for the Auto-restart after configuration error option

To reset the device internally by driving the nSTATUS pin low when a configurationerror occurs, enable the Auto-restart after configuration error option. The devicereleases its nSTATUS pin after the reset time-out period. This behavior allows you tore-initiate the configuration cycle. The nSTATUS pin requires an external 10-kΩ pull-up resistor to VCCIO.

1.5.1.4. Estimating configuration file size

To estimate the configuration file size, convert your configuration file in uncompressedRaw Binary File (.rbf). The .rbf file size provides the approximate uncompressedconfiguration file sizes.

Use uncompressed .rbf size only to estimate the file size before design compilation.Different configuration file formats, such as Hexadecimal (Intel-Format) File (.hex) orTabular Text File (.ttf) format, have different file sizes.

Related Information

MAX 10 FPGA Configuration User GuideFor more information on the uncompressed .rbf sizes for MAX 10 devices

1.5.1.5. Review available on-chip debugging tools

Take advantage of on-chip debugging features to analyze internal signals and performadvanced debugging techniques.

Different debugging tools work better for different systems and different designers.Early planning can reduce the time spent debugging, and eliminates design changeslater to accommodate your preferred debugging methodologies. Adding debug pinsmay not be enough, because of internal signal and I/O pin accessibility on the device.

Related Information

• System Debugging Tools OverviewFor more information about in-system debugging tools in the Quartus Primesoftware

• Virtual JTAG (sld_virtual_jtag) Megafunction User GuideFor more information about virtual JTAG

1.5.1.6. Consider the guidelines to plan for debugging tools

• Select on-chip debugging schemes early to plan memory and logic requirements,I/O pin connections, and board connections.

• If you want to use Signal Probe incremental routing, the Signal Tap II EmbeddedLogic Analyzer, Logic Analyzer Interface, In-System Memory Content Editor, In-System Sources and Probes, or Virtual JTAG IP core, plan your system and boardwith JTAG connections that are available for debugging.

• Plan for the small amount of additional logic resources used to implement theJTAG hub logic for JTAG debugging features.

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• For debugging with the Signal Tap II Embedded Logic Analyzer, reserve devicememory resources to capture data during system operation.

• Reserve I/O pins for debugging with SignalProbe or the Logic Analyzer Interface sothat you do not have to change the design or board to accommodate debuggingsignals later.

• Ensure the board supports a debugging mode where debugging signals do notaffect system operation.

• Incorporate a pin header or micro connector as required for an external logicanalyzer or mixed signal oscilloscope.

• To use debug tools incrementally and reduce compilation time, ensure incrementalcompilation is on so you do not have to recompile the design to modify the debugtool.

• To use the Virtual JTAG IP core for custom debugging applications, instantiate it inthe HDL code as part of the design process.

• To use the In-System Sources and Probes feature, instantiate the IP core in theHDL code.

• To use the In-System Memory Content Editor for RAM or ROM blocks or theLPM_CONSTANT IP core, turn on the Allow In-System Memory Content Editoroption to capture and update content independently of the system clock option forthe memory block in the parameter editor.

Related Information

• Quick Design Debugging Using Signal ProbeFor more information about debugging tools and methods

• Design Debugging Using the Signal Tap II Logic AnalyzerFor more information about debugging withSignal Tap II

• In-System Debugging Using External Logic AnalyzersFor more information about debugging with logic analyzers

• In-System Updating of Memory and ConstantsFor more information about debugging memory

• Design Debugging Using In-System Sources and ProbesFor more information about debugging sources and probes

• Virtual JTAG (sld_virtual_jtag

1.5.1.7. Use the PowerPlay Early Power Estimator (EPE) to estimate powersupplies and cooling solution

FPGA power consumption depends on logic design and is challenging to estimateduring early board specification and layout. However, it is an important designconsideration and must be estimated accurately to develop an appropriate powerbudget to design the power supplies, voltage regulators, decoupling capacitors, heatsink, and cooling system.

Use the PowerPlay EPE spreadsheet to estimate power, current, and device junctiontemperature before you have a complete design. The EPE calculates the estimatedinformation based on device information, planned device resources, operatingfrequency, toggle rates, ambient temperature, heat sinks information, air flow, boardthermal model, and other environmental considerations.

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• If you have an existing or partially-completed and compiled design—use theGenerate PowerPlay Early Power Estimator File command in the QuartusPrime software to provide input to the EPE spreadsheet.

• If you do not have an existing design—estimate manually the number of deviceresources used in your design and input into the EPE spreadsheet. If the deviceresources information changes during or after the design phase, your powerestimation results will be less accurate.

Related Information

• PowerPlay Early Power Estimators (EPE)

• Use power distribution network (PDN) tool to plan for power distribution anddecoupling capacitor selection on page 15

1.5.2. Power Pin Connections

The MAX 10 devices require various voltage supplies depending on your designrequirements. Use the following checklist to design the board for the FPGA power pinconnections.

1.5.2.1. Design the board for power-up

MAX 10 devices support hot socketing (hot plug-in/hot swap) and power sequencingwithout the use of external devices. Consider the following guidelines:

• During power-up, the output buffers are tri-stated and the internal weak pull-upresistors are disabled by default. You can enable the internal weak pull-upresistors through the Quartus Prime software.

• with weak pull-up resistors enabled until the device is configured and configurationpins drive out.

• Design the voltage power supply ramps to be monotonic—ensure that theminimum current requirement for the power-on-reset (POR) supplies is availableduring device power up. The following are the POR monitored power supplies:

VCC or VCC_ONE (after regulated down)

VCCIO of bank 1B and bank 8

VCCA

• Set the POR delay in the Quartus Prime software to ensure power supplies arestable. You can extend the POR delay by using an external component to assertthe nSTATUS pin low. To ensure the device configures properly and enters usermode, extend the POR delay if the board cannot meet the maximum power ramptime specifications.

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• Design power sequencing and voltage regulators for the best device reliability—although power sequencing is not required for correct operation, consider thepower-up timing of each rail to prevent problems with long-term device reliabilityif you are designing a multi-rail powered system.

• Take advantage of the power up sequence for instant-on feature. With instant-on,the device can directly enter user mode with the shortest time after powersupplies reach the required level. During power up, the control block reads thePOR delay value and instant-on setting bits. If the instant-on is set, the devicedirectly enters the initialization phase. If the instant-on feature is not selected, thePOR delay value delays the POR signal. Clear the DSM if you want to change thesetting.

• Connect the GND between boards before connecting the power supplies—Inteluses GND as a reference for hot-socketing operations and I/O buffer designs.Connecting the GND between boards before connecting the power suppliesprevents the GND on your board from being pulled up inadvertently by a path topower through other components on your board. A pulled up GND could otherwisecause an out-of-specification I/O voltage or current condition with the device.

Related Information

• MAX 10 Power Management User Guide.

• MAX 10 FPGA Device Family Pin Connection Guidelines

• MAX 10 FPGA Configuration User Guide

1.5.2.2. Review the list of required supply voltages and the power supply options

MAX 10 devices offer single and dual supply device options.

Related Information

MAX 10 FPGA Device DatasheetFor a list of the required supply voltages and the recommended operatingconditions

1.5.2.3. Ensure I/O power pin compatibility with I/O standards

The output pins of the devices will not conform to the I/O standard specifications if theVCCIO level is out of the recommended operating range of the I/O standard.

Related Information

MAX 10 General Purpose I/O User GuideFor a complete list of the supported I/O standards and VCCIO voltages

1.5.2.4. Ensure correct power pin connections

• Connect all power pins correctly.

• Connect VCCIO pins and VREF pins to support the I/O standards of each bank.

• For unused supplies, consider whether there is a need to ground, open, or retainthe power connection.

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Related Information

MAX 10 FPGA Device Family Pin Connection GuidelinesFor more information on connecting power pins

1.5.2.5. Determine power rail sharing

• Explore unique requirements for FPGA power pins or other power pins on yourboard, and determine which devices on your board can share a power rail. It isespecially important for you to consider the power supply sharing ability of devicesfrom different device families.

• Follow the suggested power supply sharing and isolation guidance, and the specificguidelines for each pin.

Related Information

• MAX 10 FPGA Device Family Pin Connection Guidelines.For more information about power sharing

• AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs.For more information on isolation guidance

1.5.2.6. Use power distribution network (PDN) tool to plan for power distributionand decoupling capacitor selection

MAX 10 devices include on-die decoupling capacitors to provide high-frequencydecoupling.

To plan power distribution and return currents from the voltage regulating module tothe FPGA power supplies, you can use the PDN design tool that optimizes the board-level PDN graphically. Although you can use SPICE simulation to simulate the circuit,the PDN design tool provides a fast, accurate, and interactive way to determine theright number of decoupling capacitors for optimal cost and performance trade-off.

Related Information

• AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) DesignMethodology

• Power Delivery Network (PDN) Tool User Guide

1.5.2.7. Review the following guidelines for PLL board design

• Connect all PLL power pins to power supplies to reduce noise even if the designdoes not use all the PLLs.

• Power supply nets should be provided by an isolated power plane, a power planecut out, or a thick trace.

Related Information

MAX 10 FPGA Device Family Pin Connection GuidelinesFor pin voltage requirements

1.5.3. Configuration Pin Connections

Depending on your configuration scheme, different pull-up or pull-down resistor, signalintegrity, and specific pin requirements apply. Connecting the configuration pinscorrectly is important. Use the following checklist to address common issues.

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1.5.3.1. Verify configuration pin connections and pull-up or pull-down resistorsare correct for your configuration schemes

Intel provides pin connection guidelines to help you plan your design These guidelinesdescribe each pin and give guidelines for their use.

Related Information

MAX 10 FPGA Device Family Pin Connection GuidelinesFor specifics about each configuration pin

1.5.3.2. Design configuration TCK pin using the same technique as in designinghigh-speed signal or system clock

• Noise on the TCK signal can affect JTAG configuration.

• For a chain of devices, noise on the TCK pin in the chain can cause JTAGprogramming or configuration to fail for the entire chain.

• For a chain of devices, ensure all devices in the JTAG chain are powered on duringJTAG programming or configuration.

1.5.3.3. Verify the JTAG pins are connected to a stable voltage level if not in use

JTAG configuration takes precedence over all configuration methods. If you do not usethe JTAG interface, do not leave the JTAG pins floating or toggling duringconfiguration.

To disable the JTAG circuitry, connect TCK pin to GND through a 1-kΩ resistor. ConnectTMS and TDI pins to VCCIO through a 1-kΩ resistor. Leave TDO unconnected.

1.5.3.4. Verify the JTAG pin connections to the download cable header

A device operating in JTAG mode uses the required TDI, TDO, TMS, and TCK pins. TheTCK pin does not support internal weak pull-down.

Connect the TCK pin to an external 1-kΩ to 10-kΩ pull-down resistor. The TDI andTMS pins have weak internal pull-up resistors. The JTAG output pin (TDO) and all JTAGinput pins are powered by VCCIO. The voltage range is 1.5 V to 3.3 V.

The download cable must be powered at 2.5 V when VCCIO of the JTAG pins arepowered at 2.5 V to 3.3 V to prevent voltage overshoot because JTAG pins do nothave internal PCI clamping diodes. The TCK pin must be pulled to ground. If the VCCIOof the JTAG pins are powered at 1.5 V or 1.8 V, the download cable should be poweredby the same VCCIO.

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1.5.3.5. Review the following JTAG pin connections guidelines:

• If you have multiple devices in the chain, connect the TDO pin of a device to theTDI pin of the next device in the chain.

• Noise on the JTAG pins during configuration, user mode, or power-up can causethe device to go into an undefined state or mode.

• To disable the JTAG state machine during power-up, pull the TCK pin low througha 1-kΩ resistor to ensure that an unexpected rising edge does not occur on TCK.

• Pull TMS and TDI high through a 1-kΩ to 10-kΩ resistor.

1.5.3.6. Ensure the download cable and JTAG pin voltages are compatible

The download cable interfaces with the JTAG pins of your device. The operatingvoltage supplied to the Intel FPGA download cable by the target board through the 10-pin header determines the operating voltage level of the download cable. The JTAGpins are powered by VCCIO.

In a JTAG chain containing devices with different VCCIO levels, the devices with ahigher VCCIO level should drive the devices with the same or lower VCCIO level. A one-level shifter is required at the end of the chain with this device arrangement. If thisarrangement is not possible, you have to add more level shifters into the chain.

Related Information

JTAG Boundary-Scan Testing User GuideFor recommendations about connecting a JTAG chain with multiple voltages acrossthe devices in the chain

1.5.3.7. Buffer the JTAG signal according to the following guidelines:

• If a cable drives three or more devices, buffer the JTAG signal at the cableconnector to prevent signal deterioration.

• Anything added to the board that affects the inductance or capacitance of theJTAG signals increases the likelihood that a buffer should be added to the chain.

• Each buffer should drive no more than eight loads for the TCK and TMS signals,which drive in parallel. If jumpers or switches are added to the path, decrease thenumber of loads.

Related Information

MAX 10 JTAG Boundary-Scan Testing User GuideFor more information about JTAG pin sharing

1.5.3.8. Ensure all devices in the chain are connected properly

If your device is in a configuration chain, ensure all devices in the chain are connectedproperly and powered on.

1.5.3.9. Determine if you need to turn on device-wide output enable

The MAX 10 device supports an optional chip-wide output enable that allows you tooverride all tri-states on the device I/Os. When the DEV_OE pin is driven low, all I/Opins are tri-stated; when this pin is driven high, all pins behave as programmed.

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To use the chip-wide output enable feature:

• Turn on Enable device-wide output enable (DEV_OE) under the Generalcategory of the Device and Pin Options dialog box in the Quartus Primesoftware before compiling your design

• Ensure that the DEV_OE pin is driven to a valid logic level on your board

• Do not leave the DEV_OE pin floating

1.5.4. General I/O Pin Connections

Use the following checklist to plan your general I/O pin connections and to improvesignal integrity.

1.5.4.1. Specify the state of unused I/O pins

• To reduce power dissipation, set clock pins and other unused I/O pins As inputstri-stated. By default, the Quartus Prime software set the input pins tri-statedwith weak pull-up resistor enabled.

• To improve signal integrity, in the Reserve all unused pins option under theUnused Pins category of the Device and Pin Options dialog box of the QuartusPrime software, set the unused pins As output driving ground. This settingreduces inductance by creating a shorter return path and reduces noise on theneighboring I/Os. However, do not use this approach if it results in many via pathsthat causes congestion for signals under the device.

• Carefully check the pin connections in the Pin-Out File (.pin) generated by theQuartus Prime software when you compile your design. The .pin file specifieshow you should connect the device pins. I/O pins specified as GND can be leftunconnected or connected to ground for improved noise immunity. Do not connectRESERVED pins.

1.5.4.2. Refer to the Board Design Resource Center

If your design has high-speed signals the board design has a major impact on thesignal integrity in the system.

Related Information

• Board Design Resource CenterFor more information about signal integrity and board design

• AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-SpeedChannel Routing.

For more information about high-speed board stack-up

• AN 529: Via Optimization Techniques for High-Speed Channel Designs.For more information about high-speed designs

• AN 530: Optimizing Impedance Discontinuity Caused by Surface Mount Pads forHigh-Speed Channel Designs.

For more information about signal routing layers

• I/O Management, Board Development Support, and Signal Integrity AnalysisResource Center

For more information on board-level signal integrity information related to theQuartus Prime software

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1.5.4.3. Design VREF pins to be noise free

Voltage deviation on a VREF pin can affect the threshold sensitivity for inputs.

Related Information

I/O Features and Pin Connections on page 22For more information about VREF pins and I/O standards

1.5.4.4. Refer to the Board Design Guideline Solution Center

Noise generated by SSN—when too many pins in close proximity change voltage levelsat the same time—can reduce the noise margin and cause incorrect switching. Forexample, consider these board layout recommendations:

• Break out large bus signals on board layers close to the device to reduce crosstalk.

• If possible, route traces orthogonally if two signal layers are next to each other,and use a separation of two to three times the trace width.

Related Information

• Board Design Guidelines Solution CenterFor more board layout recommendations that can help with noise reduction

• I/O Simultaneous Switching Noise on page 28For a list of recommendations for I/O and clock connections

1.5.4.5. Verify I/O termination and impedance matching

Voltage-referenced I/O standards require both a VREF and a termination voltage (VTT).The reference voltage of the receiving device tracks the termination voltage of thetransmitting device. Consider the following items:

• Each voltage-referenced I/O standard requires a unique termination setup. Forexample, a proper resistive signal termination scheme is critical in SSTL-2standards to produce a reliable DDR memory system with superior noise margin.

• Although single-ended, non-voltage-referenced I/O standards do not requiretermination, impedance matching is necessary to reduce reflections and improvesignal integrity.

• Differential I/O standards typically require a termination resistor between the twosignals at the receiver. The termination resistor must match the differential loadimpedance of the signal line.

The MAX 10 on-chip series termination provides the convenience of no externalcomponents. You can also use external pull-up resistors to terminate the voltage-referenced I/O standards such as SSTL and HSTL.

Related Information

MAX 10 General Purpose I/O User GuideFor a complete list of on-chip termination (OCT) support for each I/O standard

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1.5.4.6. Perform full board routing simulation using IBIS models

To ensure that the I/O signaling meets receiver threshold levels on your board setup,perform full board routing simulation with third-party board-level simulation toolsusing an IBIS model.

To select the IBIS output in the Quartus Prime software, on the Assignments menu,click Settings. Navigate to the Board-Level page of the EDA Tool Settingscategory. Under the Board-level signal integrity analysis section, in the Formatoption, select IBIS.

Related Information

Signal Integrity Analysis with Third-Party Tools

1.5.4.7. Configure board trace models for Quartus Prime advanced timinganalysis

For a system to operate properly, signal integrity and board routing propagationdelays must be taken into consideration. If you use an FPGA with high-speedinterfaces in your board design, analyze the board level timing as part of the I/O andboard planning.

Differential I/Os at the top left corner are located in the low speed region.

To generate a more accurate I/O delays and extra reports to gain better insights intothe signal behavior at the system level, turn on Enable Advanced I/O Timing underthe TimeQuest Timing Analyzer category in the Settings dialog box of yourQuartus Prime project. With this option turned on, the TimeQuest Timing Analyzeruses simulation results for the I/O buffer, package, and board trace model to generatethe I/O delays.

You can use the advanced timing reports as a guide to make changes to the I/Oassignments and board design to improve timing and signal integrity.

Related Information

• MAX 10 Device Pin-Outs.For more information about the performance of these I/O pins

• MAX 10 FPGA Device Datasheet.For more information about I/O pins

1.5.4.8. Review your pin connections

Intel provides schematic review worksheets based on the device Pin ConnectionGuidelines and other board-level pin connections literature that you need to considerwhen you finalize your schematics.

Related Information

MAX 10 Device Schematic Review WorksheetFor more information on finding mistakes in schematics and adhering to designguidelines

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1.6. I/O and Clock Planning

1.6.1. Early Pin Planning and I/O Assignment Analysis

In many design environments, FPGA designers want to plan top-level FPGA I/O pinsearly so that board designers can start developing the PCB design and layout.

1.6.1.1. Verify pin locations early in the FPGA place-and-route software

The FPGA I/O capabilities and board layout guidelines influence pin locations and othertypes of assignments. Starting FPGA pin planning early improves the confidence inearly board layouts, reduces the chance of error, and improves the overall time-to-market.

1.6.1.2. Use the Quartus Prime Pin Planner for I/O pin planning, assignments,and validation

Early in the design process, the system architect typically has information about thestandard I/O interfaces (such as memory and bus interfaces), IP cores to be used inthe design, and any other I/O-related assignments defined by system requirements.

You can use the Quartus Prime Pin Planner for I/O pin assignment planning,assignment, and validation:

• The Quartus Prime Start I/O Assignment Analysis command checks that pinlocations and assignments are supported in the target FPGA architecture. Checksinclude reference voltage pin usage, pin location assignments, and mixing of I/Ostandards.

• You can use I/O Assignment Analysis to validate I/O-related assignments that youmake or modify throughout the design process.

• The Create/Import IP core feature of the Pin Planner interfaces with the parametereditor, and enables you to create or import custom IP cores that use I/Ointerfaces.

• Enter PLL and LVDS blocks. Then, use the Create Top-Level Design Filecommand to generate a top-level design netlist file.

• You can use the I/O analysis results to change pin assignments or IP parametersand repeat the checking process until the I/O interface meets your designrequirements and passes the pin checks in the Quartus Prime software.

After planning is complete, you can pass the preliminary pin location informationto PCB designers.

After the design is complete, you can use the reports and messages generated bythe Quartus Prime Fitter for the final sign-off of the pin assignments.

Related Information

• MAX 10 General Purpose I/O User GuideFor more information about the I/O restrictions guidelines

• Managing Device I/O PinseFor more information about I/O assignment and analysis

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1.6.1.3. Check I/O restrictions related to ADC usage

The Quartus Prime software uses physics-based rules to define the number of I/O pinsallowed in a particular bank based on the I/O's drive strength. These rules are basedon noise calculation to analyze accurately the impact of I/O placement on the ADCperformance. If you use the ADC block in your design, Intel recommends that youfollow the guidelines.

Related Information

MAX 10 General Purpose I/O User GuideFor more information about ADC I/O restriction guidelines

1.6.2. I/O Features and Pin Connections

Use the checklist in this section for guidelines related to I/O features, I/O signal types,I/O standards, I/O banks memory interfaces, pad placements, and special pinconnections.

Related Information

• MAX 10 FPGA Device Family Pin Connection Guidelines

• MAX 10 Device Pin-Outs

1.6.2.1. Determine if your system requires single-ended I/O signaling

• Single-ended I/O signaling provides a simple rail-to-rail interface.

• The speed is limited by the large voltage swing and noise.

• Single-ended I/Os do not require termination, unless reflection in the systemcauses undesirable effects.

Related Information

MAX 10 General Purpose I/O User GuideFor more information about the I/O restrictions guidelines

1.6.2.2. Determine if your system requires voltage-referenced signaling

• Voltage-referenced signaling reduces the effects of simultaneous switching outputs(SSO) from pins changing voltage levels at the same time (for example, externalmemory interface data and address buses).

• Voltage-referenced signaling provides an improved logic transition rate with areduced voltage swing, and minimizes noise caused by reflection with atermination requirement.

• Additional termination components are required for the reference voltage source(VTT).

Related Information

MAX 10 General Purpose I/O User GuideFor more information about the VREF restrictions guidelines

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1.6.2.3. Determine if your system requires differential signaling

• Differential signaling eliminates the interface performance barrier of single-endedand voltage-referenced signaling, with superior speed using an additional invertedclosely-coupled data pair.

• Differential signaling avoids the requirement for a clean reference voltage. This ispossible because of lower swing voltage and noise immunity with a common modenoise rejection capability.

• Considerations for this implementation include the requirements for a dedicatedPLL to generate a sampling clock, and matched trace lengths to eliminate thephase difference between an inverted and non-inverted pair.

• Allow the software to assign locations for the negative pin in differential pin pairs.You only need to assign the positive pins.

Related Information

MAX 10 General Purpose I/O User GuideFor more information about the differential I/O restrictions guidelines

1.6.2.4. Select a suitable signaling type and I/O standard for each I/O pin

Ensure that the appropriate I/O standard support is supported in the targeted I/Obank.

Place I/O pins that share voltage levels in the same I/O bank

• Certain I/O banks can support different I/O standards and voltage levels.

• You can assign I/O standards and make other I/O-related settings in the PinPlanner.

• Use the correct dedicated pin inputs for signals such as clocks and global controlsignals.

Related Information

• MAX 10 General Purpose I/O User Guide.

• MAX 10 High-Speed LVDS SERDES User Guide.

1.6.2.5. Verify that all output signals in each I/O bank are intended to drive outat the bank's assigned VCCIO voltage level

• The board must supply each bank with one VCCIO voltage level for every VCCIO pinin a bank.

• Each I/O bank is powered by the VCCIO pins of that particular bank and isindependent of the VCCIO of other I/O banks.

• A single I/O bank supports output signals that are driving at the same voltage asthe VCCIO.

• An I/O bank can simultaneously support any number of input signals with differentI/O standards.

Related Information

MAX 10 General Purpose I/O User Guide

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1.6.2.6. Verify that all voltage-referenced signals in each I/O bank are intendedto use the bank's VREF voltage (for devices that support VREF pins)

• To accommodate voltage-referenced I/O standards, each I/O bank supportsmultiple VREF pins feeding a common VREF bus. Set the VREF pins to the correctvoltage for the I/O standards in the bank.

• Each I/O bank can only have a single VCCIO voltage level and a single VREF voltagelevel at a given time. If the VREF pins are not used as voltage references, the pinscannot be used as generic I/O pins and must be tied to the VCCIO of that samebank or GND.

• An I/O bank, including single-ended or differential standards, can support voltage-referenced standards as long as all voltage-referenced standards use the sameVREF setting.

• For performance reasons, voltage-referenced input standards use their own VCCIOlevel as the power source. You can place voltage-referenced input signals in abank with a VCCIO of 2.5 V or below.

• Voltage-referenced bidirectional and output signals must drive out at the VCCIOvoltage level of the I/O bank.

1.6.2.7. Check the I/O bank support for LVDS features

Different I/O banks include different support for LVDS signaling. Some banks havelower speed performance. Allocate the pins according to your data rate requirement.

Related Information

MAX 10 High-Speed LVDS SERDES User Guide

1.6.2.8. Verify the usage of the VREF pins that are used as regular I/Os

VREF pins have higher pin capacitance that results in a different I/O timing:

• Do not use these pins in a grouped interface such as a bus.

• Do not use these pins for high edge rate signals such as clocks.

1.6.2.9. Test pin connections with boundary-scan test

A boundary-scan test allows you to test pin connections at board level without usingphysical test probes while the device is operating normally. To perform the boundary-scan test, you must have the boundary-scan description language (BSDL) file of thedevice.

Use the BSDL files from www.altera.com to perform boundary-scan test on pre-configured MAX 10 devices. For post-configured devices, you must modify the BSDLfile according to the design.

Related Information

BSDL SupportFor information on performing boundary-scan test after configuration, BSDLgeneration tool, and guidelines

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1.6.2.10. Use the UNIPHY IP core for each memory interface, and followconnection guidelines

The self-calibrating UNIPHY IP core is optimized to take advantage of the MAX 10structure. The UNIPHY IP core allows you to set external memory interface featuresand helps set up the physical interface (PHY) best suited for your system. When youuse the Intel memory controller IP core functions, the UNIPHY IP core is instantiatedautomatically.

If you design multiple memory interfaces into the device using Intel FPGA IP, generatea unique interface for each instance to ensure good results instead of designing it onceand instantiating it multiple times.

Related Information

Planning Pin and FPGA Resources

1.6.2.11. Use dedicated DQ/DQS pins and DQ groups for memory interfaces

The data strobe DQS and data DQ pin locations are fixed in MAX 10 devices. Beforeyou design your device pin-out, refer to the memory interface guidelines for detailsand important restrictions related to the connections for these and other memoryrelated signals.

Related Information

• Volume 2: Design GuidelinesFor more information about external memory guidelines

• MAX 10 External Memory Interface User GuideFor more information about MAX 10 external memory interfaces

• External Memory Solutions CenterFor more information about the memory spec estimator

1.6.2.12. Make dual-purpose pin settings and check for any restrictions whenusing these pins as regular I/O

You can use dual-purpose configuration pins as general I/Os after device configurationis complete. Select the desired setting for each of the dual-purpose pins on the Dual-Purpose Pins category of the Device and Pin Options dialog box. Depending on theconfiguration scheme, these pins can be reserved as regular I/O pins, as inputs thatare tri-stated, as outputs that drive ground, or as outputs that drive an unspecifiedsignal.

For configuration pins that used as general purpose I/Os, take note of the limitationsof the pins when operating in user mode.

You can also use dedicated clock inputs, which drive the GCLK networks, as generalpurpose input pins if they are not used as clock pins. If you use the clock inputs asgeneral inputs, the I/O registers use arithmetic logic module (ALM)-based registersbecause the clock input pins do not include dedicated I/O registers.

The device-wide reset and clear pins are available as design I/Os if they are notenabled.

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Related Information

• MAX 10 General Purpose I/O User Guide.

• MAX 10 FPGA Configuration User Guide.

• Determine if you need to turn on device-wide output enable on page 17

• Enable the chip-wide reset to clear all registers if required on page 31

1.6.2.13. Review available device I/O features that can help I/O interfaces

Check the available I/O features and consider the following guidelines:

• Programmable current strength—ensure that the output buffer current strength issufficiently high, but does not cause excessive overshoot or undershoot thatviolates voltage threshold parameters for the I/O standard. Intel recommendsperforming an IBIS or SPICE simulations to determine the right current strengthsetting for your specific application.

• Programmable slew rate—confirm that your interface meets its performancerequirements if you use slower slew rates. Intel recommends performing IBIS orSPICE simulations to determine the right slew rate setting for your specificapplication.

• Programmable input/output element (IOE) delays—helps read and time marginsby minimizing the uncertainties between signals in the bus. For delayspecifications, refer to the relevant device datasheet.

• Open-drain output—if configured as an open-drain, the logic value of the output iseither high-Z or 0. This feature is used in system-level control signals that can beasserted by multiple devices in the system. Typically, an external pull-up resistoris required to provide logic high.

• Bus hold—If the bus-hold feature is enabled, you cannot use the programmablepull-up option. Disable the bus-hold feature if the I/O pin is configured fordifferential signals. For the specific sustaining current driven through this resistorand the overdrive current used to identify the next driven input and level for eachVCCIO voltage, refer to the relevant device datasheet.

• Programmable pull-up resistors—weakly holds the I/O to the VCCIO level when inuser mode. This feature can be used with the open-drain output to eliminate theneed for an external pull-up resistor. If the programmable pull-up option isenabled, you cannot use the bus-hold feature.

• Programmable pre-emphasis—increases the amplitude of the high frequencycomponent of the output signal, and thus helps to compensate for the frequency-dependent attenuation along the transmission line.

Related Information

MAX 10 General Purpose I/O User Guide

1.6.2.14. Consider OCT features to save board space and verify that the requiredtermination scheme is supported for all pin locations

Driver-impedance matching provides the I/O driver with controlled output impedancethat closely matches the impedance of the transmission line to significantly reducereflections. OCT maintains signal quality, saves board space, and reduces externalcomponent costs.

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• OCT RS are supported in the same I/O bank for different I/O standards if they usethe same VCCIO supply voltage

• Each I/O in an I/O bank can be independently configured to support OCT RS orprogrammable current strength

• You cannot configure both OCT RS and programmable current strength or slewrate control for the same I/O buffer

Related Information

• MAX 10 General Purpose I/O User GuideFor more information about the support and implementation of OCT

• MAX 10 High-Speed LVDS SERDES User Guide.For more information about high-speed design

1.6.3. Clock Planning

The first stage in planning your clocking scheme is to determine your system clockrequirements:

• Understand your device’s available clock resources and correspondingly plan thedesign clocking scheme. Consider your requirements for timing performance, andhow much logic is driven by a particular clock.

• Based on your system requirements, define the required clock frequencies for yourFPGA design and the input frequencies available to the FPGA. Use thesespecifications to determine your PLL scheme.

• Use the Quartus Prime parameter editor to enter your settings in ALTPLL IP core,and check the results to verify whether particular features and input/outputfrequencies can be implemented in a particular PLL.

1.6.3.1. Use the device PLLs for clock management

Connect clock inputs to specific PLLs to drive specific low-skew routing networks.Analyze the global resource availability for each PLL and the PLL availability for eachclock input pin. Use the following descriptions for the clock signals in your design:

• The GCLK networks can drive throughout the entire device, serving as low-skewclock sources for device logic.

• IOEs and internal logic can also drive GCLKs to create internally generated GCLKsand other high fan-out control signals; for example, synchronous or asynchronousclears and clock enables.

• PLLs cannot be driven by internally-generated GCLKs. The input clock to the PLLmust come from dedicated clock input pins or from another pin/PLL-fed GCLK.

1.6.3.2. Ensure that you select the correct PLL feedback compensation mode

MAX 10 PLLs support four different clock feedback modes.

Related Information

MAX 10 Clocking and PLL User GuideFor more information about clock feedback modes

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1.6.3.3. Check that the PLL offers the required number of clock outputs and usededicated clock output pins

You can connect clock outputs to dedicated clock output pins or clock networks.

MAX 10 PLL only allows one clock output per PLL block. If your device have 4 PLLs,there are 4 clock outputs from the PLLs.

1.6.3.4. Use the clock control block for clock selection and power-down

Every GCLK network has its own clock control block. The control block provides thefollowing features that you can use to select different clock input signals or power-down clock networks to reduce power consumption without using any combinationallogic in your design:

• Clock source selection (with dynamic selection)

• GCLK multiplexing

• Clock power down (with static or dynamic clock enable or disable)

In MAX 10 devices, the clkena signals are supported at the clock network levelinstead of at the PLL output counter level. This allows you to gate off the clockeven when you are not using a PLL. You can also use the clkena signals tocontrol the dedicated external clocks from the PLLs.

Related Information

MAX 10 Clocking and PLL User Guide

1.6.3.5. Instantiate PLL with ADC

You can only use the PLL C0 counter to connect to the ADC reference clock pin.

1.6.4. I/O Simultaneous Switching Noise

SSN is a concern when too many I/Os (in close proximity) change voltage levels at thesame time. Use the checklist in this section for recommendations to plan I/O and clockconnections.

1.6.4.1. Consider the following recommendations to mitigate I/O simultaneousswitching noise:

• Analyze the design for possible SSN problems.

• Reduce the number of pins that switch the voltage level at exactly the same timewhenever possible.

• Use differential I/O standards and lower-voltage standards for high-switching I/Os.

• Use lower drive strengths for high-switching I/Os. The default drive strengthsetting might be higher than your design requires.

• Reduce the number of simultaneously switching output pins within each bank.Spread output pins across multiple banks if possible.

• Spread the switching I/Os evenly throughout the bank to reduce the number ofaggressors in a given area to reduce SSN if bank usage is substantially below100%.

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• Separate simultaneously switching pins from input pins that are susceptible toSSN.

• Place important clock and asynchronous control signals near ground signals andaway from large switching buses.

• Avoid using I/O pins one or two pins away from PLL power supply pins for high-switching or high-drive strength pins.

• Use staggered output delays to shift the output signals through time, or useadjustable slew rate settings.

Related Information

• I/O Features and Pin Connections on page 22

• Signal & Power Integrity Design Techniques for SSN Webcast

1.6.4.2. Check on the pin connection guidelines for the ADC pins

The Quartus Prime software uses physics-based rules to define the number of I/O pinsallowed in a particular bank based on the I/O's drive strength. These rules are basedon noise calculation to analyze accurately the impact of I/O placement on the ADCperformance. If you use the ADC block in your design, Intel recommends that youfollow the guidelines.

Related Information

MAX 10 FPGA Device Family Pin Connection GuidelinesFor more information about the filter type requirement at the ADC power pin,analog input pins, and VREF pin

1.7. Design Entry

In complex FPGA design development, design practices, coding styles, and IP coreusage have an enormous impact on your device's timing performance, logic utilization,and system reliability. In addition, while planning and creating the design, plan for ahierarchical or team-based design to improve design productivity.

1.7.1. Use synchronous design practices

In a synchronous design, a clock signal triggers all events. When all of the registers’timing requirements are met, a synchronous design behaves in a predictable andreliable manner for all process, voltage, and temperature (PVT) conditions. You caneasily target synchronous designs to different device families or speed grades.

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1.7.2. Consider the following recommendations to avoid clock signalsproblems:

• Use dedicated clock pins and clock routing for best results—dedicated clock pinsdrive the clock network directly, ensuring lower skew than other I/O pins. Use thededicated routing network to have a predictable delay with less skew for high fan-out signals. You can also use the clock pins and clock network to drive controlsignals like asynchronous reset.

• For clock inversion, multiplication, and division use the device PLLs.

• For clock multiplexing and gating, use the dedicated clock control block or PLLclock switchover feature instead of combinational logic.

• If you must use internally generated clock signals, register the output of anycombinational logic used as a clock signal to reduce glitches. For example, if youdivide a clock using combinational logic, clock the final stage with the clock signalthat was used to clock the divider circuit.

• In multi-clock designs, ensure that signals crossing clock domains are properlysynchronized using the synchronizer, a handshake mechanism, or a FIFO.

Related Information

MAX 10 Clocking and PLL User GuideFor more information about clock networks

1.7.3. Use IP cores with the parameter editor

Instead of coding your own logic, save your design time by using Intel FPGA IP cores—a library of parameterized modules and device-specific IP cores. The IP cores areoptimized for Intel FPGA device architectures and can offer more efficient logicsynthesis and device implementation.

To ensure that you set all ports and parameters correctly, use the Quartus Primeparameter editor to build or change IP cores parameters.

For detailed information about a specific IP core, refer to the respective MAX 10 userguides.

1.7.4. Review the information on dynamic reconfiguration feature

The MAX 10 devices support dynamic reconfiguration—dynamically change the PMAsettings or protocols of a channel affecting data transfer on adjacent channels.

1.7.5. Consider the Intel's recommended coding styles to achieve optimalsynthesis results

HDL coding styles can have a significant impact on the quality of results forprogrammable logic designs. For example, when designing memory and digital systemprocessing (DSP) functions, understanding the device architecture helps you to takeadvantage of the dedicated logic block sizes and configurations.

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• You can use the HDL templates provided in the Quartus Prime software asexamples for your reference. To access the templates, right click the editing areain the Quartus Prime text editor and click Insert Template.

• For additional tool-specific guidelines, refer to the documentation of your synthesistool.

Related Information

Recommended HDL Coding StylesFor specific HDL coding examples and recommendations

1.7.6. Enable the chip-wide reset to clear all registers if required

MAX 10 devices support an optional chip-wide reset that enables you to override allclears on all device registers, including the registers of the memory blocks (but notthe memory contents).

• DEV_CLRn pin is driven low—all registers are cleared or reset to 0. The affectedregister behave as if they are preset to a high value when synthesis performs anoptimization called NOT-gate-push back due to register control signals.

• DEV_CLRn pin is driven high—all registers behave as programmed.

To enable chip-wide reset, before compiling your design, turn on Enable device-wide reset (DEV_CLRn) under the Options list of the General category in theDevice and Pin Options dialog box of the Quartus Prime software.

1.7.7. Use device architecture-specific register control signals

Each MAX 10 logic array block (LAB) contains dedicated logic for driving registercontrol signals to its ALMs. It is important that the control signals use the dedicatedcontrol signals in the device architecture. In some cases, you may be required to limitthe number of different control signals in your design.

Related Information

MAX 10 FPGA Device ArchitectureFor more information about LAB and ALM architecture

1.7.8. Review recommended reset architecture

• If the clock signal is not available when reset is asserted, an asynchronous reset istypically used to reset the logic.

• The recommended reset architecture allows the reset signal to be assertedasynchronously and deasserted synchronously.

• The source of the reset signal is connected to the asynchronous port of theregisters, which can be directly connected to global routing resources.

• The synchronous deassertion allows all state machines and registers to start at thesame time.

• Synchronous deassertion avoids an asynchronous reset signal from being releasedat, or near, the active clock edge of a flipflop that can cause the output of theflipflop to go to a metastable unknown state.

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Related Information

www.sunburst-design.com/papersFor more information about good reset design

1.7.9. Review the synthesis options available in your synthesis tool

If you force a particular power-up condition for your design, use the synthesis optionsavailable in your synthesis tool:

• By default, the Quartus Prime software Integrated Synthesis turns on the Power-Up Don’t Care logic option that assumes your design does not depend on thepower-up state of the device architecture. Other synthesis tools might use similarassumptions.

• Designers typically use an explicit reset signal for the design that forces allregisters into their appropriate values after reset but not necessarily at power-up.You can create your design with asynchronous reset that allows you to power upthe design safely with the reset active, regardless of the power-up conditions ofthe device.

• Some synthesis tools can also read the default or initial values for registeredsignals in your source code and implement the behavior in the device. Forexample, the Quartus Prime software Integrated Synthesis converts HDL defaultand initial values for registered signals into Power-Up Level settings. Thesynthesized behavior matches the power-up conditions of the HDL code during afunctional simulation.

• Registers in the device core always power up to a low (0) logic level in the physicaldevice architecture. If you specify a high power-up level or a non-zero reset value(preset signal), synthesis tools typically use the clear signals available on theregisters and perform the NOT-gate push back optimization technique. If youassign a high power-up level to a register that is reset low, or assign a low power-up value to a register that is preset high, synthesis tools cannot use the NOT-gatepush back optimization technique and might ignore the power-up conditions.

Related Information

Quartus Prime Integrated SynthesisFor more information about the Power-Up Level settings and the altera_attributeassignment that sets the power-up state

1.7.10. Consider resources available for register power-up and controlsignals

To implement a reset and preset signal on the same register, synthesis tools emulatethe controls with logic and latches that can be prone to glitches because of thedifferent delays between the different paths to the register. In addition, the power-upvalue is undefined for these registers.

Related Information

Recommended HDL Coding StylesFor more information about reset logic and power up conditions

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1.7.11. Consider Intel's recommendations for creating design partitions

Partitioning a design for an FPGA requires planning to ensure optimal results when thepartitions are integrated and ensures that each partition is well placed, relative toother partitions in the device.

Follow Intel's recommendations for creating design partitions to improve the overallquality of results. For example, registering partition I/O boundaries keeps criticaltiming paths inside one partition that can be optimized independently. Plan yoursource code so that each design block is defined in a separate file. The software canautomatically detect changes to each block separately.

Use hierarchy in your design to provide more flexibility when partitioning. Keep yourdesign logic in the leaves of the hierarchy trees; that is, the top level of the hierarchyshould have very little logic, and the lower-level design blocks contain the logic.

Related Information

Best Practices for Incremental Compilation Partitions and Floorplan AssignmentsFor guidelines to help you create design partitions

1.7.12. Perform timing budgeting and resource balancing betweenpartitions

If your design is created in multiple projects, it is important that the system architectprovide guidance to designers of lower-level blocks to ensure that each partition usesthe appropriate device resources:

• Because the designs are developed independently, each lower-level designer hasno information about the overall design or how their partition connects with otherpartitions, which can lead to problems during system integration.

• The top-level project information, including pin locations, physical constraints, andtiming requirements, should be communicated to the designers of lower-levelpartitions before they start their design.

• The system architect can plan design partitions at the top level and use theQuartus Prime software Generate Bottom-Up Design Partition Scripts optionon the Project menu to automate the process of transferring top-level projectinformation to lower-level modules.

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1.7.13. Create a design floorplan for incremental compilation partitions

• A design floorplan avoids conflicts between design partitions and ensure that eachpartition is well-placed relative to other partitions. When you create differentlocation assignments for each partition, no location conflicts occur.

• A design floorplan helps avoid situations in which the Fitter is directed to place orreplace a portion of the design in an area of the device where most resourceshave already been claimed.

• Floorplan assignments are recommended for timing-critical partitions in top-downflows. You can use the Quartus Prime Chip Planner to create a design floorplanusing LogicLock region assignments for each design partition.

• With a basic design framework for the top-level design, the floorplan editorenables you to view connections between regions, estimate physical timing delayson the chip, and move regions around the device floorplan.

• After you compiled the full design, you can also view logic placement and locateareas of routing congestion to improve the floorplan assignments.

Related Information

• Best Practices for Incremental Compilation Partitions and Floorplan AssignmentsFor more information and guidelines in creating a design floorplan andplacement assignments in the floorplan

• Analyzing and Optimizing the Design Floorplan with the Chip Planner.For more information about the Floorplan Editor

1.8. Design Implementation

1.8.1. Synthesis and Compilation

1.8.1.1. Specify your synthesis tool and use correct supported version

The Quartus Prime software includes integrated synthesis that fully supports VerilogHDL, VHDL, Intel hardware description language (AHDL), and schematic design entry.You can also use industry-leading third-party EDA synthesis tools to synthesize yourVerilog HDL or VHDL design, and then compile the resulting output netlist file in theQuartus Prime software:

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• Specify a third-party synthesis tool in the New Project Wizard or the EDA ToolsSettings page of the Settings dialog box to use the correct Library Mapping File(.lmf) for your synthesis netlist.

• Intel recommends that you use the most recent version of third-party synthesistools because tool vendors are continuously adding new features, fixing toolissues, and enhancing performance for Intel devices.

• Different synthesis tools can give different results. If you want to select the best-performing tool for your application, you can experiment by synthesizing typicaldesigns for your application and coding style, and comparing the results.

• Perform placement and routing in the Quartus Prime software to get accuratetiming analysis and logic utilization results.

• Your synthesis tool may offer the capability to create a Quartus Prime project andpass constraints such as the EDA tool setting, device selection, and timingrequirements that you specified in your synthesis project. You can use thiscapability to save time when setting up your Quartus Prime project for placementand routing.

Related Information

• Quartus Prime Integrated Synthesis

• Synopsys Synplify Support

• Mentor Graphics Precision Synthesis Support

• Mentor Graphics LeonardoSpectrum Support

• Quartus Prime Software Release NotesFor information about the officially supported version of each synthesis tool ina Quartus Prime software version

1.8.1.2. Review resource utilization reports after compilation

After compilation in the Quartus Prime software, review the device resource utilizationinformation:

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• Use the information to determine whether the future addition of extra logic orother design changes introduce fitting difficulties.

• If your compilation results in a no-fit error, use the information to analyze fittingproblems.

• To determine resource usage, refer to the Flow Summary section of theCompilation Report for a percentage representing the total logic utilization, whichincludes an estimation of resources that cannot be used due to existingconnections or logic usage.

• For more detailed resource information, view the reports under ResourceSection in the Fitter section of the Compilation Report. The Fitter ResourceUsage Summary report breaks down the logic utilization information andindicates the number of fully and partially used ALMs, and provides other resourceinformation including the number of bits in each type of memory block.

There are also reports that describe some of the optimizations that occurredduring compilation. For example, if you use the Quartus Prime IntegratedSynthesis, the reports under the Optimization Results folder in the Analysis &Synthesis section provide information that includes registers that were removedduring synthesis. Use this report to estimate device resource utilization for apartial design to ensure that registers were not removed due to missingconnections with other parts of the design.

Low logic utilization does not mean the lowest possible ALM utilization. A designthat is reported to be close to 100% may still have space for extra logic. The Fitteruses ALUTs in different ALMs, even when the logic can be placed within one ALM,so that it can achieve the best timing and routability results. Logic might bespread throughout the device when achieving these results. As the device fills up,the Fitter automatically searches for logic that can be placed together in one ALM.

1.8.1.3. Review all Quartus Prime messages, especially warning or errormessages

Each stage of the compilation flow generates messages, including informational notes,warnings, and critical warnings. Understand the significance of warning messages andmake changes to the design or settings if required.

In the Quartus Prime user interface, you can use the Message window tabs to look atonly certain types of messages. You can suppress the messages if you havedetermined that your action is not required.

Related Information

Managing Quartus Prime ProjectsFor more information about messages and message suppression

1.8.1.4. Consider using incremental compilation

Use the incremental compilation feature to preserve logic in unchanged parts of yourdesign, preserve timing performance, and reach timing closure more efficiently. Youcan speed up design iteration time by an average of 60% when making changes to thedesign with the incremental compilation feature.

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1.8.1.5. Ensure parallel compilation is enabled

The Quartus Prime software can run some algorithms in parallel to take advantage ofmultiple processors and reduce compilation time when more than one processor isavailable to compile the design. Set the Parallel compilation option on theCompilation Process Settings page of the Settings dialog box, or change thedefault setting in the Options dialog box in the Processing page from the Toolsmenu.

1.8.1.6. Use the Compilation Time Advisor

The Compilation Time Advisor provides guidance in making settings that reduce yourdesign compilation time. On the Tools menu, point to Advisors and click CompilationTime Advisor. Using some of these techniques to reduce compilation time can reducethe overall quality of results.

Related Information

Area and Timing Optimization

1.8.2. Timing Optimization and Analysis

Use the guidelines in the following checklist for analyzing your design timing andoptimizing your timing performance.

1.8.2.1. Ensure timing constraints are complete and accurate

In an FPGA design flow, accurate timing constraints allow timing-driven synthesissoftware and place-and-route software to obtain optimal results. Timing constraintsare critical to ensure designs meet their timing requirements, which represent actualdesign requirements that must be met for the device to operate correctly.

The Quartus Prime software optimizes and analyzes your design using different timingmodels for each device speed grade, so you must perform timing analysis for thecorrect speed grade. The final programmed device might not operate as expected ifthe timing paths are not fully constrained, analyzed, and verified to meetrequirements.

Related Information

Timing Analysis Overview

1.8.2.2. Review the TimeQuest Timing Analyzer reports after compilation

The Quartus Prime software includes the Quartus Prime TimeQuest Timing Analyzer, apowerful ASIC-style timing analysis tool that validates the timing performance of alllogic in your design. It supports the industry standard Synopsys Design Constraints(SDC) format timing constraints, and has an easy-to-use GUI with interactive timingreports. It is ideal for constraining high-speed source-synchronous interfaces andclock multiplexing design structures.

The software also supports static timing analysis in the industry-standard SynopsysPrimetime software. To generate the required timing netlist, specify the tool in theNew Project Wizard or the EDA Tools Settings page of the Settings dialog box.

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1.8.2.3. Ensure that the I/O timings are not violated when data is provided to theFPGA

A comprehensive static timing analysis includes analysis of register to register, I/O,and asynchronous reset paths. It is important to specify the frequencies andrelationships for all clocks in your design.

Use input and output delay constraints to specify external device or board timingparameters. Specify accurate timing requirements for external interfacing componentsto reflect the exact system intent.

The TimeQuest Timing Analyzer performs static timing analysis on the entire system,using data required times, data arrival times, and clock arrival times to verify circuitperformance and detect possible timing violations. It determines the timingrelationships that must be met for the design to correctly function. You can use thereport_datasheet command to generate a datasheet report that summarizes theI/O timing characteristics of the entire design.

1.8.2.4. Perform Early Timing Estimation before running a full compilation

If the timing analysis reports that your design requirements were not met, you mustmake changes to your design or settings and recompile the design to achieve timingclosure. If your compilation results in no-fit messages, you must make changes to getsuccessful placement and routing.

You can use the Early Timing Estimation feature in the Quartus Prime software toestimate your design’s timing results before the software performs full placement androuting. On the Processing menu, point to Start and click Start Early TimingEstimate to generate initial compilation results after you have run analysis andsynthesis.

1.8.2.5. Consider the following recommendations for timing optimization andanalysis assignment:

• Turn on Optimize multi-corner timing on the Fitter Settings page in theSettings dialog box.

• Use create_clock and create_generated_clock to specify the frequenciesand relationships for all clocks in your design.

• Use set_input_delay and set_output_delay to specify the external deviceor board timing parameters

• Use derive_pll_clocks to create generated clocks for all PLL outputs,according to the settings in the PLL IP cores. Specify multicycle relationships forLVDS transmitters or receiver deserialization factors.

• Use derive_clock_uncertainty to automatically apply inter-clock, intra-clock,and I/O interface uncertainties.

• Use check_timing to generate a report on any problem with the design orapplied constraints, including missing constraints

• Use the Quartus Prime optimization features to achieve timing closure or improvethe resource utilization.

• Use the Timing and Area Optimization Advisors to suggest optimization settings.

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Related Information

The Quartus Prime TimeQuest Timing AnalyzerFor more guidelines about timing constraints

1.8.2.6. Perform functional simulation at the beginning of your design flow

Perform the simulation to check the design functionality or logical behavior of eachdesign block. You do not have to fully compile your design; you can generate afunctional simulation netlist that does not contain timing information.

1.8.2.7. Perform timing simulation to ensure your design works in targeteddevice

Timing simulation uses the timing netlist generated by the TimeQuest Timing Analyzer,which includes the delay of different device blocks and placement and routinginformation. You can perform timing simulation for the top-level design at the end ofyour design flow to ensure that your design works in the targeted device.

1.8.2.8. Specify your simulation tool and use correct supported version

• Intel provides the ModelSim - Intel FPGA Edition simulator Starter Edition andoffers the higher-performance ModelSim - Intel FPGA Edition that enable you totake advantage of advanced testbench capabilities and other features.

• In addition, the Quartus Prime EDA Netlist Writer can generate timing netlist filesto support other third-party simulation tools such as Synopsys VCS, Cadence NC-Sim, and Aldec Active-HDL.

• If you use a third-party simulation tool, use the software version that is supportedwith your Quartus Prime software version.

• Specify your simulation tool in the EDA Tools Settings page of the Settingsdialog box to generate the appropriate output simulation netlist. The software canalso generate scripts to help you setup libraries in your tool with NativeLinkintegration.

• Use only the model libraries provided with your Quartus Prime software version.Libraries may change between versions and this can cause a mismatch with yoursimulation netlist.

• To create a testbench in the Quartus Prime software, on the Processing menu,point to Start and click Start Testbench Template Writer.

Related Information

• Quartus Prime Software Release NotesFor information about the officially supported version of each simulation tool ina Quartus Prime software version

• Simulating Intel FPGA Designs

• Mentor Graphics ModelSim and QuestaSim Support

• Synopsys VCS and VCS MX Support

• Cadence Incisive Enterprise Simulator Support

• Aldec Active-HDL and Rivera-PRO Support

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1.8.3. Formal Verification

Use the following guidelines if your design requires formal verification.

1.8.3.1. Determine if you require formal verification for your design

If formal verification is required for your design, it is easier to plan for limitations andrestrictions in the beginning than to make changes later in the design flow.

1.8.3.2. Check for support and design limitations for formal verification

The Quartus Prime software supports some formal verification flows. Using a formalverification flow can impact performance results because it requires that certain logicoptimizations be turned off, such as register retiming, and forces hierarchy blocks tobe preserved, which can restrict optimization.

Related Information

Cadence Encounter Conformal SupportFor more information

1.8.3.3. Specify your formal verification tool and use correct supported version

Specify your formal verification tool in the EDA Tools Settings page of the Settingsdialog box to generate the appropriate output netlist.

Related Information

Quartus Prime Software Release NotesFor information about the officially supported version of each simulation tool in aQuartus Prime software version

1.8.4. Power Analysis and Optimization

After compiling your design, analyze the power consumption and heat dissipation withthe Quartus Prime PowerPlay Power Analyzer to calculate the dynamic, static, and I/Othermal power consumption and ensure the design has not violated power supply andthermal budgets.

Power optimization in the Quartus Prime software depends on accurate power analysisresults. Use the following guidelines to ensure the software optimizes the powerutilization correctly for the design’s operating behavior and conditions.

1.8.4.1. Provide accurate typical signal activities to get accurate power analysisresult

You need to provide accurate typical signal activities to PowerPlay Power Analyzer:

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• Compile a design to derive the information about design resources, placement androuting, and I/O standards.

• Derive signal activity data (toggle rates and static probabilities) from simulationresults or a user-defined default toggle rate and vectorless estimation. The signalactivities used for analysis must be representative of the actual operatingbehavior.

For the most accurate power estimation, use gate-level simulation results with aValue Change Dump File (.vcd) output file from a third-party simulation tool. Thesimulation activity should include typical input vectors over a realistic time periodand not the corner cases often used during functional verification. Use therecommended simulator settings, such as glitch filtering, to ensure good results.

1.8.4.2. Specify the correct operating conditions for power analysis

Specify the operating conditions, including the core voltage, device powercharacteristics, ambient and junction temperature, cooling solution, and the boardthermal model.

In the Quartus Prime software, select the appropriate settings on the OperatingSettings and Conditions page in the Settings dialog box.

1.8.4.3. Analyze power consumption and heat dissipation in the PowerPlayPower Analyzer

In the Quartus Prime software, on the Processing menu, click PowerPlay PowerAnalyzer Tool. The tool also provides a summary of the signal activities used foranalysis and a confidence metric that reflects the overall quality of the data sourcesfor signal activities.

The PowerPlay Power Analyzer report is a power estimate and is not a powerspecification. Always refer to the device datasheet for the power specification.

Related Information

PowerPlay Power AnalysisFor more information about power analysis and recommendations for simulationsettings for creating signal activity information

1.8.4.4. Review recommended design techniques and Quartus Prime options tooptimize power consumption

The Power Optimization Advisor provides specific power optimization advice andrecommendations based on the current design project settings and assignments.

Related Information

Power OptimizationFor information about design techniques to optimize power consumption

1.8.4.5. Consider using a faster speed grade device

If your design includes many critical timing paths that require the high-performancemode, you might be able to reduce power consumption by using a faster speed gradedevice if available. With a faster device, the software might be able to set more devicetiles to use the low-power mode.

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1.8.4.6. Optimize the clock power management

Clocks represent a significant portion of dynamic power consumption, because of theirhigh switching activity and long paths. The Quartus Prime software automaticallyoptimizes clock routing power by enabling only the portions of a clock network thatare required to feed downstream registers.

You can also use clock control blocks to dynamically enable or disable the clocknetwork. When a clock network is powered down, all the logic fed by that clocknetwork does not toggle, thereby reducing the overall power consumption of thedevice.

To reduce LAB-wide clock power consumption without disabling the entire clock tree,use the LAB-wide clock enable signal to gate the LAB wide clock. The Quartus Primesoftware automatically promotes register-level clock enable signals to the LAB level.

Related Information

MAX 10 Clocking and PLL User GuideFor more information about using clock control blocks

1.8.4.7. Reduce the number of memory clocking events

Reduce the number of memory clocking events to reduce memory powerconsumption. You can use clock gating or the clock enable signals in the memoryports.

1.8.4.8. Consider I/O power guidelines

• The dynamic power consumed in the I/O buffer is proportional to the total loadcapacitance—lower capacitance reduces power consumption.

• Dynamic power is proportional to the square of the voltage. Use lower voltage I/Ostandards to reduce dynamic power. Non-terminated I/O standards such as LVTTLand LVCMOS have a rail-to-rail output swing equal to the VCCIO supply voltageand consume little static power.

• Dynamic power is proportional to the output transition frequency. Use resistively-terminated I/O standards such as SSTL for high-frequency applications. Theoutput load voltage swings by an amount smaller than the VCCIO around a biaspoint. Because of this, the dynamic power is lower than for non-terminated I/Ounder similar conditions.

• Resistively-terminated I/O standards dissipate significant static power becausecurrent is constantly driven into the termination network. Use the lowest drivestrength that meets your speed and waveform requirements to minimize staticpower when using resistively terminated I/O standards.

• The power used by external devices is not included in the PowerPlay PowerAnalyzer calculations. Ensure that you include the external devices powerseparately in your system power calculations.

1.8.4.9. Reduce design glitches through pipelining and retiming

A design that has many glitches consumes more power because of faster switchingactivity. Pipelining by inserting flip flops into long combinational paths can reducedesign glitches.

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Page 43: Intel® MAX® 10 FPGA Design Guidelines · 2020-01-20 · 1. Intel® MAX® 10 FPGA Design Guidelines 1.1. Intel® MAX® 10 FPGA Design Guidelines This application note provides a

However, if there are not many glitches in your design, pipelining may increase powerconsumption due to the addition of unnecessary registers.

1.8.4.10. Review the information on power-driven compilation and PowerOptimization Advisor

The Quartus Prime software offers power-driven compilation to fully optimize devicepower consumption. Power-driven compilation focuses on reducing your design’s totalpower consumption using power-driven synthesis and power-driven place-and-route.

Related Information

Power Optimization

1.8.4.11. Reduce power consumption with architectural optimization

Use specific device architecture features to reduce power consumption.

For example, use the dedicated DSP block available in the MAX 10 device in place ofLEs to perform arithmetic-related functions; build large shift registers from RAM-basedFIFO buffers instead of building the shift registers from the LE registers.

1.9. Document Revision History

Table 1. Document Revision History

Date Version Changes

May 2017 2017.05.03 • Rebranded as Intel.

December 2014 2014.12.15 • Changed the following terms:Dual image to dual configuration imageDual image configuration to dual configuration

• Changed MAX 10 EMIF IP core to UNIPHY IP core.

September 2014 2014.09.22 Initial release.

1. Intel® MAX® 10 FPGA Design Guidelines

M10-GUIDELINES | 2017.05.03

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