interconnects and reliability · 2019-12-19 ·...

Interconnects and Reliability

Sandip TiwariSandip [email protected]

1Tiwari_12_2009_iWSG_Interconnects&Reliability.pptx

SRAM: IBM J. R&D (1995)Logic Interconnects Insulators/Reliability

Prologue

Global

Middle

Local


Interconnects

obab

ility

Pro

LocalFringing & Coupling Capacitances

0 5

Capacitances

Technology scaling occurs with increasing average interconnect length and routing density and increased interconnect aspect ratio

Wire Length (unit of die-size)0.5

Global

Interconnects grow linearly with cells in ordered arrays (memories, e.g.)

Interconnects grow as the square of the elements in random logic

Local (intra-block) wires scale with block size, but global (inter-block) i d t

3Tiwari_12_2009_iWSG_Technology.pptx

wires do not.

Below the Interconnect


D. Antoniadis IBM J R&D (2006)

Strip Line Capacitance


Reducing line width will not reduce C0 proportionally for small w/h

Clokc Skewing

probe points on chip

Transmission line effects Clock signals in 400 MHz IBM Microprocessor(measured using e beam prober)


cause overshooting and nonmonotonic behavior

(measured using e-beam prober)

P. Restle (1998)

Time Scales of Pulse Propagation

Scale of distances and delays (c/n):

Board 20 cm 0.67 ns

Chip 1 cm 33 ps

Logic Units 0.1 cm 3.3 psg p

Short Interconnects: Capacitive (lumped) Cross talk & NoiseShort Interconnects: Capacitive (lumped), Cross-talk & Noise

Long Interconnects: Transmission lines, cross-talk & noise, ground loops


Interconnects that need to maintain precise timing and match in jitter: Clocks

Short Transmission Lines

Open Short

if


e.g., if

Transmission Line Implication

Board 20 cm 0.67 ns

Chip 1 cm 33 ps

Logic Units 0 1 cm 3 3 ps

Scale of distances and delays (c/n):

Transmission line effects should be considered when the rise or fall time of the input signal (t tf) is quite

Logic Units 0.1 cm 3.3 psy ( )

the rise or fall time of the input signal (tr, tf) is quite smaller than the time-of-flight of the transmission line (tflight) tr (tf) << 2.5 tflight

Transmission line effects increasingly important when the total resistance of the wire is limited: R < 5 Z0

The transmission line treatable as lossless hen theThe transmission line treatable as lossless when the total resistance is substantially smaller than the characteristic impedance: R < Z0/2


Matching

Z 0

Z 0 Z L

Series Source Termination

Z S

Z 0 Z 0

Parallel Destination Termination


Parallel Destination Termination

Lossless Transmission Line

Pulse impedance:

F l d fl ti ffi i tFor a load, , reflection coefficient

Open:

Short:Short:


On Chip Transmission Line

O hi llOn chip, usually,


Capacitively Coupled Noise

Active

Floating


Loosely Coupled Transmission Lines

From Odd and Even mode analysis:

Inductive Coupling , Short line:


Inductively coupled component is negligible for most on-chip conditions

Crossing Lines on Chip

Non Transverse EM (non TEM)Slow wave structureStrong coupling between parallel lines

Source of


ground loop problems

Lossy Lines

For low loss:

V lt d bli t liVoltage doubling at line end compensates for loss, but may cause problems at intermediate pointsintermediate points

For high loss:

1st 2nd

ns μm2 Ω ps

0.2 5x1.5 60 2.4 90

For high loss:

16

0.2 1x0.5 900 540 1350

Tiwari_12_2009_iWSG_Interconnects&Reliability.pptx

Skin Effect

Skin Depth

On chip TEM line

Assume delay is limited by wire resistanceAssume delay is limited by wire resistance

Then, Narrow line

Wide lineWide line

Skin effect is unimportant for usual case of on-chip propagation.


But, if size becomes too small, scattering effects from surfaces would contribute

Using Bypass for Resistive Lines

DriverPolysilicon word lineWL

Metal word line

Metal bypass

Driving a word line from both sides

Polysilicon word line

Metal bypass

WL K cells Polysilicon word line

Using a metal bypass


Long Lines: Reducing RC Delay

Repeater


L di/dt

VDD

Impact of inductance on supply voltages:V’DD

L i(t)

Change in current induces a change in voltage

C

VoutVin

Longer supply lines have larger L

CL

GND’

LL

Critical to design power lines for low inductance


Segmenting Matched Line Drivers

VDD

In

Z 0

Z

c1 c2

s0 s1 s2 sn

cn

Z L

GND


Output Driver TerminationsVDD

ClampingL = 2.5 nH

4

Vin V s V d

VDD

Diodes

CL= 5 pF CL

L = 2.5 nH Z 0 = 50 Ω

275

120

Vs

Vd

Vin

1

2

3L= 2.5 nH

1 2 3 4

Initial design

5 6 7 80

1

0

Vs

Vd

Vin

2

3

4

Initial design

1 2 3 4 5 6 7 80

1

0

1


1 2 3 4

time (sec)

Revised design with matched driver impedance

5 6 7 80

Parallel Terminations: Using Resistance from Transistors

PMOS with 1V biasVdd PMOS with-1V bias

NMOS only

1 71.81.9

2Mr

dd

V

PMOS only

1.41.51.61.7

Out

0 5 1

NMOS-PMOS

1 5 2 2 50

1.11

1.21.3

Mr

Vdd

V

Mrp Mrn

Vdd

0.5 1 1.5VR (Volt)

2 2.50

Out

Vbb

Out


ElectromigrationElectromigration


A Cross-Section

Insulators

Interconnects

Transistors


Maxwell’s Equations

Original Scaled Scaling Factors



Low κ Oxide

D it ( / 3) 1 03 2 2Density (g/cm3) 1.03 2.2

Dielectric constant (κ) ~1.9-2.5 4.1

Modulus (GPa) ~3-9 55-70

Hardness (GPa) ~0.3-0.8 3.5

cTE (ppm/K) ~10-17 0.6

Porosity ~35-65% nonePorosity 35 65% none

Average Pore <2.0-10 nm none

Thermal Conductivity(W/m K)

0.26 1.4(W/m.K)


Damascene

(111)


1.2 μm(100)

(110)


Metal Resistivity


At <200 nm, Cu Resistance starts to riseGrain boundaries and interface scattering – with Ta based barriers

Voids and accumulation caused by flux divergence, accelerated by stress y g , yand temperature


Interconnects

Passivated Cu:350 nm, width 600 nm

Stress temperature: 230 C

Current densities increased up to 107

A/cm2 during ~17 hrs


Sneider, Fut Fab Vol19

Technology & Reliability IssuesElectromigration

e-Hillocks

Nucleation on defects

Metal

Nucleation on defects

(111)Voids

(100)

300 nm 300 nm

Before After


Before After

Technology & Reliability Issues Low kDiffusion Barrier!Voids! Diffusion Barrier!Voids!

e- Electromigration

Metal

Porosity!Dielectric cracking!(111)Voids

300 nm 300 nm


ElectromigrationD ift f t i th di ti f l t fl d b fi ld l t i dDrift of atoms in the direction of electron flow caused by fields: electron wind

Aluminum: mitigated by alloying with Cu and conductive barrier/liner layers

N t E ti

At d ift

Nernst Equation:

Atom drift velocity

Electromigration

Effective charge

Field

Diffusivity

resistivity

Intrinsic atom

bilit

driving forcee d es s y

Current density


mobility

Reliability of InsulatorsReliability of Insulators

In transistors:

thick and thin oxides and consequences of high κwith particular emphasis on NBTI

Implications for circuits

In Flash Memories

implications of relatively thick oxides


Gate Dielectric: Nitrided Oxide with polySi


Leaky, difficult to control, B penetration, SILC, soft breakdowns, NBTI, PBTI, …

Metal Gates and High κ


Plasma Damage

Linder, P2ID(1948)

Thin Oxides (scaled devices) reduced damageThick Oxides (IO devices) damage persistsN ff t t ll di i di l t i diff t BEOL di l t i


New effects at small dimensions: new dielectrics, different BEOL dielectrics and processing techniques (UV cure?) and heavy dose implants

Old: Charge to Breakdown

Defect generation to Breakdown

41Tiwari_12_2009_iWSG_Interconnects&Reliability.pptxDiMaria, APL(1997)

Bias Dependence of Breakdown Growth

From 0 to 100 μAbreakdown leakage

i 300 f


in 300 years of continuous operation

J. Stathis (2008)

Charge to BreakdownPercolation


Stathis, IRPS(2001) and JAP (1999)

SILCStress Induced Leakage CurrentStress Induced Leakage Current


Oxides and Transport in InsulatorsO idOxides:The properties of SiO2 change to bulk like over a length scale of about 2 monolayers.Direct tunneling is certainly quite significant at sizes below about 1.5 nm.

What does electron transport do when biases are applied in oxides?

E l i th i l t b ki b dEnergy losses in the insulator – breaking bonds and trapping carriers (so charge in oxides, and sites in oxides through which electron transport can take place (e.g. by percolation)p ( g y p )

Energy losses at interfaces – breaking bonds, releasing ionized species that can then move in applied fieldsapplied fields

Magnitudes of various effects depend on how thick oxides are, bias conditions and multiple phenomena may be important simultaneously


and multiple phenomena may be important simultaneously.

Effects may be hard, i.e. “abrupt” or soft, i.e. a gentle degradation

Dielectric Reliability: Nitridation Hardening

Bulk properties lost below 2 monolayers

Below 32 nm, SiON required for appropriate EOT (electrical thickness) is very high in N

P l h i i l th l f H0 d H+ f l SiON


E. Wu, IEDM(2000)P. Nicollian IRPS (2003) & IEDM(2005)

Power law mechanisms may involve the release of H0 and H+ from poly-SiONinterface

Outline

Ultra-thin oxide breakdown“Progressive” breakdown

Ci it i li tiCircuit implications

Negative Bias Temperature Instability (NBTI)Role of Nitrogen

New materials

Comments for thick Oxides (NVRAMs)


Progressive Breakdown

Hard Breakdown doesn’t happen suddenly as a catastrophic processcatastrophic process

Happens gradually over a measurable time scale

D d ti t iDegradation rate is slower for lower stress voltages

Log time scale


Hosoi, IEDM(2002)Log time scale

What does it Mean?

Thick Oxide High Voltage Stress Ultra-Thin Oxide Low Voltage Stress


T. Hosoi, SSDM(2002)

Interface State Distribution

Mid-gap defects with gated diode peak Conduction band edge defects with flat-b d t l k (LV SILC)


band gate leakage (LV-SILC)

Stathis, INFOS(2005)

Interpretation

All breakdown is progressive

Continuum of rates ofContinuum of rates of post-BD current growth

Progressive BD can be “stopped” atstopped at intermediate current level

Operational definitions are circuit dependent


Negative Bias

Positive bias shifts away from the SiO2/Si interface

Charge exchange: Hole trapping or electron detrapping increases the net positive


g g pp g pp g pcharge at the Si/SiO2 interface

NBTI: A Serious Reliability Issue

pMOS threshold shift (drain currentshift (drain current reduction)

Interface states and positive oxide charge

Serious concernSerious concern for low VDD new technologiestechnologies

Nitridationworsens NBTI


Channel Hot Carrier Issues with Scaling

Decreasing lifetimeLg shrinking while VDD scaling limitedIncreased use of well bias => additional stress


JW McPherson, IEDM(2005)

NBTI

Ox thickReddy, IRPS(2002)

Ox thick. scalingLower Thermal

budget

BEOLOx thick. scaling

SOCNitridation


Power dissipation

NBTI: Negative Bias Temperature Instability

Negative Bias Temperature Instability

pFET on-state(holes involved)

Thermal activation: ~0.2 eV

Miura & Matukura JJAP(1966)

Power law dependence of tn with n 0 15 0 25

Miura & Matukura, JJAP(1966)

Power law dependence of tn with n ~ 0.15-0.25

Source believed to be electrochemical reaction with a hydrogen related species in the oxide

R ti /diff i

56

Reaction/diffusion


NBTI: Dispersive TransportZafar, JAP(2005)

Hydrogen density calculated from kinetics (is statistical)Creation of interfacial and oxide traps

I t f i l d id t h h d d t l t tInterfacial and oxide traps have charged and neutral states

Charge state densities follow Fermi function

Correct treatment of the drift/diffusion of [H] including dispersive t f i h dinature of process in amorphous mediumDispersive transport arises when mobile species experiences a broad distribution of barrier heights leading to an exponentially broad distribution of hopping timesdistribution of hopping times

Causes stretched exponential

This reduces to power law form at short times


This reduces to power law form at short times, and accounts for saturation at long times

Process Influence

Nitridation of gate oxide enhances NBTI

Deuterium – some publications show improvement

Fluorinated gate oxide reduces NBTIImprovement diminishes with nitridation

Oxidation conditions and tooling

BEOL charging enhances NBTI effect

Composition of contact etch stop layer and stress films


Circuit ImplicationsCircuit Implications


SRAM

Increasing asymmetry from NBTI and PBTI

PBTI more sensitive to Tinv

SRAM cell itself more sensitive to NBTI


SRAM cell itself more sensitive to NBTI

Read affected more than WriteA. Bansal, Micro Rel (2009)

Implications of Progressive Breakdown

Many characteristics are not strongly perturbed by oxide breakdowne.g. transconductance (gm) and threshold voltage (VT)

Strongest implication is in an increase in off currentin gate-drain or gate-source leakage

Include power law equation from breakdown curves


Include power law equation from breakdown curves

Inverter Transfer Characteristics

Loads output of 1st inverter by breakdown in 2ndbreakdown in 2

Logic may tolerate high breakdown leakage (~10 μA)with reduced noise


leakage ( 10 μA)with reduced noise margin(is another source of variability)

SRAM Static Noise Margin

At breakdown current > 50 μA, SNM reduced by 50%50%

Worst case:n-source breakdown•Pulls down voltage at gopposite node•Loads a weaker pFET


Rodriguez, EDL(2002)

Circuit Failure Distribution

Follows from

Weibull distribution of oxide BD timese bu d s bu o o o de es

(β=1 for tox < 2 nm):

Assumed exponential distribution of post –BD times (Δt):


E. Wu, IEDM(2003)

Circuit Failure Distribution

Example:

For 100 ppm failure (F=10-4)

A 100x increase in lifetime


High κHigh κ


HfSiON: SiO2

Shanware, IEDM(2003)

2-3 orders of reduced leakage over SiO2Carrier mobility is ~20% below universal curve at high fieldsTh l t bilit t 1100 C


Thermal stability to 1100 C

High κ Breakdown

Breakdown strength decreases with κ


gField/voltage acceleration g increases with κ (useful in burn-in and stress testing)

NBTI in High κ

Similar to SiO2

Interface dominated

Power law time dependenceSaturationRelaxationDependence on temperature & field

69Tiwari_12_2009_iWSG_Interconnects&Reliability.pptxZafar, EDL(2005)

High κ Stability


Shanware, IEDM(2003) Some of the high κ dielectrics are quite unstable under stressLower breakdown strength will affect thickness scaling

HfO2/SiO2 Stack Stressing

Two time constants (others have observed three)

At the beginning: due to pre-existing traps(?)

Then, degradation due to stressing

A third one depending onA third one, depending on thicknesses, due to hard breakdown


E. Amat, Microelectron Rel (2007)

Recovery: Metal Gate with high κ

Recovery and recovery rate after stressing

Interface properties affect ΔVT, but little effect on recoveryStressing field, rather than stressing voltage, influences NBTI recovery in pMOSFET


M. Wang, Micro Eng (2009)

Metal GateMetal Gate


Metal GatesFUSI: fully silicided

Higher dielectric leakage and reduced breakdown strength with metal gates (FUSI)Higher dielectric leakage and reduced breakdown strength with metal gates (FUSI)Electric stressing show higher VT shifts in metal gates

Metal gates:Stability of interface under NBTI and PBTI


Stability of interface under NBTI and PBTIProcess impact of charging, breakdown, TDDBWorkfunction variability

Metal Gate Breakdown Transients

F t b kd t i t (iFast breakdown transients (i.e. hard breakdown) observed in metal gates FETs in the voltage range where polySig g p ygate show progressive breakdwon

Advantage of progressive breakdown lost for metal gatesgates


Palumbo, IRPS(2004)

Metal Gate with High κ

At <1 μA, progressive breakdown before catastrophic breakdownp

The increase in stress current just e c ease s ess cu e jusbefore hard breakdown is progressive breakdown since independent of device area and localized in the same position as finallocalized in the same position as final hard breakdown


S. Lombardo, ISAGST(2006)

Charge Trapping Dependence on Gate

Metal gates are better

Silicide is similar to polySi

polySi/high κinteractions appear to be prime suspect p pfor charge trapping instabilities in polySiand FUSI devicesand FUSI devices

PBTI has a stretched exponential

77

dependence similar to NBTI


Gusev, IEDM(2004)

Summary

For polySi gates: “Hard” breakdown is a slow (“progressive”) process :

Breakdown criterion is circuit dependentBreakdown criterion is circuit-dependent

Circuit failure will be later than initial oxide breakdown

For metal gates: Progressive breakdown is less apparent

VT stability is a concern for oxynitride and new dielectrics/gates


Back UpBack Up



Clock Span

Increasing fclk and speedReduced logic span


Reduced logic span

Higher electromagnetic coupling: capacitive coupling inductive bounce

Source: Saraswat

Transmission Line

Vin Voutr r r x r

l l l l

g c g c g c g c

The Wave Equation


RepeatersTaking the repeater loading into account

For a given technology and a given interconnect layer, there exists an optimal length of the wire segments between repeaters. The delay of these wire segments is independent of the routing layer:


Inductance in Supply Lines

1

1.5

2

2.5

ut(V

)

1

1.5

2

2.5

0 0.5 1 1.5 2

x 10-9

0

0.5

1Vou

0 0.5 1 1.5 2

x 10-9

0

0.5

1

0.02

0.04

i L(A

)

0.02

0.04

decoupled

Without inductorsWith inductors

0 0.5 1 1.5 2

x 10-9

0

1

0 0.5 1 1.5 2

x 10-9

0

1

0 0.5 1 1.5 2

0

0.5

VL

(V)

0 0.5 1 1.5 2

0

0.5


0 0.5 1 1.5 2

x 10-9time (nsec)

0 0.5 1 1.5 2

x 10-9time (nsec)

Input rise/fall time: 50 psec Input rise/fall time: 800 psec

Mitigating Inductive Effects

Separation of power pins for I/O pads and coreMultiple power and ground pins Careful positioning of the power and ground pins on the packagethe packageIncrease the rise and fall times of the off-chip signals to the maximum extent allowableS h d l t i t itiSchedule current-consuming transitionsImproved packagingAdd decoupling capacitanceAdd decoupling capacitance


SRAM cell Flip Failure Envelope

Minimum voltage of SRAM affected by

combination ofcombination of

NBTI (pFET VT shift)

A dAnd

Oxide progressive breakdown

86Tiwari_12_2009_iWSG_Interconnects&Reliability.pptxMueller, IRPS(2004)

Metal Gate High κ

Major issueMobility degradation

Th h ld lt t lThreshold voltage control

For high κ , electron trapping under positive bias (PBTI in nFET) is a new concern


interconnects and reliability · 2019-12-19 ·...

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