Interfacing and Memory

Martin Schoeberl

Technical University of DenmarkEmbedded Systems Engineering

April 23, 2020

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Overview

I Repeat FSMD (for the vending machine)I InterfacesI Memory (intern and extern)I Serial interface (RS 232)I 2 hours lab SRAM exercise

I Exercise description is in DTU InsideI sram exercise.pdfI SRAM data sheet: CYCC1041...

I The course evaluation is open for feedback

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The Online Exam

I We will use the “old” online systemI Show it at http://onlineeksamen.dtu.dk/I It will be two parts:

I Multiple choiceI Download and hand in a document (e.g., PDF generated

from Word)I You can play with the very short one todayI We will do a test exam next week, before the lab

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Using an FSM and a Datapath

I About the design of the vending machine (VM)I Some of you start coding the VM directly

I This may work for small designsI But does not scale

I Better use a systematic approachI Use a FSM that communicates with a datapath (FSMD)I We will quickly repeat FSMD

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Finite-State Machine (FSM)

I Has a register that contains the stateI Has a function to computer the next state

I Depending on current state and inputI Has an output depending on the stateI Use a Moore FSM for the VM

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Basic Finite-State Machine

I A state registerI Two combinational blocks

in

state

nextStateNext statelogic

Ouputlogic out

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State Diagram

bad event

green orange red/ring bell

bad event

clear

reset

clear

I States and transitions depending on input valuesI Example is a simple alarm FSMI Nice visualizationI Draw the state diagram for your VM during the designI Include a state diagram in the report

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The Input and Output of the Alarm FSM

I Two inputs and one output

val io = IO(new Bundle{

val badEvent = Input(Bool())

val clear = Input(Bool())

val ringBell = Output(Bool())

})

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Encoding the State

I We can optimize state encodingI Two common encodings are: binary and one-hotI We leave it to the synthesize toolI Use symbolic names with an EnumI Note the number of states in the Enum constructI We use a Scala list with the :: operator

val green :: orange :: red :: Nil = Enum(3)

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Start the FSM

I We have a starting state on reset

val stateReg = RegInit(green)

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The Next State Logicswitch (stateReg) {

is (green) {

when(io.badEvent) {

stateReg := orange

}

}

is (orange) {

when(io.badEvent) {

stateReg := red

} .elsewhen(io.clear) {

stateReg := green

}

}

is (red) {

when (io.clear) {

stateReg := green

}

}

}

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The Output Logic

io.ringBell := stateReg === red

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Summary on the Alarm Example

I Three elements:1. State register2. Next state logic3. Output logic

I This was a so-called Moore FSMI There is also an FSM type called Mealy machine

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FSM with Datapath

I A type of computing machineI Consists of a finite-state machine (FSM) and a datapathI The FSM is the master (the controller) of the datapathI The datapath has computing elements

I E.g., adder, incrementer, constants, multiplexers, ...I The datapath has storage elements (registers)

I E.g., sum of money payed, count of something, ...I You VM design shall be a FSMD

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FSM-Datapath Interaction

I The FSM controls the datapathI For example, add 2 to the sum

I By controlling multiplexersI For example, select how much to addI Not adding means selecting 0 to add

I Which value goes whereI The FSM logic also depends on datapath output

I Is there enough money payed to release a can of soda?I FSM and datapath interact

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Popcount Example

I An FSMD that computes the popcountI Also called the Hamming weightI Compute the number of ‘1’s in a wordI Input is the data wordI Output is the count

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Popcount Block Diagram

dinValid popCntValid

FSM

din popCnt

popCntReadydinReady

Datapath

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The FSM

Count

Idle

Done

Valid

Finished

Result read

I A Very Simple FSMI Two transitions depend on input/output handshakeI One transition on the datapath output

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The Datapath

+

shfdin

00 cnt

count

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Let’s Explore the Code

I In PopCount.scala

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Usage of an FSMD

I Of course for your VMI The VM is a simple processorI But not Turing completeI Can only process coins of 2 and 5

I An FSMD can be used to build a processorI Fine for simple processorsI E.g., LipsiI Pipelined processor topic of

I Computer Architecture Engineering (02155)

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Use a FSMD for the VM

I This is the main part your vending machineI Can be design and tested just with Chisel testers (no

FPGA board needed)I See the given tester

I Sets the price to 7I Adds two coins (2 and 5)I Presses the buy button

I Extend the test along the developmentI Remember test driven development?I Maybe write the test before the implementationI Maybe test developer and FSMD developer are not always

the same person

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Code Snippets for the VM

val idle :: add2 ... :: Nil = Enum(?)

val stateReg = RegInit(idle)

...

switch (stateReg) {

is (idle){

when(coin2) {

stateReg := ...

}

when(...) {

...

switch(stateReg) {

is (add2) { ... } // drive the datapath for

adding a coin of kr. 2

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Memory

I Registers are storage elements == memoryI Just use a Reg of a VecI This is 1 KiB of memory

val memoryReg = Reg(Vec(1024, UInt(8.W)))

// writing into memory

memoryReg(wrAddr) := wrData

// reading from the memory

val rdData = memoryReg(rdAddr)

I Simple, right?I But is this a good solution?

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A Flip-Flop

I Remember the circuit of a register (flip-flop)?I Two latches: master and slaveI One (enable) latch can be built with 4 NAND gatesI a NAND gate needs 6 transistors, an inverter 2 transistorsI A flip-flop needs 20 transistors (for a single bit)I Can we do better?

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A Memory Cell

I A single bit can be stored in 6 transistorsI That is how larger memories are builtI FPGAs have this type of on-chip memoriesI Usually many of them in units of 2 KiB or 4 KiBI We need some Chisel code to represent itI More memory needs an extra chipI Then we need to interface this memory from the FPGA

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SRAM Memory

I RAM stands for random access memoryI SRAM stands for static RAMI There is also something called DRAM for dynamic RAM

I Uses a capacitor and a transistorI DRAM is smaller than SRAMI But needs refreshesI Different technology than technology for logic

I All on-chip memory is SRAM (today)

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Memory Interface

I InterfaceI Address input (e.g., 10 bits for 1 KiB)I Write signal (e.g., we)I Data inputI Data output

I May share pins for the data input and output (tri-state)I May have read and write address

I A so-called dual ported memoryI Can do a read and a write in the same clock cycle

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On-Chip Memory

I SRAM by itself is asynchronousI No clock, just the correct timingI Apply the address and after some time the data is validI But one can add input registers, which makes it a

synchronous SRAMI Current FPGAs have only synchronous memoriesI FPGAs usually have dual-ported memoriesI This means the result of a read is available on clock cycle

after the address is givenI This is different from the use of flip-flops (Reg(Vec(..)))

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Synchronous Memory

rdAddr

wrAddr

wrData

rdData

wrEna

Memory

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Use of a Chisel SyncReadMem

class Memory() extends Module {

val io = IO(new Bundle {

val rdAddr = Input(UInt(10.W))

val rdData = Output(UInt(8.W))

val wrEna = Input(Bool())

val wrData = Input(UInt(8.W))

val wrAddr = Input(UInt(10.W))

})

val mem = SyncReadMem(1024, UInt(8.W))

io.rdData := mem.read(io.rdAddr)

when(io.wrEna) {

mem.write(io.wrAddr, io.wrData)

}

}

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Read-During-Write

I What happens when one writes to and reads from thesame address?

I Which value is returned?I Three possibilities:

1. The newly written value2. The old value3. Undefined (mix of old and new)

I Depends on technology, FPGA family, ...I We want to have a defined read-during-writeI We add hardware to forward the written value

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Condition for Forwarding

I If read and write addresses are equalI If write enable is trueI Multiplex the output to take the new write value instead of

the (old) read valueI Delay that forwarded write value to have the same timing

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Memory with Forwarding

rdAddr

wrAddr

wrData

rdData

wrEna

=AND

dout

Memory

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Forwarding in Chisel

val mem = SyncReadMem(1024, UInt(8.W))

val wrDataReg = RegNext(io.wrData)

val doForwardReg = RegNext(io.wrAddr ===

io.rdAddr && io.wrEna)

val memData = mem.read(io.rdAddr)

when(io.wrEna) {

mem.write(io.wrAddr, io.wrData)

}

io.rdData := Mux(doForwardReg , wrDataReg ,

memData)

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External Memory

I On-chip memory is limitedI We can add an external memory chip

I Is cheaper than FPGA on-chip memoryI Sadly the Basys3 board has no external memoryI Simple memory is an asynchronous SRAM

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External SRAM

I We buy a CY7C1041CV33I Let us look into the data sheet

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Interfacing the SRAM

I FPGA output drives address, control, and data(sometimes)

I FPGA reads dataI The read signal is asynchronous to the FPGA clockI Do we need an input synchronizer?

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Synchronous Interface

I Logic is synchroousI Memory is asynchronous

I How to interface?I Output signals

I Generate timing with synchronous circuitI Small FSM

I Asynchronous input signaleI Usually 2 register for input synchronizationI Really needed for the SRAM interface?I We would loose 2 clock cycles

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SRAM Read

I Asynchronous timing definition (data sheet)I But, we know the timing and we trigger the SRAM address

from our synchronous designI No need to use synchronization registersI Just get the timing correctI Dra the example

I Address - SRAM - dataI Relative to the FPGA clock

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Read Timing Continued

I Add all time delaysI Within FPGAI Pad to pinI PSB tracesI SRAM read timingI PCB traces backI Pin to padI Into FPGA register

I Setup and hold time for FPGA registerI Is your today’s lab exercise

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Connecting to the World

I Logic in the FPGAI Described in ChiselI Abstracting away electronic properties

I Interface to the worldI Simple switches and LEDsI Did we think about timing?

I FPGA is one component of the systemI Need interconnect to

I Write outputsI Read inputsI Connect to other chips

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Bus Interface

I Memory interface can be generalizedI We use a so-called bus to connect several devicesI Usually a microprocessor connected to devices (memory,

IO)I The microprocessor is the masterI A bus is an interface definition

I Logic and timingI Electrical interface

I Parallel or serial dataI Asynchronous or synchronous

I But interface clock is usually not the logic clock

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Bus Properties

I Address bus and data busI Control lines (read and write)I Several devices connected

I Multiple outputsI Use tri-state to avoid multiple driver

I Single or multiple masterI Arbitration for multiple master

I Sketch a small microprocessor system

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Serial I/O Interface

I Use only one wire for data transferI Bits are serializedI That is where you need your shift register

I Shared wire or dedicated wires for transmit and receiveI Self timed

I Serial UART (RS232)I EthernetI USB

I With a clock signalI SPI, I2C, ...

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RS 232

I Old, but still common interface standardI Was common in 90’ in PCsI Now substituted by USBI Still common in embedded systemsI You Basys3 board has a RS232 interface

I Standard definesI Electrical characteristicsI ’1’ is negative voltage (-15 to -3 V)I ’0’ is positive voltage (+3 to +15 V)I Converted by a RS232 driver to normal logic voltage levels

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Serial Transmission

I Transmission consists ofI Start bitI 8 data bitsI Stop bit(s)

I Common baud rate 115200 bits/s

b0 b1 b2 b3 b4 b5 b6 b7

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RS 232 Interface

I Generate bit clock with with counterI Like clock tick generation for display multiplexer

I Output (transmit)I Use shift register for parallel to serial conversionI Small FSM to generate start bit, data bits, and stop bits

I Input (receive)I Detect start with the falling edge of the start bitI Position into middle of start bitI Sample individual bitsI Serial to parallel conversion with a shift register

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Chisel Code for RS 232

I More explanation can be found in section 11.2I The code is in the Chisel bookI uart.scalaI Also see example usage in chisel-examples repo

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RS 232 on the Basys3

I Basis3 has an FTDI chip for the USB interfaceI USB interface for FPAG programmingI But also to provide a RS 232 to the FPGAI You can talk with the LaptopI Your VM could write out some textI Use the Chisel code I showed youI Open a terminal to watch (show it)

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Today’s Lab

I Paper & pencil exercises on SRAM interfacingI On paper or in a plain text editorI As usual, show and discuss with a TAI Exercise description is in DTU Inside file sharingI sram exercise.pdfI SRAM data sheet: CYCC1041...

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Summary

I Use an FSMD for the vending machine and simpleprocessors

I We need to connect to the worldI FPGA (or any chip) is only part of a systemI Bus interface to external devices (e.g., memory)I Serial interface to connect systems

I E.g., your Basys3 board to the laptop

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