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Dr. Kimberly E. NewmanHybrid Embedded wk3Fall 2009Interrupt Systems Notes (overview of NIOS II, HAL, and PIO)Necessary StuffLecture Notes are now on the course websiteHomework #1 due date extended to Thursday.Zip and email the files to me (newmanke@colorado.edu) while we work out the kinks in the CULEARN system.Lab #3 Interrupts and intro to debugPolling vs. Interrupt Driven InterfacingExpanding the I/O SystemInterrupt system: Allow devices to get processors attentionProcessorMemory - I/O BusMainMemoryI/OControllerDiskDiskI/OControllerI/OControllerGraphicsNetworkinterrupts4This is a more in-depth picture of the I/O system of a typical computer.The I/O devices are shown here to be connected to the computer via I/O controllers that sit on the Memory I/O busses. We will talk about buses on Friday.For now, notice that I/O system is inherently more irregular than the Processor and the Memory system because all the different devices (disk, graphics) that can attach to it. So when one designs an I/O system, performance is still an important consideration.But besides raw performance, one also has to think about expandability and resilience in the face of failure.For example, one has to ask questions such as:(a)[Expandability]: is there any easy way to connect another disk to the system?(b) And if this I/O controller (network) fails, is it going to affect the rest of the network?

+2 = 7 min (X:47)

Push ButtonsInterrupt TermsHardware interrupt an exception caused by a signal from hardware (request for action)IRQ- Interrupt ReQuest ISR- Interrupt Service Routine Code executed on the main processor in service of the deviceInterrupt vector - commonly referred to term for memory location holding the address of the interrupt service routine (ISR)Interrupt mask used to block interruptsexceptionAny condition or signal that interrupts normal program execution.Software: divide by 0, illegal opcode, etc.

Difference between Interrupts and Software ExceptionsInterrupt is a hardware-based eventSoftware exceptions originate from the program currently running on processorHandled in a similar way to interrupts: each designed cause will change the program to an exception handler routine.

NIOS II InterruptMany devicesInterrupt controller is generated by SOPC builderControlled by IRQ number assignment32 interrupt request linesPriority encoded IRQ[0] is highest priority

NIOS II Interrupt Controller

NIOS II Interrupt Controller 2

Exception Handling in Nios IIWhen an interrupt occurssaves the status registerdisables hardware interruptspreserves the program counter or effective address register on the stack transfers control to the handlerHardware Abstraction Layer (HAL)Lightweight runtime environmentprovides simple device driver interfaceallows access to devices with common C library functions

HAL ServicesIntegration with C standard libraryDevice driversHAL APISystem initializationDevice initializationInterfacing with HALApplication developersusing HAL API or C standard librarydo not consider the underlying hardwareDevice driver developersmaking drivers for low-level hardwareinterface newly written drivers with HALGeneric Devices in HALCharacter-mode devicesTimer devicesFile subsystemsEthernet devicesDMA devicesFlash memory devices

Exception Handling in HALTop level exception handlercreates private stackstores register values onto the stackdetermines the type of exception and invoke the right SW or HW handlerSoftware exception handlerHardware interrupt handlerISRs for peripheralsNIOS II Interrupt or Exception Control Diagram1. Save the status registers2. Disable interrupts3. Save the EA (effective address register)where the program was executing before interruptTransfer control to the interrupt vector

EA is also known as PC (Program Counter)

Exception Handling in HALCheck estatus to see if hardware interrupt is enabledif yes, check to see if the interrupt is hardware by checking ipendingif yes, corresponding ISR is calledif no, call the software exception handlerHardware interrupts have higher priority than software exceptionsException Handling in HALUpon returning from exceptions, the top-level handlerrestores the stack pointerrestores the registers from the stackexits by issuing an eret instructionException Handling in HALHW Handlers32 hardware interrupts (0 to 31, with 0 as highest priority)priority is HAL specific and not NIOS II

Exception Handling in HALSW handlersused for unimplemented instructionse.g. running multiplication on NIOS II with no multiplierstrapsInterrupt Diagram StepsAdvantage:User program progress is only halted during actual transferDisadvantage, special hardware is needed to:Cause an interrupt (I/O device)Detect an interrupt (processor)Save the proper states to resume after the interrupt (processor)addsubandornopreadstore...rtimemoryuserprogram(1) I/Ointerrupt(2) save EA(3) Get interruptservice addrand changeNIOS EA to thataddressinterruptserviceroutine(4)CPUIOCdeviceMemory:22That is, whenever an I/O device needs attention from the processor, it interrupts the processor from what it is currently doing.This is how an I/O interrupt looks in the overall scheme of things. The processor is minding its business when one of the I/O device wants its attention and causes an I/O interrupt.The processor then save the current PC, branch to the address where the interrupt service routine resides, and start executing the interrupt service routine.When it finishes executing the interrupt service routine, it branches back to the point of the original program where we stop and continue.The advantage of this approach is efficiency. The user programs progress is halted only during actual transfer.The disadvantage is that it require special hardware in the I/O device to generate the interrupt. And on the processor side, we need special hardware to detect the interrupt and then to save the proper states so we can resume after the interrupt.

+2 = 62 min. (Y:42)Get Interrupt Service Address(3) Get interrupt service addr and change NIOS EA to that address

For each IRQ #, there is a memory address story in an interrupt vector table (also in memory).

Upon that hardware selecting which IRQ, a LOAD to the corresponding vector table entry is performed. The result of that loaded value (4 bytes) is placed in the EA (effective address) of the NIOS ProcessorThus the next instruction executed is the code for the Interrupt Service Routine (ISR)

PIO Core Types: Output, Input w/ Interrupt, Bi-directional

PIO Device MapBase address assigned from SOPCBut device is 4 register locations (4 bytes each location)Registers are: DATA, Direction, InterruptMask, Edgecapture

PIO CORE Data

PIO CORE Edgecapture

PIO CORE Interrupt (IRQ) Generation

PIO CORE Configurations

Expanded PIO Device Map

Expanded PIO Device Map

Expanded PIO Device Map

Expanded PIO Device Map

Hardware Abstraction Layer (HAL).System software that allows programmer to control the hardware devices using a series of function callsControl how or whether interrupts should be handledi.e. turn off interrupts when code executing on NIOS II CPU is critical (time constraint), dont allow serial input cable to get processors attentionHAL Interface

NIOS II Interrupt SetupDeclare variable for holding information that will be passed from device to ISREnable the device Set the control registers on the deviceRegister the ISR with the HAL systemDone in main()Develop code for ISR

Enable Device and Register ISR

Register the ISR with the HAL interface: assign address of the ISR to theInterrupt vector table.Set the controls on the PIO device to capture and cause interruptsDeclare variable to hold state of device that will be passed to ISREnable Device and Register ISR

This is decided at SOPC builder time, user can define which IRQ # [0 up to 31]Memory-mapped device address assigned at SOPC builder timeNIOS II Interrupt Example ISR#include system.h#include altera_avalon_pio_regs.h#include alt_types.h

static void handle_button_interrupts(void* context, alt_u32 id){ // cast the context pointer to an integer pointer. volatile int* edge_capture_ptr = (volatile int*) context;

//Read the edge capture register on the button PIO & Store value. *edge_capture_ptr= IORD_ALTERA_AVALON_PIO_EDGE_CAP(BUTTONS_BASE);

//Write to the edge capture register to reset it. IOWR_ALTERA_AVALON_PIO_EDGE_CAP(BUTTONS_BASE, 0);

// reset interrupt capability for the Button PIO. IOWR_ALTERA_AVALON_PIO_IRQ_MASK(BUTTONS_BASE, 0xf);}

NIOS II Interrupt Example ISR-Expandedstatic void handle_button_interrupts(void* context, alt_u32 id){ // cast the context pointer to an integer pointer. volatile int* edge_capture_ptr = (volatile int*) context;

//Read the edge capture register on the button PIO & Store value. *edge_capture_ptr= IORD_ALTERA_AVALON_PIO_EDGE_CAP(BUTTONS_BASE);

//Write to the edge capture register to reset it. IOWR_ALTERA_AVALON_PIO_EDGE_CAP(BUTTONS_BASE, 0);

// reset interrupt capability for the Button PIO. IOWR_ALTERA_AVALON_PIO_IRQ_MASK(BUTTONS_BASE, 0xf); if ( *edge_capture_ptr == 1) // Check if the first button was pressed LCDwrite("hello world\n");

if ( *edge_capture_ptr == 4) // Check if the 4th button was pressed { IOWR(LEDS_BASE,0, (1 & 0xF)); // Write 1 to the LEDs usleep(1000000); IOWR(LEDS_BASE,0, (0 & 0xF)); // Write 0 to the LEDs }}

NIOS II Interrupt Handling Performance