Interrupts

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Interrupts

Definition:

An electrical signal sent to the CPU (at any time) to alert it to the occurrence of some event that needs its attention

Purpose:

To free the CPU from having to constantly check for the occurrence of these events

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Interrupts

Significance:

all event-driven software, such as GUIs, window managers and operating systems, depend on interrupts to supply their events

What might an event be?

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Events

• Keyboard state change (key pressed or released)

• Mouse movement• System clock tick• Data received• Output buffer empty (or output complete)• Communication error (e.g. data corrupted or

lost contact)

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CPU’s Response to an Interrupt

• The CPU responds to an interrupt at the end of the current instruction, but only if the interrupt is important enough

• The response consists of:1. Saving the current CPU state on the stack

2. Jumping to a special routine, called an interrupt handler or interrupt service routine

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CPU’s Response to an Interrupt

The CPU resumes execution of the interrupted program when the interrupt handler executes a Return from Interrupt (RTI) instruction

The RTI instruction uses the state data that was stored on the stack to restore the state to what it was when the interrupt occurred

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The Interrupt Service Routine

• This is the special piece of code that will run in response to an interrupt request

• Specially written for each interrupting device

• Typically, it will perform actions such as transferring data to or from the device that has requested the interrupt

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Fetch-Execute cycle

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Interrupt Masks and Priorities

How does the processor decide if an interrupt is important enough to service?

There are two possible methods:

• Prioritised Interrupts

• Interrupt Masks

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Prioritised Interrupts• The CPU has a number of interrupt lines• Each interrupt line is given a numeric priority• The CPU itself also has a priority, which is a

number stored in the status register. This number represents the priority of the current program, and can be changed by the program

• If the priority of the interrupt is greater than the priority of the current program then the CPU responds to the interrupt

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Interrupt Masks

Interrupt masks are bits in the CPU’s status register that control which interrupts the CPU will respond to – if the appropriate bits are set, the interrupt will not get served

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Interrupts(typical of many microcontrollers)

Many microcontrollers support two types of interrupt:

• Ordinary interrupts

• Non-maskable interrupts

Ordinary interrupts can be “masked” (i.e. prevented from interrupting the CPU) by setting the interrupt mask bit in the CPU’s status register

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68HC11 Interrupts68HC11

IRQ (interrupt request)

NMI (non-maskable interrupt)

X I N Z C VStatus register

Interrupt mask bit

NMI mask bit

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State Save on Interrupt

The CPU must save enough state data to be able to resume execution of the interrupted program from the exact point where it was interrupted

There are two strategies for doing this:

1. Complete state save

2. Minimum state save

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Complete State Save

• All of the registers accessible to the programmer; i.e.– Program Counter (PC)– Status register– General-purpose registers, data registers

(accumulators), address and index registers

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Minimum State Save

• Program Counter

• Status Register

Q: why save the status register?

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Physical Implementation

Simplest method:

CPU I/O port 2I/O port 1

Control bus

IRQ IRQ1 IRQ2

CPU interrupt-request input

Interrupt-request outputs from each I/O port

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Implications

1. The CPU is told only that an interrupt has occurred. It does not know where it came from.

2. The interrupt handler has to poll the I/O ports – that is, interrogate each one in turn to see which one has caused the interrupt.

3. I/O ports must make it known to the CPU that they have requested an interrupt, e.g. by setting a bit in an I/O status register

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Vectored Interrupts

IACK: CPU’s Interrupt Acknowledge output.

Each I/O port has an IACK input and an IACK output; these are connected together in a daisy chain.

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Vectored Interrupt Response1. The CPU puts an interrupt acknowledge signal on its

IACK output2. Any I/O port that receives an interrupt acknowledge

signal on its IACK input, and is not currently issuing an interrupt, copies the signal to its IACK output

3. Any I/O port that receives an interrupt acknowledge signal on its IACK input, and is currently issuing an interrupt, intercepts the signal and writes a pre-arranged identification number onto the data bus

4. The CPU reads the interrupter’s ID from the data bus

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Where is the Interrupt Handler?• The address of an Interrupt Handler is stored in a

special location in memory• In a simple system, this address is hard-wired into

the CPU• In a system supporting vectored interrupts, the

addresses of all the interrupt handlers are stored in a table in memory. The ID supplied by the I/O port is used as an index into this table

In both cases, the locations containing the interrupt handler addresses are known as interrupt vectors