introducing mips64® and simultaneous multi-threading in an ... · 3/27/2011 · inside...

© 2011 MIPS Technologies, Inc. All rights reserved.

Introducing MIPS64® and Simultaneous Multi-threading in an IP Core: Project “Prodigy”March 27, 2011

2 © 2011 MIPS Technologies, Inc. All rights reserved.

Preview: 64-bit MIPS “Prodigy” Core

World’s First 64-Bit Multi-threaded Multiprocessor IP


Meeting the Challenges of Tomorrow's Applications

Software systems are becoming more complexHigher data-rates and deeper packet inspection in NetworkingManagement of higher data-rate baseband modems in MobileExecution of Java-based applications in Home Entertainment and Mobile

To achieve this the software systems require:Larger memory footprintMuch higher performance

This performance should be delivered: At the lowest possible power envelopeWith minimal silicon areaWhile utilizing low cost off-chip system devices


Parallel is the Way to go – but…

With tight power constraints, parallel is the way to goMore execution pipelines within a single CPUWhen the CPU is fully optimized, a multi-core should be considered

While a single pipeline is efficient, multiple in-line execution units are much less efficient

The “bubbles” in the multi-issue pipeline could be reduced with an Out-of-Order dispatch

But, at the expense of a huge increase in area and power

Execution PipelineInstruction

Queue

Execution PipelineInstruction Queue


Multi-threading to the Rescue

Multi-threading enables much better performance and utilization of the execution units

Multi-threading can increase the already high efficiency of a single execution pipeline

Execution Pipeline

Instruction Queue

Thread 0

Thread 1

Thread 2

Thread 3


Simultaneous Multi-threading is Even Better

Simultaneous Multi-threading (SMT) improves the sub-optimal performance of a multi-issue pipeline

This can be done with a reduced need for power hungry mechanisms such as:

Out-of-order executionSpeculative execution (pre-fetch, branch prediction)

Execution Pipeline

Instruction Queue

Thread 0

Thread 1

Thread 2

Thread 3


TraditionalAdd pipeline stagesMore execution unitsMore speculative execution

Efficiency is reducedHigher performance but

• A lot more logic and leakage• Faster clock increases

dynamic power

MT-BasedAdd VPEsMore execution units

Efficiency is enhancedMuch higher throughput with

• Minimal increase of logic and leakage

• Same frequency

Different Approaches for Increasing Performance

Current Gen

Next Gen

Efficiency

Per

form

ance

1004K

Prodigy

Efficiency

Per

form

ance

Competition MIPS Technologies


Unique Capabilities in MIPS’Multi-threaded Products

Support for light-weight multi-threading: Thread Contexts (TCs) can be used to further increase the number of hardware threads within a Virtual Processing Element (VPE)Increases opportunity to improve performance through multi-threading without need to add full hardware required for implementing another VPE

Quality of Service (QoS) Through use of user-configurable thread schedulerEases management of real time behavior

Efficient inter-thread communication For implementing high-performance data-flow

Zero-overhead interrupt capability Can be implemented through letting a thread “park” until an external event signals it to resume execution


MIPS Technologies’ Multi-threading Solutions

Currently MIPS offers two multi-threaded solutionsSingle-core MIPS32® 34K® processorMulti-core MIPS32® 1004K™ coherent processing system (CPS)

MIPS’ multi-threading architecture allows standard multiprocessor operating systems such as Linux and Android to run unmodified

35+ licenses to-date of MIPS multi-threaded productsTo companies including Altair Semiconductor, Lantiq, Mobileye, MStar, PMC-Sierra, Ralink, Realtek, Sigma Designs and ViXS

33% of the shipping products with a mid-range to high-end MIPS cores are based on a multi-threaded core


The Power of MIPS Multi-threading: PMC’s maxRAID Architecture

PMC-Sierra PM8013 maxSAS RAID-on-Chip Controller with 3 multi-threaded MIPS cores

PMC-Sierra uses both the 34K and 1004K cores

“…performance reaches new levels… The multi-threading MIPS 34K cores deliver performance higher than

any other RAID solution.” – PMC-Sierra


The Power of MIPS Multi-threading: Ralink’s ADSL Internet Access Device

Ralink uses 34K core in new ADSL IAD SoC for “Triple-Play”customer premises equipment

“With this architecture, Ralink is able to efficiently provide deterministic VoIP response and support for multiple

applications in a single device” – Ralink

• Used MT to enable more applications while ensuring high QoS for VoIP

SoC in mass production; successfully deployed in European Telco Network


The Power of MIPS Multi-threading: Mobileye’s EyeQ2™ Vision-Based SoC

Mobileye uses 34K cores in current EyeQ2; licensed 1004K

CPS for next generation

“MIPS’ multi-threaded 34K cores helped us achieve a 6x performance increase in the EyeQ2 vision chip

over the prior generation. ” – Mobileye

The EyeQ2 is the processorinside Mobileye’s C2-270™

Driver Assistance System

EyeQ2 Provides Driver Assistance for new Volvo S60


The Industry’s Increasing Need for More Address Space

Dramatic increases in parallel tasks means more physical memory is needed

32-bits is no longer enough for higher-end embedded applications

Many networking applications are already based on 64-bit architectures

Today’s set-top boxes, DTVs, phones and tablets already pack a GByte of memory; tomorrow's applications will cross the 4GByte limit of 32-bit CPUs

64-bit will be necessary for many embedded applications because of the practically unlimited address space it allows


MIPS64® Architecture is the Answer

World’s first 64-bit microprocessor, MIPS’ R4000, introduced in 1991Established binary compatibility between all 32-bit and 64-bit MIPS implementations that have come to the market since then

Today’s MIPS64 architecture offers the same extended addressing and compatibility with MIPS32

Approx. 15% of MIPS’ royalties today are based on MIPS64 products

A broad ecosystem already exists around the MIPS64 architecture, driven by MIPS64 architectural licensees including Cavium Networks and NetLogic Microsystems

Operating systems, middleware, development tools, etc.

Proven, widely adopted MIPS64 architecture continues to proliferate


The “Prodigy” Project: 64-bits + SMT in IP

Prodigy cores will implement SMTDelivering high performance in minimal silicon footprint and power envelope

Prodigy cores will be offered with single- and multi-core options

MIPS64 architecture in an IP core

Prodigy products will target markets such as Networking, Mobile and the Digital Home

Delivering scalability, flexibility and efficiency

Formal launch of Prodigy products later in 2011

Full characteristics and benchmarks will be disclosed


Why “Prodigy”? Why Now?

Multi-threading dramatically improves performance efficiency for a broad range of embedded applications

Infrastructure and broad, mature ecosystem already in place for MIPS64 architecture &

multiprocessing / multi-threading on MIPS

MIPS Technologies: the only choice for 64-bit multi-threaded IP

The embedded world needs a 64-bit architecture for next-generation networking, mobile and digital home products

World’s first 64-bit multi-threaded multiprocessor IP: a fast path to scalability for next generation designs


At the core of the user experience®

Thank You!

MIPS, MIPS32, MIPS64, MIPS-Based, MIPS-Verified, MIPS Technologies logo are trademarks of MIPS Technologies, Inc. and registered in the U.S. Patent and Trademark Office. MIPS, MIPS32, MIPS64, MIPS-Based, MIPS Logo, MIPS Technologies Logo, CorExtend, Pro Series, microMIPS, M14K, M4K, 4KE, 4KEc, 24K, 24KE, 34K, 74K, 1004K, 1074K, MIPS Navigator, and FS2 are trademarks or registered trademarks of MIPS Technologies, Inc. in the United States and other countries.

introducing mips64® and simultaneous multi-threading in an ... · 3/27/2011 · inside...

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