introducing: the calibre nm platform and calibre … the calibre nm platform and ... calibre pvx...

Introducing:The Calibre nm Platform and Calibre nmDRC

Joe SawickiVP and GM, Design to Silicon Division

June/July 2006

The Calibre nm Platform and Calibre nmDRC, JS, June/July 2006 2

Yield Issues in Nanometer Technologies

SystematicSystematicRandomRandom

ParametricParametric

The Wonderful and Frightening World of Physical Verification and DFM

Additional DFM Rules

Design Size(Geometry Count)


Basic DRC Rules

-10.0020.0030.0040.0050.0060.0070.0080.0090.00100.00

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010

Total Geometric Shape Count

0100200300400500600700

0.35um 0.25um 0.18um 0.13um 0.09um345678910

Rules with 3 metal layers Additional metal rulesTotal DRC rules

Recommended Rules

Litho-friendly Design

Critical Area Analysis

45nm130nm 90nm 65nm

Computational Complexity

Basic DRC Rules



90 nm



Basic DRC Rules



90 nm

65 nm



Basic DRC Rules



90 nm

65 nm

45 nm



Design: Seeing through the Fog

Original Design Data

DRC Rule

130nm

DFM Rule

200nm

Typical DRC Result Typical DFM Result


Complexity Drives a Change From Rules to Models

pinching

Major DFM capabilities are

moving from a rules-based

approach to a models-based

approach

— Critical Area Analysis (CAA)

— Litho-friendly Design (LFD)

Defect size

Prob

abili

ty

Yield=exp(-C(s)*D(s))

D(s):Defect DistributionC(s):Critical Area

Increasing complexity and the rise in multiple issues will force this trend to continue.


Yesterday’s Calibre PlatformResults ViewingCalibre PVX

DRC/LVSDRC/LVS

xRC/xLxRC/xLResultsViewing

Data Query

Data QueryData Query

Results Data

Devices &Parasitics

Derived Layout& Error Markers

Layout Data

SVRF/CAPIMTflex

SVRF/CAPIMTflex

Layout Update

SchematicNetlist

OASIS

GDSII

Post LayoutNetlist

OASIS

GDSII


The New Calibre nm Platform

Optimization

IncrementalAnalysis

IncrementalEnhancement

ConstraintBased

Filtering

DFM Data

RuleDerivations

EnhancementResults

AnalysisResults

Hierarchy &Connectivity

OriginalLayout

Design andMfg. Data

PerformanceConstraints

Mfg Models &Parameters

Open Access

Milky Way

LEF/DEF

Results Analysis

Design DBUpdate

Reports &Visualization

SiliconDeBug

Calibre Analysis& EnhancementRecommendedRules & CAA

RecommendedRules & CAA

Litho FriendlyDesign


Device andInterconnect

Modeling


Modeling

LayoutModifications

LayoutModifications

TVF (TCL)Hyperflex

TVF (TCL)Hyperflex

Design Update

Design QualityAssessment

SensitivityAnalysis

Open Access

Milky Way

LEF/DEF

Results ViewingCalibre PVX

DRC/LVSDRC/LVS


Data Query


Results Data

Devices &Parasitics


Layout Data

SVRF/CAPIMTflex

SVRF/CAPIMTflex

Layout Update

SchematicNetlist

OASIS

GDSII

Post LayoutNetlist

OASIS

GDSII


Optimization

IncrementalAnalysis


ConstraintBased

Filtering

DFM Data

RuleDerivations

EnhancementResults

AnalysisResults


OriginalLayout

Design andMfg. Data



Open Access

Milky Way

LEF/DEF

Results Analysis

Design DBUpdate


SiliconDeBug






Modeling


Modeling

LayoutModifications

LayoutModifications

TVF (TCL)Hyperflex

TVF (TCL)Hyperflex

Design Update


SensitivityAnalysis

Open Access

Milky Way

LEF/DEF


DRC/LVSDRC/LVS


Data Query


Results Data

Devices &Parasitics


Layout Data

SVRF/CAPIMTflex

SVRF/CAPIMTflex

Layout Update

SchematicNetlist

OASIS

GDSII

Post LayoutNetlist

OASIS

GDSII

Calibre nm Platform


Introducing Calibre nmDRC

CalibreDRC

Block & CellCreation

Place & Route

ChipAssembly

Tapeout

CalibreDRC

Block & CellCreation

Place & Route

ChipAssembly

Tapeout

Calibre nmDRC


Achieving Faster Turn Around Times (TAT)

Time

CPU

Util

izat

ion

OperationCell/bin

Single CPUSingle CPU

CPU

Thread Scheduler

DataDataOperationsOperations

Multi CPU Data PartitioningMulti CPU Data Partitioning

CPU

Thread Scheduler

OperationsOperations

CPU

CPUDataData

Data and Operation PartitioningData and Operation Partitioning

CPU

Thread Scheduler

OperationsOperations

CPU

CPUDataData

CPU

CPU

CPUDataData


Multiprocessing EnvironmentSMP MachineSMP

MemoryManagement

In-MemoryDatabse

Distributed SM Ext.

Distributed MM Ext.

ScheduleManagement

CPU

CPU

CPU

CPU

SMP MachineSMP

MemoryManagement

In-MemoryDatabse

Distributed SM Ext.

Distributed MM Ext.

ScheduleManagement

CPU

CPU

CPU

CPU

CPU

CPU

SMP MachineSMP

MemoryManagement

In-MemoryDatabse

Distributed SM Ext.

Distributed MM Ext.

ScheduleManagement

CPU

CPU

CPU

CPU

CPU

CPU

CPU

1

CPU

1

CPU

2

CPU

2

Distributed Machines

Multi-CoreCluster

SMP

SingleCPU

Multi-Core Cluster


Calibre nmDRC Performance Improvement

Hyperscaling provides a dramatic speed upSingle CPU vs. Hyperscaling - Distributed

010203040506070

1 2 3 4 5 6Customer Designs

Run

Tim

e ( h

r )

Single CPUHyperscaling - Distributed

CustomerDB Size,

Design NodeCPU's

Run Time 0:18 1:19 2:01 1:0040 40 32 24 32 40

2:18 0:48

C D E F

0.5GB, 90nm 6.8GB, 130nm 7GB 7.2GB, 90nm 11GB, 90nm 1.3GB, 90nm

A B

Excellent scaling over a range of job sizes and types


Calibre nmDRC Performance Improvement - SMP

Hyperscaling delivers improved TAT on existing CAPEX

Average improvement 1.9x

Traditional MT (SMP) vs. HyperScaling (SMP)

-

5

10

15

20

25

18GB, 80nm Chip,

16CPU1.2GHz

1.3GB, 90nm Chip,

16CPU1.2GHz

6.8GB,130nm Test,

24CPU1.2GHz

7.2GB, 90nm Mask,

24CPU1.2GHz

4.3GB, 90nm Chip,

4CPU2.8GHz

10.2GB,90nm Chip,

4CPU2.8GHz

Customer Designs (Size, Node, Design Type, CPUs, Scaling, Utilization)

Run

Tim

e ( h

r ) Traditional MT

Hyperscaling - SMP

— Extends life

— Supports a wide range of H/W platforms

— Does not require H/W investment


Calibre nmDRC Performance Improvement - Distributed

Hyperscaling provides fast TAT on distributed hardware

Average improvement 2.9x4 longest designs improved by 3.8x

Traditional Mtflex (Distributed) vs. Hyperscaling (Distributed)

-12345678

1.3GB, 90nm

Full_Chip,40CPU

6.8GB, 130nmTest_Pat.,

40CPU

0.47GB, 90nm

Full_Chip,40CPU

7.2GB, 90nm

Mask, 24CPU

1.2GB, 90nm

Test_Pat.,40CPU

2.8GB, 90nm

Full_Chip,40CPU

4.0GB, 90nm

Full_Chip, 8CPU

0.6GB, 90nm

Memory,40CPU

0.7GB, 90nm

Full_Chip,40CPU

0.15GB, 70nmMemory,24CPU

Customer Designs (Size, Node, Design Type, CPUs, Scaling, Utilization)

Run

Tim

e ( h

r )

Traditional MTflexHyperscaling - Distributed


Performance Scaling with Design Size

0

1

2

3

4

Run

Tim

e (h

ours

)

8 16 27

GDS File Size (Gb)

Performance Impact with Design Size

Performance insensitive to data volume

32 CPU’s

Calibre nmDRC: Drops Into Current CAD Environment Without Disruption

Design Environments

RuleFiles

Encryption

Interactive,Batch

Invocation,Control

DesignData

TrainedUsers

FlowMaintenance

ConfigurationManagement

Calibre nmDRC ReportingFormats

DebugMethodologies

ModificationFlows

Benefits— Realize new functionality and

dramatic total cycle time improvement

— Maintain existing infrastructure— Drop in, no risk

CalibreDRC



Calibre nmDRC Dramatically Reduced Iteration Runtimes

Incremental DRC— Highlight errors as identified

Begin debug immediately -before job completion

— Automatically identify changed regions

DB Diff

— Minimize subsequent runtimesStream-out only changed areasRun only affected checks


Traditional Serial DRC Verification

Calibre nmDRC Dramatically Reduced Iteration Runtimes

DebugTranslation DRC Runtime

Calibre nmDRC: Dynamic Results Visualization and Incremental VerificationDays

2 hrs 6 hrs4 hrs

Benefits— Traditional serial verification process

produces < PV iteration per shift

— nmDRC revolutionizes the debugging process

— Dramatically improves productivity

Erro

r #1

Erro

r #2

Erro

r #3

Erro

r #4

Erro

r #5


Calibre nmDRCModern Development Tools

Traditional SVRF Recommended Rule Metal1

METAL1.1.1R#rra#b0.28 = INT ame1 >=0.256 <0.28 ABUT >0<90 OPPOSITE REGIONMETAL1.1.1R#rra#b0.30 = INT ame1 >=0.28 <0.30 ABUT >0<90 OPPOSITE REGIONMETAL1.1.1R#rra#b0.32 = INT ame1 >=0.30 <0.32 ABUT >0<90 OPPOSITE REGIONMETAL1.1.1R#rra#b0.28 {@ {Minimum METAL1 width >=0.256<0.28}

DFM ANALYZE METAL1.1.1R#rra#b0.28 METAL1.1.1R#rra#b0.30 METAL1.1.1R#rra#b0.32 >=0 [(COUNT(METAL1.1.1R#rra#b0.28))*1.0/AREA()] RDB ONLY "yield.rdb"

}METAL1.1.1R#rra#b0.28_c {@ output RR yield prediction to RDB BY CELL

@ check: METAL1.1.1R#rraDFM ANALYZE METAL1.1.1R#rra#b0.28 METAL1.1.1R#rra#b0.30 METAL1.1.1R#rra#b0.32 >= 0 BY CELL NOPSEUDO [(COUNT(METAL1.1.1R#rra#b0.28))*1.0/AREA()] RDB ONLY "yield.rdb"

}METAL1.1.1R#rra#b0.28_ {@ {Minimum METAL1 width >=0.256<0.28}

COPY METAL1.1.1R#rra#b0.28}METAL1.1.1R#rra#b0.30 {@ {Minimum METAL1 width >=0.28<0.30}





COPY METAL1.1.1R#rra#b0.30}METAL1.1.1R#rra#b0.32 {@ {Minimum METAL1 width >=0.30<0.32}





COPY METAL1.1.1R#rra#b0.32}METAL1.1.1R#rra# {@ {Minimum METAL1 width}

DFM ANALYZE METAL1.1.1R#rra#b0.28 METAL1.1.1R#rra#b0.30 METAL1.1.1R#rra#b0.32 >=0 [((COUNT(METAL1.1.1R#rra#b0.28))*1.0+(COUNT(METAL1.1.1R#rra#b0.30))*0.8+(COUNT(METAL1.1.1R#rra#b0.32))*0.6)/AREA()] RDB ONLY "yield.rdb"

}METAL1.1.1R#rra#_c {@ output RR yield prediction to RDB BY CELL

@ check: METAL1.1.1R#rraDFM ANALYZE METAL1.1.1R#rra#b0.28 METAL1.1.1R#rra#b0.30 METAL1.1.1R#rra#b0.32 >= 0 BY CELL NOPSEUDO [((COUNT(METAL1.1.1R#rra#b0.28))*1.0+(COUNT(METAL1.1.1R#rra#b0.30))*0.8+(COUNT(METAL1.1.1R#rra#b0.32))*0.6)/AREA()] RDB ONLY "yield.rdb"

}

Repeat For Metal2 through Metal9Total Lines of SVRF Code = 509

Calibre TVFRecommended Rule Metal1

set met111_bin {SLIST 0.256 0.28 0.30 0.32}Create_RRA_SVRF METAL1.1.1R {WID_MIN_L1 {ame1 ORTHO} "Minimum METAL1 width"} \

$met111_bin {DLIST 1.0 0.8 0.6} {USER $lambda/AREA()}

Call Template = 2 lines of TVF CodeLibrary Template = 59 lines of TVF CodeForloop all metals = 3 lines of TVF Code

Total lines of TVF Code = 64

High level programming language

Simplifies the development and maintenance of advanced rule files


Calibre Integrated into Design Platforms

MentorIC Station, DESIGNrev

CadenceVirtuoso/ADE, Encounter

SynopsysAstro

MagmaBlastFusion

GDSII

OASIS

OpenAccess

Milkyway

LEF/DEF


Virtuoso Integration Example


BlastFusion Integration Example


Encounter Integration Example


OASIS: Tackling the Capacity Bottlenecks

Original GDSII-to-OASISFile Size Reduction Distribution

Reduction Amount (X)

GDSIIGDSII

>10x!>10x!

OASIS

Evaluation of 5000 customer GDSII vs OASIS data files!

Statistical Analysis Augments SimpleError MarkersOriginal Design Data

DRC Rule

130nm

DFM Rule

200nm

Typical DRC Result Typical DFM Result


Calibre YieldAnalyzer


Yield Analysis and Visualization

YRC Rule Summary Table


Model Based Verification: From DRC to nmDRCSystematic ParametricRandom

Rul

e B

ased

Mod

el B

ased

Calibre YieldAnalyzerCritical Area Analysis

Calibre LFDLitho Variation Analysis

Calibre LVS/xRC/xLMfg Aware Silicon Modeling

Calibre YieldAnalyzerRecommended Rule Analysis



Solving the WHOLE Cycle Time Issue

Design


Incremental DRCDramatically Reduces

Iteration Runtimes

Rule and Model-Based Verification

OASIS FormatSignificantly Reduces

Stream-out Time

TVF Simplifies Rule Scripting &

Maintenance

Statistical Analysis Facilitates Pinpoint

Debugging

Deb

ugD

ebug

PVPV

Stre

amSt

ream

Classic Serial VerificationClassic Serial Verification

Deb

ugD

ebug

Stre

amSt

ream

PVPV

Deb

ugD

ebug

PVPVnmDRC VerificationnmDRC Verification

Design

HyperscalingDramatically Reduces

Runtime

Direct Database Access Eliminates

Stream-out

Dynamic Results Visualization Enables

Real-Time Debug


Summary

The Calibre nm Platform provides the industry’s most robust platform for design to silicon in the DFM era

With Calibre nmDRC we continue to provide best in class performance, improved total TAT and the design database integration required for nanometer design


Design Environment Integration: How It Works


Introducing the New Calibre nm Platform

Optimization

IncrementalAnalysis


ConstraintBased

Filtering

DFM Data

RuleDerivations

EnhancementResults

AnalysisResults


OriginalLayout

Design andMfg. Data



Open Access

Milky Way

LEF/DEF

Results Analysis

Design DBUpdate


SiliconDeBug






Modeling


Modeling

LayoutModifications

LayoutModifications

TVF (TCL)Hyperflex

TVF (TCL)Hyperflex

Design Update


SensitivityAnalysis

Open Access

Milky Way

LEF/DEF


DRC/LVSDRC/LVS


Data Query


Results Data

Devices &Parasitics


Layout Data

SVRF/CAPIMTflex

SVRF/CAPIMTflex

Layout Update

SchematicNetlist

OASIS

GDSII

Post LayoutNetlist

OASIS

GDSII


Traditional DRCResults ViewingCalibre PVX

DRC/LVSDRC/LVS


Data Query


Results Data

Devices &Parasitics


Layout Data

SVRF/CAPIMTflex

SVRF/CAPIMTflex

Layout Update

SchematicNetlist

OASIS

GDSII

Post LayoutNetlist

OASIS

GDSII

Optimization

IncrementalAnalysis


ConstraintBased

Filtering

DFM Data

RuleDerivations

EnhancementResults

AnalysisResults


OriginalLayout

Design andMfg. Data



Open Access

Milky Way

LEF/DEF

Results Analysis

Design DBUpdate


SiliconDeBug






Modeling


Modeling

LayoutModifications

LayoutModifications

TVF (TCL)Hyperflex

TVF (TCL)Hyperflex

Design Update


SensitivityAnalysis

Open Access

Milky Way

LEF/DEF


DRC/LVSDRC/LVS


Data Query


Results Data

Devices &Parasitics


Layout Data

SVRF/CAPIMTflex

SVRF/CAPIMTflex

Layout Update

SchematicNetlist

OASIS

GDSII

Post LayoutNetlist

OASIS

GDSII

Introducing Next Generation DRC Calibre nmDRC


CalibreDRC

Calibre nmDRC: Drops Into Current CAD Environment Without Disruption


ModificationFlows

DebugMethodologies

DesignEnvironments

Interactive,Batch

Trai

ned

Use

rs

Flow

Mai

nten

ance

DesignData

RuleFiles

Encryption

ReportingFormats

Invocation,Control

Con

figur

atio

nM

anag

emen

t Benefits— Realize new functionality and dramatic

total cycle time improvement — Maintain existing infrastructure— Drop in, no risk

CalibrenmDRC


Advantages of Calibre nmDRC

Faster Turn Around Time

Modern Development Tools

Model-Based Verification

Statistical Analysis to Augment Simple Error Markers

Integration that allows tight ‘fix’ loops

Higher productivity

ComputationalComputationalComplexityComplexity

The Fog of DFMThe Fog of DFMIssuesIssues

Yield Is HardYield Is HardTo DoTo Do

Rules Moving toRules Moving toModelsModels

Calibre nmDRCCalibre nmDRC

introducing: the calibre nm platform and calibre … the calibre nm platform and ... calibre pvx...

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