introduction digitaldesign
TRANSCRIPT
TYPES OF IC DESIGNS Analog Digital
Full Custom Standard-cell based
(ASIC) from RTL
Semi-custom Steps in a design
process
Define Overall ChipC/RTL Model
Initial Floorplan
Cell LibrariesCircuit Schematics
Megacell BlocksCircuit Simulation
Layout and FloorplanPlace and Route
Parasitics ExtractionDRC/LVS/ERC
Behavioral SimulationLogic Simulation
SynthesisDatapath Schematics
RTL SimulatorSynthesis ToolsTiming AnalyzerPower Estimator
Text EditorC Compiler
Schematic EditorCircuit Simulator
Router
Designer Tasks Tools
Architect
LogicDesigner
DesignerCircuit
PhysicalDesigner
Place/Route ToolsPhysical Design and Evaluation Tools
TYPES OF LOGIC STRUCTURES Combinational logic
output depends on current inputs Sequential logic
output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: ??
CL
clk
in out
clk clk clk
CL CL
PipelineFinite State Machine
WHY SEQUENTIAL DESIGN? If tokens moved through pipeline at constant
speed, no sequencing elements would be necessary
Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses
This is called wave pipelining in circuits In most circuits, dispersion is high
Delay fast tokens so they don’t catch slow ones.
SEQUENCING OVERHEAD Use registering elements to delay fast tokens
so they move through exactly one stage each cycle.
Inevitably adds some delay to the slow tokens
Makes circuit slower than just the logic delay Called sequencing overhead
Clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining
sequence
RULES FOR RIGHT SEQUENCING To Ensure Proper Sequencing of Data through a
Sequential Circuit: Rule 1: Data launched by a Flip-Flop SHOULD BE
captured by the subsequent FF at the subsequent edge Rule 2: Data launched by a FF SHOULD NOT BE captured
by the subsequent FF at the same edge Example: A serial-in-serial-out shift register
D3 D2 D1 D0
D Q
F1
D Q
F2
D Q
F3
D Q
F4CLK
D3D2D1D0
(IM)PROPER SEQUENCING
What if: F2 violates setup requirement? F2 violates hold requirement?
D0 D1 D2 D3
D0 D1 D2 D3xxxx D0 D1 D2
xxxx D0 D1
xxxx D0
x
CLK
Input
F1/QF2/QF3/Q
F4/Q
STATIC TIMING ANALYSIS Analyzing timing performance Flip-Flops and latches break signal flow by means of
clock Analogous to closing and opening valves in fluid pipe
Goal : every timing path to meet the required timing constraints
Design divided into pairs of registers separated by combinational logic Launch (start or source) register Capture (end or destination) register
For every endpoint register: Many paths possible, each one starting at different start points Known as fanin cone
TIMING PATHS
F2
F1
Fn
.
.
.in1in2
Fanin cone
F(End as well as Start for next stage)
Path1
Path2
Path n