introduction from the 53rd ectc program chairman donna...
TRANSCRIPT
The 53rd Electronic Componentsand Technology Conference(ECTC) will be held at theSheraton New Orleans Hotel inNew Orleans, Louisiana, from May27-30, 2003.
This annual international conferencebrings together the best in packag-ing, components, and microelec-tronic systems science, technology,and education in an environment of
cooperation and technical exchange. The conference programincludes technical sessions, professional development courses, apanel discussion, a plenary session, and a technology corner.
The Technical Program will have more than 300 papers focusingon leading edge developments and technical innovations. Theprogram is divided into 38 sessions covering a wide range of top-ics, including optoelectronics, RF and MEMS packaging, 3D andhigh performance package design, flip chip and Pb-free intercon-nections, wafer-level packaging and manufacturing, reliability testmethods, and electrical, thermal and mechanical modeling.
Two poster sessions will offer unique opportunities for authorsand ECTC attendees to interact, discuss in detail, and exchangeideas in a more relaxed forum. To emphasize the importance ofthis method of technical presentation, the ECTC recognizes andgives awards for the best and most outstanding posters.
Two technical sessions will specifically explore topics related toengineering education and web-based packaging education forthe 21st century.
This year, the International Academic Workshop (sponsored bythe Packaging Research Center) will be held in conjunction withECTC as a one-day workshop on Tuesday, May 27. The purposeof this workshop is to make the academic community aware ofthe significant advances being made worldwide in next genera-tion electronic packaging education and to promote internationalcollaborations that serve the global technical community.
The 53rd ECTC will feature a panel discussion on packagingdirections. This session, offered on Tuesday evening, May 27, has aformat that allows for ample exchange and dialogue between thepresenters and audience.
A plenary session featuring presentations on leadership tech-nologies, organized by Dr. Phil Garrou, is the feature forWednesday evening, May 28. This session will provide the con-ference participants the opportunity to gain the insight and per-spective of technical and business leaders of dynamic companiesat the forefront of technology.
The conference offers 14 professional development courses onTuesday, May 27. Dr. Ronald Scotti and his committee havebrought together industry experts from a variety of disciplines tooffer state-of-the-art technology reviews and updates in con-densed half-day and full-day formats. Course topics cover a widerange of technologies, including RF/wireless packaging, GHz IC
packaging, photonic-optoelectronic packaging and systems, sys-tems on a package, chip scale and wafer scale packaging, integrat-ed passive technology, and polymers for electronic packaging.These courses are eligible for Continuing Education Unit (CEU)credits.
A technology corner is available on Wednesday afternoon and allday Thursday, May 28-29. The technology corner complementsthe technical program by offering companies the opportunity toexhibit their products and services in an environment thatenables discussion and interaction with the managers, engineers,and scientists attending ECTC.
Each conference attendee will receive a choice of the proceed-ings in a CD-ROM or printed book format. Both can be pur-chased for a nominal fee.
The ECTC would not be possible without the sponsorship ofthe IEEE Components, Packaging, and Manufacturing TechnologySociety and the Electronic Components,Assemblies, andMaterials Association (the components sector of the ElectronicIndustries Alliance) and numerous corporate participants andsponsors.
The ECTC Executive Committee and Program Committees,composed of more than 140 engineers and scientists who con-tribute their time and energy to this conference, hope you findthe 53rd ECTC to be the premier international meeting formicroelectronic packaging, components, and systems technolo-gies.
Please join us at this year’s conference.
Donna M. Noctor
53rd ECTC Program Chair
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IndexECTC Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Transportation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3General Information . . . . . . . . . . . . . . . . . . . . . . . . . . .3Technology Corner Exhibits . . . . . . . . . . . . . . . . . . . . .4Panel Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Plenary Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Academic Workshop . . . . . . . . . . . . . . . . . . . . . . . . . . .4Luncheons and Receptions . . . . . . . . . . . . . . . . . . . . . .5Hotel Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Executive & Program Committees . . . . . . . . . . . . . . .6,7Area Attractions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Conference Overview . . . . . . . . . . . . . . . . . . . . . . . . . .9Short Courses . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-14Program Sessions . . . . . . . . . . . . . . . . . . . . . . . . . .15-29Corporate Conference Sponsors . . . . . . . . . . . . . . . . .30Registration Information . . . . . . . . . . . . . . . . . . . . .30,31
Introduction from the 53rd ECTC Program Chairman Donna M. Noctor
The 53rd Electronic Components and Technology Conference (ECTC)Sheraton New Orleans Hotel, New Orleans, Louisiana, May 27 - 30, 2003
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Advance RegistrationTo register in advance for the 53rd ECTC, your application andpayment check/credit card information must be received no laterthan May 12, 2003. Complete and submit the on-line registrationform (preferred registration) at www.ectc.net/reg.htm, mail tothe address on the Advance Registration Form on page 31, or faxyour form with payment information to (703) 875-8908.
Register early…Save $100. All applications received after May12, 2003 will be considered Door Registrations.Those who regis-ter in advance may pick up their registration packets at theECTC Registration Desk in the Grand Ballroom Foyer (5thfloor), Sheraton New Orleans Hotel.Additional AdvancePrograms are available from:
Jim Bruorton, Publicity Chairman53rd Electronic Components & Technology Conferencec/o KEMET Electronics CorporationP.O. Box 5928Greenville, SC 29606Phone: (864) 963-6621 Fax: (864) 963-6444Email: [email protected]
DO NOT SEND ADVANCE REGISTRATIONS TO THEABOVE ADDRESS. SEE REGISTRATION FORM ONPAGE 31.
Registration FeesAdvance registration with proceedings (CD or printed), ECTC,
CPMT and Program Chair Luncheons . . . . . . . . . . . . .$550*Door registration with proceedings (CD or printed), ECTC,
CPMT and Program Chair Luncheons . . . . . . . . . . . . .$650*One Day Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$350Speaker/Session Chair (Door Rate $450) . . . . . . . . . . . . .$350Speaker/One Day . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$225Student . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$125Tuesday Single AM or PM Course with Luncheon . . . . . .$325#Tuesday AM & PM Course with Luncheon . . . . . . . . . . .$525# Student All-Day Courses . . . . . . . . . . . . . . . . . . . . . . . . . . . .$50Proceedings only, U.S. Postpaid . . . . . . . . . . . . . . . . . . . . . .$300Foreign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$350
* IEEE Member - Advance/$450, Door/$550# Door rate will be an additional $50Note: There will be no refunds on cancellations made afterMay 12, 2003.
At Door Registration ScheduleRegistration will be held at the Grand Ballroom Foyer (5th Floor) as follows:Monday, May 26, 2003 – 3:00 to 5:00 PM (Short Courses & Conference)Tuesday, May 27, 2003 – 6:45 to 8:00 AM (AM Short Courses Only)Tuesday, May 27, 2003 – 11:00 AM to 1:15 PM (PM Short Courses Only)Tuesday, May 27, 2003 – 1:15 PM to 5:00 PM (Conference)Wednesday, May 28, 2003 – 6:45 AM to 4:00 PMThursday, May 29, 2003 – 7:30 AM to 4:00 PMFriday, May 30, 2003 – 7:30 AM to 12:00 PM
General InformationConference organizers reserve the right to cancel or change theprogram without prior notice.
Loss Due to TheftConference management is not responsible for loss or theft ofpersonal belongings. Security for each individual’s belongings isthe individual’s responsibility.
Tax DeductionsTreasury regulation 1.162.5 currently permits an income taxdeduction for educational expenses (fees and cost of travel,meals, and lodging) undertaken to (1) maintain or improve skillsrequired in one’s employment; or (2) meet express requirementsof an employer. Check with your accountant or tax attorney.
Coffee Break SponsorsSponsorships are available for companies who would like to par-ticipate in the 2003 Electronic Components and TechnologyConference by assisting in sponsoring the conference breaks.Your company’s name will be included in the conference finalprogram and will be displayed on a sign in the refreshments area.A table will be provided nearby to display limitedpromotional/informational material about the companies spon-soring breaks.To sign up to sponsor a coffee break, simply indi-cate your interest on the Conference Advance Registration form(page 31) and enclose the $350 sponsorship fee, payable to the53rd Electronic Components and Technology Conference. Pleasenote: Sponsorships must be prepaid, and must be received at leastfour weeks before the conference in order to be listed in the FinalProgram. For further information, call EIA (703) 907-8027.
53rd ECTC Advance Registration
54th Electronic Components and Technology ConferenceCaesars Palace, Las Vegas, Nevada • June 1 - 4, 2004
Make plans now to join us!
The above schedule for Tuesday will be vigorously enforced to prevent students from being late for their courses.
With the current economic climate, com-panies are being very careful with theirselection of conferences and trade showswhere they will exhibit their products andservices. More and more companies havedetermined that ECTC provides them theopportunity to identify superiorprospects.The primary reason is that theengineers and managers who attendECTC hold decision-making positions atthe world’s leading electronics industry’sequipment and components manufactur-ers.The attendees are attracted byECTC’s strong technical program.Authorsin the field believe that ECTC offers thebest forum for presenting their work.
Following is a list of current exhibitors.Exhibit hours will be from 1:30 PM to6:30 PM on Wednesday, May 28 and 9:00AM to Noon and 1:30 PM to 6:00 PM onThursday, May 29. Exhibit spaces are stillavailable. To obtain information aboutexhibiting your products or services, callBill Moody at (302) 478-4143, fax to (302) 478-7057, or email [email protected]. The exhibit applica-
tion and exhibitor list are available on theECTC web site at www.ectc.net.
3M Austin CenterAblestik Laboratories
Advanced Packaging MagazineAnsoft Corporation
ANSYS, Inc.Applied Simulation Technology
Bergquist Company,TheChip Scale Review Magazine
Cool Shield, Inc.Dow Chemical Company
Dow Corning CorporationElectronic Packaging & Production
MagazineElectronics Cooling Magazine
Emerson & CumingEpoxy Technology, Inc.
Fluent Inc.HD Microsystems
Henkel LoctiteHitachi Cable America, Inc.Interconnect Systems Inc.
Kluwer Academic PublishersKyocera America, Inc.
Mitsui Chemicals America, Inc.National Semiconductor Die Products
NEXX Systems LLCNippon Steel Chemical Co., Ltd.
Optimal CorporationPac Tech Gmbh
Packaging Research Center Sanyu Rec. Co. Ltd.
Siemens Dematic EASSIGRITY, Inc.
Sony Chemicals Corporation of AmericaSumitomo Electric USA, Inc.
SUSS MicroTecTechSearch International, Inc.
Teledyne Interconnect DevicesTeledyne Microelectronics
Telephus Inc.Tempo ElectronicsThermagon, Inc.
Toray Engineering Co., Ltd.Ultratech Stepper
Unitive, Inc.Vishay Intertechnology, Inc.
ZIMARCZymet, Inc.
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ECTC 2003 Panel Discussion
ECTC Plenary SessionThe Coming Changes in IC TechnologyWednesday, May 28, 2003 – 7:00 PM - 9:00 PM
Chair: Phil Garrou – Dow at MCNC (IEEE CPMTTechnical Vice President)
1. Status of Non-silicon High Frequency I Technology2. Strained Silicon Technology – Dr. Eugene Fitzgerald –
MIT/Amberwave Inc.3. Entering the Era of Polymeric Transistors –
Dr. Henning Sirringhouse – Plastic Logic
International Academic WorkshopTuesday, May 27, 2003 – 8:15 AM - 5:00 PM
The Academic Conference Workshop will provide opportunities forfaculty to present courses, curriculum, and other educational pro-grams they developed, and exchange ideas on how to improve thestatus of microsystems packaging education.
1. Session 1: Novel Electronic Packaging Education Program
2. Panel Session:Assessment of Packaging Courses and Programs Moderator – Avram Bar-Cohen, University of Maryland
3. Round Table Discussion: International Partnerships and Exchange ProgramsModerator – Rao Rummala, Georgia Institute of Technology
Technology Corner Exhibits
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LuncheonsShort Course LuncheonThe Electronic Components and Technology Conference willsponsor a luncheon on Tuesday, May 27th for all short courseattendees.
ECTC LuncheonThe Electronic Components and Technology Conference willsponsor a luncheon on Wednesday, May 28th for conferenceattendees.
CPMT LuncheonThe IEEE Components, Packaging and Manufacturing TechnologySociety will sponsor a luncheon for conference attendees onThursday, May 29th.
Program Chair LuncheonOn Friday, May 30th, the Program Chairman will sponsor aluncheon for conference attendees.
Hotel AccommodationsRooms for ECTC attendees have been reserved at the SheratonNew Orleans Hotel. The special conference rate is $155++ forsingle/double, main house, and $175++ single/double, club level.
The 1,110 guest room, 53 luxury suite and 200 elegantly appoint-ed club-level room hotel is located on Canal Street in the heartof the business district and French Quarter.
Room reservations must be made directly with the hotel byApril 28, 2003 to ensure special convention rates. If you need tochange or cancel your reservation, please do so prior to the can-cellation deadline. Failure to do so may result in forfeiture ofyour deposit.There is a $75 charge for early departures. (Check-in time is 3:00 PM and check-out time is 12:00 PM.) The hotel is15 miles, 30 minutes from the Louis Armstrong InternationalAirport. (Taxi and shuttle are approximately $25 and $12, respec-tively.)
53rd ECTC Gala ReceptionAll badged attendees and guests are invited to attend
a reception hosted by KEMET Electronics
Corporation, KOA Speer Electronics, Inc., Murata
Electronics North America, ROHM Electronics USA,
and Vishay on Thursday, May 29th at 6:30 PM
General Chairman’s SpeakersReception
Tuesday, May 27, 2003
6:00 PM - 7:00 PM
Photograph courtesy of Sheraton New Orleans Hotel Photograph courtesy of New Orleans Metropolitan Convention and Visitors Bureau, Inc.
ExecutiveCommittee Wayne HowellGeneral ChairIBM Corporation(845) 892-5360
Steve BezukVice-General ChairKyocera America, Inc.(858) 576-2651
Robert WillisVice-Chair AdministrationECA/EIA(703) 907-8021
Donna M. NoctorProgram [email protected]
Patrick Thompson Asst. Program ChairTexas Instruments, Inc.(972) 995-7660
Peter J.WalshArrangements ChairEIA/ECA(703) 907-8028
Thomas G. Reynolds, III Finance ChairMurata Electronics NA, Inc.(770) 433-7825
James A. BruortonPublicity ChairKEMET Electronics Corporation(864) 963-6621
John H. LauPublications ChairAglient Technologies, Inc.(408) 553-2358
Mino F. DautartasWebsite Administration Chair(540) 953-2160
Michael B. McShanePast General ChairMotorola, Inc.(512) 996-6175
Ronald E. Scotti, ProfessionalDevelopment Course ChairConsultant(908) 534-2039
Glyndwr Smith, EIA/ECARepresentativeVishay(610) 251-5274
C. P. Wong, IEEE/CPMTRepresentativeGeorgia Institute of Technology(404) 894-8391
ProgramCommittees
Advanced PackagingJoseph W. Soucy, ChairDraper Laboratory(617) 258-2953
Sudipta K. Ray, CochairIBM Microelectronics(845) 894-6240
Tim AdamsDow Corning Corporation(989) 496-8867
Daniel BaldwinGeorgia Institute of Technology(404) 894-4135
Karla Y. CarichnerCoexant Systems(949) 483-9151
Douglas HopkinsHigh Power Electronics Institute(607) 729-9949
Satoshi ItoNitto Denko Corporation+81 532 431802
Beth KeserMotorola, Inc.(480) 413-8022
Young KimTessera(408) 383-3685
Jeffery A. KnightIBM Corporation(607) 757-1015
S.W. Ricky LeeHong Kong University of Science &Technology+852 2358 7203
Yee L. LowLucent Technologies(908) 582-2718
Karen W. MarkusJDS Uniphase(919) 806-4682
Raj N. MasterAMD(408) 982-7023
Mike McShaneMotorola, Inc.(512) 996-6175
Gary MorrisonTexas Instruments, Inc.(972) 995-4851
Masood MurtuzaTexas Instruments, Inc.(281) 274-2403
Luu T. NguyenHelsinki University of Technology+358 9 451 5905
Raj PendseChipPAC, Inc.(510) 979-8330
Ashok SaxenaLucent Technologies, Inc.(973) 386-5211
Rick SiglianoKyocera America Inc.(858) 576-2792
E. Jan VardamanTechSearch International, Inc.(512) 372-8887
Components & RFLeonard W. Schaper, ChairUniversity of Arkansas(479) 575-8408
Eric Michelson, CochairVishay Intertechnology, Inc.(610) 251-5279
Rao BondaMotorola, Inc.(480) 413-6121
Amit P. AgrawalPropulsion Networks(408) 369-5779
William ClarkIBM Corporation(802) 769-9280
Shankar Ekkanath-MadathilDe’Monfort University+44 116 250 6158
Craig GawMotorola, Inc.(480) 413-5920
Lih-Tyng HwangMotorola, Inc.(847) 576-5182
Mahadevan K. IyerInstitute of Microelectronics+65 7705424
Timothy G. LenihanConsultant(585) 249-4781
Li LiMotorola, Inc.(480) 413-6653
Koji NiheiWaseda University+81 3 5286 3171
Albert F. PuttlitzMechanical Eng. Consultant(802) 899-4692
Thomas G. Reynolds, IIIMurata Electronics NA, Inc.(770) 433-7825
Ho-Ming TongASE Group+886 2 8780 5489
Connectors & ContactsJim Johnson, ChairBrush Wellman, Inc.(216) 383-4014
Jerry WitterChugal USA, Inc.(847) 244-6025
EducationPaul Wesling, Chair(408) 252-9051
Leyla Conrad, CochairGeorgia Institute of Technology(404) 385-0439
Avram Bar-CohenUniversity of Maryland(301) 405-3173
William BrownUniversity of Arkansas(479) 575-6045
Jim MorrisPortland State University(503) 725-9588
Albert F. PuttlitzMechanical Eng. Consultant(802) 899-4692
Andrew A.O. TayNational University of Singapore+65 6874 2207
Rao R.TummalaGeorgia Institute of Technology(404) 894-9097
InterconnectionsRajen Dias, ChairIntel Corporation(480) 554-5202
David McCann, CochairAmkor Technology, Inc.(408) 821-5000
Mark BrillhartCisco Systems(408) 525-7466
Yifan GuoSkyworks Solutions, Inc.(949) 231-4796
Christine KallmayerTechnical University of Berlin+49 30 46403228
Sung K. KangIBM - TJ Watson Research Ctr.(914) 945-3932
Corey KoehlerAmkor Technology, Inc.(480) 821-2408 X5373
Charles LeeInfineon Technologies AP+65 68400448
S.W. Ricky LeeHong Kong Univ. of Science &Tech.+852 2358 7203
Jong-Kai LinMotorola, Inc.(480) 413-3254
Goran MatjasevicUniversity of California, Irvine(949) 824-9830
Lei L. MercadoIntel Corporation(480) 552-1383
Dennis OlsenConsultant(480) 994-9926
Kanji OtsukaMeisei University+81 428 25 5214
Senol PekinLSI Logic(408) 433-8210
Matt SchwiebertAglient Technologies, Inc.(408) 553-2385
Paul A.TottaIBM Corporation(845) 297-7982
ManufacturingTechnologyTom Swirbel, ChairMotorola, Inc.(954) 723-5671
Tom Poulin, CochairAerie Engineering(909) 248-1237
Sharad BhattShanta Systems, Inc.(814) 362-6996
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Peter BlackUS Army Aviation & MissileCommand(256) 876-3004
Douglas E. ChrzanowskiIBM Corporation(607) 755-1403
David KeezerGeorgia Institute of Technology(404) 894-4741
Claude LadouceurIBM Canada, Ltd.(450) 534-7314
Sylvain OuimetIBM Canada, Ltd.(450) 534-6690
Kitty PearsallIBM Corporation(512) 838-7215
Jerzy ZalesinskiIBM Corporation(802) 769-6648
Materials & ProcessingChin C. Lee, ChairUniversity of California, Irvine(949) 824-7462
Ceferino Gonzalez, CochairDuPont Advanced Fibers Systems(919) 248-5062
Y. C. ChanCity University of Hong Kong+852 3 2788 7130
Rajen ChanchaniSandia National Laboratories(505) 844-3482
Phil GarrouDOW at MCNC(919) 248-9261
Chandra JayaramIntel Products (M) Sdn. Bhd.+604 408 2240
Vaidyanathan KripeshInstitute of Microelectronics +65 6770 5592
Ning-Cheng LeeIndium Corporation of America(315) 853-4900
Yeong LeeDow Corning(989) 496-7032
Ming LiChinese University of Hong Kong+852 31634129
Johan LiuChalmers University of Technology+46 31 706 6294
Jim MorrisPortland State University(503) 725-9588
Kyung-Wook PaikKorean Advance Institute ofScience+82 42 869 3335
Eric PerfectoIBM Microelectronics(845) 894-4400
Quinn TongNational Starch & ChemicalCompany(908) 685-5227
C. P. WongGeorgia Institute of Technology(404) 894-8391
Modeling & SimulationSuresh K. Sitaraman, ChairGeorgia Institute of Technology(404) 894-3405
Michael Lamson, CochairTexas Instruments, Inc.(972) 995-2490
W. Scott BurtonAgilent Technologies, Inc.(970) 288-1186
Andreas CangellarisUniversity of Illinois at Irbana-Champaign(217) 333-6037
Moises CasesIBM Corporation(512) 838-6225
Steve DvorakUniversity of Arizona(520) 621-6170
L. J. ErnstDelft University of Technology+31 15 278 6519
George A. KatopisIBM Corporation(914) 435-6719
Ravi KawAglient Technologies, Inc.(408) 345-8893
Bruce KimArizona State University(480) 965-3749
J. Peter KrusiusCornell University(607) 255-3401
Pradeep LallAuburn University(334) 844-3424
Erdogan MadenciUniversity of Arizona(520) 621-6113
Tony MakDallas Semiconductor Corporation(972) 371-4364
John L. PrinceUniversity of Arizona(520) 621-6187
Madhavan SwaminathanGeorgia Institute of Technology(404) 894-3340
G. Q. Kouchi ZhangPhilips+31 40 273 3825
OptoelectronicsJames E.Watson, Chair3M Center(651) 733-3890
Torsten Wipiejewski, CochairNorth AmericaAgility Communications (805) 690-1781
Yasuhiro Ando, Cochair,AsiaFujikura Ltd.+81 3 5606 1203
Sue Law, Cochairman,AustraliaAustralian Photonics CooperativeResearch Center+612 9351 1960
Martin Groeneveld, Cochair, EuropeJDS Uniphase+31 40 2578736
Mario DagenaisQuantim Photonics(240) 456-7101
Mino F. Dautartas(540) 953-2160
Jon HallBookham+44 132 735 6737
Randy HeylerNewport Corporation(949) 862-3465
Werner HunzikerOpto Speed AG+41 17046262
Masataka ItoOptobahn Corporation(310) 768-2900
Harry G. KellziTeledyne Electronic Technologies(310) 574-2097
Michael LebbyIgnis Optics, Inc.(408) 896-8484
Graeme [email protected]
Alan J. MorrowBinOptics Corporation(607) 257-3200 X236
Bill RingTyco Electronics(908) 704-6605
Ronald E. ScottiConsultant(408) 534-2039
Andrew ShaprioUniversity of California, Irvine(949) 824-8086
Dariusz SieniawskiAchray Photonics(613) 823-2211
Ephraim SuhirUniversity of Illinois at Chicago(650) 969-1530
Atsushi TakaiHitachi, Ltd.+81 45 865 7003
Chris TheisAgere Systems(484) 397-2964
Jean TrewhellaIBM TJ Watson Research Center(914) 945-2786
Ping ZhouGeneral Optoelectronic Devices,Inc.(818) 735-7823
PosterMichael Caggiano, ChairRutgers University(732) 445-0678
Swapan Bhattacharya, CochairGeorgia Institute of Technology(404) 385-0708
Quality & ReliabilityCharles Zhang, ChairIntel Corporation(480) 552-0453
Darvin R. Edwards, CochairTexas Instruments, Inc.(972) 995-3569
Jo CaersPhilips Electronics Singapore PteLtd.+65 6357 9370
Sridhar CanumallaNokia Mobile Phones(469) 767-9808
Harry K. CharlesThe Johns Hopkins University APL(443) 778-8050
George HarmanNIST(301) 975-2097
Xiaoling HeUniversity of Wisconsin, Milwaukee(414) 229-6772
Robert HowardRTH & Associates(802) 863-4600
Donna [email protected]
John H. L. PangNanyang Technological University+65 6790 5514
Andreas SchubertFraunhofer Institute for Relliabilityand Microintegration (IZM) Berlin+49 30 46403 134
Ephraim SuhirUniversity of Illinois at Chicago(650) 969-1530
Patrick ThompsonTexas Instruments, Inc.(972) 995-7660
Dongji XieFlextronics International(408) 576-7597
ProfessionalDevelopment CoursesRonald Scotti, ChairConsultant(908) 534-2039
Albert F. Puttlitz, CochairMechanical Eng. Consultant(802) 899-4692
Rao BondaMotorola, Inc.(480) 413-6121
The Sheraton New Orleans Hotel is in the heart of New Orleans. Just cross Canal Street and explore the French Quarter.The hotelis overlooking the Mississippi River and within walking distance of Riverwalk Marketplace, the Aquarium of the Americas, the IMAXTheater, and all the best food in the world. Make sure you have an umbrella for those late afternoon showers while you are takingthose sightseeing trips.
As you take that early morning walk to see New Orleans, listen for the steamboat whistle, smell the aroma of fresh bread and pas-tries in the air and admire the New Orleans architec-ture.“Uptown,” the city’s largest historic district, hasalmost 11,000 buildings and 82 percent of themwere built before 1935.The New Orleans architec-tural character is unlike no other city.
While you are in New Orleans ride the railway sys-tem that is over 150 years old. Ride on an historicstreetcar and see the beautiful mansions, homes andgardens that make New Orleans the city to see.
Area Attractions
Photographs courtesy of New Orleans Metropolitan Convention and Visitors Bureau, Inc.8
Audubon Park Fountain
French Quarter
Nottoway Plantation Home
Bourbon Street
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May 27, 2003Morning Professional
Development Courses8:15 AM - 12:00 PM
1. RF/Wireless Packaging: Part 1 - Fundamentals, Principles and Current Challenges
2. Polymers for Electronic Packaging:Materials, Process and Reliability - Part 1:The Fundamentals of Packaging and Materials Science and Engineering
3. Optoelectronics Components and Modules for Communication Networks
4. System-On-Package (SOP) System-In-Package (SIP), and System-On-Chip (SOC): New Paradigms in Electronics
5. Advanced Organic Substrate Package Design & Manufacturing for RF and Broadband Applications
6. Microelectronics Packaging and Interconnection - A Worldwide Perspective
7. Integrated Passive Technology
May 27, 2003Afternoon ProfessionalDevelopment Courses
1:15 PM - 5:00 PM8. Photonics Packaging: Physical
Design for Reliability9. RF/Wireless Packaging Part 2:
State-of-the-Art and Future Challenges
10. Polymers for Electronic Packaging Part 2: Recent Advances on Materials and Processes
11. Active Optical Components12. Wafer Level-Chip Scale13. Microvias & Chip Scale Packages for
Low-Cost High-Density Interconnects
14. Packaging Challenges for 10Gb/s and 40Gb/s Systems
May 27, 2003International Academic
Workshop8:15 AM - 5:00 PM
Technical SessionsMay 28, 2003
8:00 AM - 11:40 AMS1 Leading Edge Packaging TechnologyS2 Pb-Free Interconnections IS3 Quality and Reliability Issues of
Portable ProductsS4 High-Density Substrates and
Embedded ComponentsS5 Leaded and Lead-Free Solder
Characterization and ModelingS6 Application of Statistical Tools
in Manufacturing for In-process Control,Test and Product Cycle
May 28, 20031:30 PM - 5:10 PM
S7 Optoelectronic ModulesS8 Experimental Assessment of Quality
and ReliabilityS9 MEMS, Sensors and MicrostructuresS10 Thermal and Thermo-Mechanical
ModelingS11 RF Modules and PerformanceS12 Novel Packaging Education Programs
May 29, 20038:00 AM - 11:40 AM
S13 Flip Chip PackagingS14 Analytical Assessment of ReliabilityS15 MEMsS16 Pb-Free SoldersS17 New Materials and Interface
Delamination Modeling and Experiments
S18 Multimedia Packaging Education
May 29, 20031:30 PM - 5:10 PM
S19 Devices for Wavelength Division Multiplexing
S20 Pb-Free Interconnections IIS21 Wafer Level and Chip Scale PackagingS22 Advances in Test MethodsS23 Underfills for Flip ChipS24 Electrical Modeling
May 30, 20038:00 AM - 11:40 AM
S25 Optical Backplane and Parallel Interconnects
S26 3D Packaging TechnologiesS27 Novel InterconnectionsS28 Reliability Issues in Polymers and
Interfaces
S29 Interconnect MetallurgiesS30 Electrical Characterization and
Validation
May 30, 20031:30 PM - 5:10 PM
S31 Low-Cost Manufacturing of Optoelectronics
S32 Wire BondingS33 AdhesivesS34 System Design Electrical IssuesS35 Advancements in Wafer Thinning,
Bumping and Interconnect in Support of Wafer Level Packaging Manufacturing
S36 Component Technology
May 28, 20031:30 PM - 6:00 PM
S37 Poster Session 1
May 29, 20031:30 PM - 6:00 PM
S38 Poster Session 2
May 29, 20021:30 PM - 6:00 PM
Technology Corner Exhibits
May 30, 20029:00 AM - 12:00 PM1:30 PM - 6:00 PM
Technology Corner Exhibits
Conference Overview
Session Summary byInterest AreaAdvanced Packaging
S1, 9, 13, 21, 26Components & RF
S11, 36Package Education
S12, 18Interconnections
S2, 15, 20, 27, 32Manufacturing Technology
S6, 35Materials & Processing
S4, 16, 23, 29, 33Modeling & Simulation
S5, 10, 17, 24, 30, 34Optoelectronics
S7, 19, 25, 31PosterS37, 38
Quality & ReliabilityS3, 8, 14, 22, 28
Professional DevelopmentCourses
May 27, 2003
Ronald E. Scotti, ChairConsultantPhone: (908) 534-2039Email: [email protected]
Albert F. Puttlitz, CochairConsultantPhone: (802) 899-4692Fax: (802) 899-4692Email: [email protected]
MORNING COURSES8:15 AM - 12:00 PM
1. RF/WIRELESS PACKAGING:PART 1 — FUNDAMENTALS,PRINCIPLES,AND CURRENT
CHALLENGESInstructors: Joy Laskar and
Emmanouil (Manos) M.TentzerisGeorgia Institute of Technology
Course Objectives:Review the fundamentals of RF/WirelessPackaging definitions and mechanisms.Discuss the use of S-parameters and thenature of parasitic coupling, radiation andloss factors in common packaging geome-tries. Present the principles in the design ofembedded passives and the basic evaluationparameters (effective value, quality factor).
Course Outline:• Practical RF transmission lines
and impedance matching • Scattering (S) parameters • Fundamental crosstalk and
radiation definitions • Quality (Q) factor and loss
mechanisms in embeddedpassives
• General overview of full-wave simulation tools (e.g. FDTD)
Who Should Attend:Engineers and technical managers whowould like to get familiar with the chal-lenges, fundamental definitions and prob-lems encountered in RF/Wireless Packaging.
2. POLYMERS FOR ELECTRONICPACKAGING: MATERIALS,
PROCESS AND RELIABILITY PART 1:The Fundamentals of Packaging andMaterials Science and Engineering
Instructor: C. P. WongGeorgia Institute of Technology
Course Objectives:Polymers are widely used in electronicpackaging as adhesives, encapsulants, insula-tors, dielectrics, molding compounds andconducting elements for interconnects.These materials also play a critical role inthe recent advances of low-cost, high per-formance multi-chip module (MCM), chip-on-board (COB), ball grid array (BGA), flipchip (FC), novel no flow underfills, chip scalepackaging (CSP), paper-thin, 3D packagingand reliability without hermiticity (RWOH),plastic packaging and nano-functional mate-rials. It is imperative that material suppliers,formulators and their users have a thor-ough understanding of polymeric materialsand their importance in the advances of theelectronic packaging and interconnect tech-nologies.
Course Outline:• Overview electronic packaging
present and future trends • Fundamentals of polymers and
their physical and mechanical properties and measurements
• IC device interconnection & packaging technology - wire-bond,TAB, flip chip, polymer interconnects - current and future trends
• Purpose of pre-encapsulation cleaning, encapsulation and packaging - conventional cleaning, reactive oxygen and hydrogen cleaning processes
• Overview of inorganic and organic polymers for electronic packaging - Silicon dioxides, nitrides &
oxynitrides - Epoxies, silicones, polyimides,
silicone-polyimides,polyurethanes,benzocyclobutenes,parylenes, BT resins,sycars, polyesters, high temperature & liquid-crystal polymers, low k, low loss and nano-functional and-foam materials
Who Should Attend:Engineers, scientists and managers involvedin the design, process and manufacturing ofIC electronic components and hybrid pack-aging, and electronic material suppliersinvolved in materials manufacturing andresearch & development.
3. OPTOELECTRONICS COMPONENTS AND MODULES
FOR COMMUNICATION NETWORKS
Instructor: Bill Ring Tycoelectronics
Course Objectives:Optoelectronics components and modulesfor the communications industry and net-works are continuously advancing in termsof speed, lower cost and design for high vol-ume manufacture. The objectives of thiscourse are to provide a background on thecurrent industry active components andpackaging approaches and review the direc-tion of active devices and packaging tech-nology for discrete components and datanetwork modules. The course will coverthe fundamentals of active III-V devices,manufacturing of components and trans-ceivers for the communications industry.
Course Outline:• Overview of communication
requirements• Semiconductor devices for active
communications devices- InP-based structures- GaAs-based structures
• Packaging technology for communication components- Butterfly assembly- Lead frame assembly- TO-can assembly- Silicon optical bench
technology• Modules for Datacom
- 1x9 SC Duplex- Through-hole small form
factor - Hot pluggable SFP trans-
ceivers- Parallel module technology- 10Gb Ethernet modules
• Future trends
Who Should Attend:This course is intended for engineers andmanagers who are involved in the design ofcomponents and modules for communica-tion networks. It will be beneficial for thosewho require a fundamental understandingand broad perspective on active compo-nents for LAN, SAN OI connection andtelecom modules, specifically technology,and manufacturing issues.
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IMPORTANT NOTICEIt is extremely important to register
in advance to prevent delays atdoor registration. Course sizes
are limited.
4. SYSTEM-ON-PACKAGE (SOP),SYSTEM-IN-PACKAGE (SIP),AND
SYSTEM-ON-CHIP (SOC):New Paradigms in Electronics
Course Leaders: Rao R.Tummala andDaniel Guidotti
Georgia Institute of Technology
Course Objectives:This course is an overview course based onthe Georgia Institute of TechnologyPackaging Research Center’s (PRC’s)System on Package (SOP) vision for highlyintegrated and convergent consumer, com-puter and telecom systems with not onlydigital functions, but also analog, RF, opticaland MEMS.The SOP paradigm changes thecurrent chip-centric SOC methodology to acheaper and faster-to-market, package-cen-tric microsystem packaging design and tech-nology flow. The advantages of the SOPparadigm over the System-on-Chip (SOC)paradigm beyond the year 2007, when IClithography becomes highly resistive andexpensive, appear overwhelming due todesign simplicity, lower cost, and higherelectrical performance, without the intellec-tual property issues that dominate SOC.Torealize these enormous advantages newtechnology paradigms are required.Theseinclude mixed signal design and test, ultrahigh-density wiring, embedded optoelec-tronics, passive and RF component integra-tion, wafer level packaging (WLP) andassembly, testing and burn-in before dicing,and thermal management and system relia-bility. A key technology paradigm, whichGeorgia Tech has been developing with theNational University of Singapore, is the con-cept of WLP, testing and burn-in, whichpromises ultimate size miniaturization, andvirtually unlimited interconnections at nanoscales. In an overview fashion, this coursemakes a compelling case for and presentsthe status of SOP, SIC, SOC and WLP tech-nologies in forming high performance, inte-grated and convergent systems of thefuture.
Course Outline:• System trends to convergent
systems • Semiconductor trends to SOC • Fundamental and engineering
limits of SOC • IC packaging toward SIP• What is SOP? And why?• SOP = SOC + SIP + Wafer level
assembly + Multifunction Board • Global developments of SOP • SOP technology reviews in
- Design - Fabrication, integration with
RF, Optical, Digital- Wafer level packaging - Cooling
- Assembly- Burn-in and test- Reliability
• What next after SOP? - Nano packaging- Nano systems
Who Should Attend:This course is an overview course and issuitable for all levels of R & D managers,senior engineers and executives involved intechnical strategy, R&D, design, manufactur-ing, process and product development ofelectronic packaging systems and productsin automotive, telecommunications, comput-ers, consumer, medical, and aerospace products.
5. ADVANCED ORGANICSUBSTRATE PACKAGE DESIGN &MANUFACTURING FOR RF AND
BROADBAND APPLICATIONSInstructor: Hassan Hashemi
Mindspeed Technologies,A ConexantBusiness
Course Description:The objectives of this course are to reviewdesign and manufacturing practices andtradeoffs affecting current and next genera-tion Wireless and Broadband IC Packagingusing laminate substrate technologies in sin-gle or multiple die format.The course mate-rial is based upon the instructor’sexperience in current practices used forWireless & GHz IC packaging for commer-cial wireless (e.g. Power Amplifier modules)and networking and storage infrastructureapplications.
Course Outline:• Review design and manufactur-
ing practices and tradeoffs affecting current and next gen-eration RF & GHz packaging using laminate substrate tech-nologies in single or multiple die packaging formats.- Ceramic versus laminate
substrate based packaging- RF laminate packages
designed to use chip-on-board and surface mount technologies
- RF laminate package design issues with emphasis on design for high volume man-ufacturing
- Package electrical, thermal,and mechanical modeling in support of design verification and process development
• Review laminate package mate-rials, processes, cost analysis,and manufacturing issues
• Discuss quality and reliability concerns with RF laminate package
• Review surface mounting and chip & wire assembly manu- facturing Issues and challenges- Manufacturing tolerances
and their effects on con-trolled impedance lines & transitions
- Conclusions
Who Should Attend:The course is designed for engineers orengineering managers who want to under-stand more about laminate modules, andthe unique requirements for assuring thatpackages can be manufactured in a high vol-ume commercial application and meet strin-gent electrical and thermal performancerequirements.
6. MICROELECTRONICS PACKAG-ING AND INTERCONNECTION - A WORLDWIDE PERSPECTIVE
Instructor: E. Jan VardamanTechSearch International, Inc.
Course Objectives:This course will present delegates an updat-ed and broad perspective of the latestdevelopments in microelectronics packagingand interconnect technology. The focus ofthe course is area array packages such asball grid array (BGA), chip scale packaging(CSP), and flip chip (FC). CSPs includewafer level packages. The course willemphasize drivers for package use and highvolume applications.
Course Outline:• Overview and trends in micro-
electronics packaging and inter-connect technology
• BGA - definition, package construc-tions, major volume applications by package type, new developments by package type, and new develop-ments especially in high-perform-ance packaging
• CSP - definition, package con-structions, major volume appli-cations by package type,new developments by package type, and new developments including wafer-level packages
• Flip chip related technologies - definition, flip chip in-package (FCIP) and flip chip on board (FCOB) applications, drivers for expansion, and future trends
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In addition, samples of packages/substrates/modules will be used during this course toillustrate the topics described above.Photosof products using advanced packages will alsobe included in this seminar.
Who Should Attend:This course will be beneficial to all man-agers and individual contributors from theelectronic industry who need fundamentalunderstanding and broad perspective onmicroelectronics packaging and intercon-nect technology, especially in technologytrends and key developmental areas such asBGA, CSP, and flip chip.
7. INTEGRATED PASSIVETECHNOLOGY
Instructor: Dr. Richard UlrichDept. of Chemical Engineering,
University of Arkansas
Course Objectives:This course will be a comprehensive reviewof potential applications, commercializedtechnology, and possible future directions inintegrated passive components and process-ing for organic boards. The organization ofthe course centers on the benefits andproblems with their implementation inorder to help potential users make deci-sions about their applicability in a given situ-ation. Considerable time will also be spenton the candidate materials and processesfor integrated resistors, capacitors andinductors in order to help the potentialuser decide what processes can provide theneeded electrical performance while beingcompatible with their existing substratesand fabrication technology. Emphasis willalso be placed on electrical testing, sinceusers of integrated passives will find them-selves in the business of producing passivecomponents, not just buying them, since theelectrical performance characteristics ofintegrated passives can be very differentfrom their surface-mount counterparts,possibly providing significant competitiveadvantages. Several current potential appli-cations will be described, with particularemphasis on decoupling.
The course emphasizes applicability to man-ufactured microelectronic systems andincludes theoretical material necessary tosupport that purpose.
Course Outline:• Why use IPs?• Substrates of interest • Integrated resistors• Integrated capacitors• Integrated inductors
• Electrical measurement of integrated passives
• Applications favorable for integrated passives
• Economics of IPs• Tolerance, repeatability and
yield issues• Commercialized systems• Where are integrated passives
going?
Who Should Attend:Engineers and scientists involved in elec-tronics packaging, circuit board manufacture,electrical design and passive componenttechnologies.
AFTERNOON COURSES 1:15 PM - 5:00 PM
8. PHOTONICS PACKAGING:PHYSICAL DESIGN FOR
RELIABILITYInstructor: Ephraim Suhir, University
of Illinois at Chicago, Chicago, IL., USA
Course Objectives:Some major problems, challenges, attributesand pitfalls in physical design and reliabilityof photonic (opto-electronic) packages areaddressed, with an emphasis on the roleand use of predictive modeling. Numerouspractical examples are examined, and rec-ommendations for materials selection andimproved reliability are given.The courseanticipates active interaction of the atten-dees with the instructor.
Course Outline:• The future of photonics, and
the role of packaging, materials and reliability engineering
• Predictive modeling, its role, merits,shortcomings, and interaction with experiment
• Adhesively bonded and soldered assemblies subjected to thermal loading; bow-free assemblies;interaction of “local” and “global” thermal expansion (contraction) mismatch
• Solder joints in thermally mismatched and matched assemblies
• Thin film assemblies• Fiber optics interconnects (bare,
polymer coated, metallized),subjected to thermal and/or mechanical loading: design for reliability
• Fibers for long haul communications• Dynamic response of photonics
structures to shocks and vibrations
• Accelerated life testing in photonics packaging: its objectives, role,attributes, pitfalls, predictive models and interaction with qualification tests
• Probabilistic approach in physical design of photonics packages
Who Should Attend:Engineers and technical managers whowould like to get familiar with the mechani-cal, materials and reliability problemsencountered in photonics packaging.
9.RF/WIRELESS PACKAGING PART 2:State-of-the-Art andFuture Challenges
Instructors: Joy Laskar andEmmanouil (Manos) M.TentzerisGeorgia Institute of Technology
Course Objectives:Review the latest developments in the areaof next generation RF/ microwave packag-ing. Investigate different materials andtopologies. Present integrated solutions forwireless transceivers incorporating packag-ing adaptive antennas. Discuss possible solu-tions for RF-MEMS packaging problems.Provide easy-to-use design rules using CADtools.
Course Outline:• Vertical interconnects (flip chip,
BGA, PGA) • Embedded components in organics
and ceramics (LTCC) materials • Packaging adaptive antennas • Integrated wireless transceivers • RF-MEMS • Practical designs using modeling
CAD tools
Who Should Attend:Engineers and technical managers whowould like to get familiar with the chal-lenges and problems encountered inRF/Wireless packaging.
10. POLYMERS FOR ELECTRONICPACKAGING PART 2:
Recent Advances on Materials and Process
Instructor: C. P. WongGeorgia Institute of Technology
Course Objectives:Polymers are widely used in electronicpackaging as adhesives, encapsulants, insula-tors, dielectrics, molding compounds andconducting elements for interconnects.
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These materials also play a critical role inthe recent advances of low-cost, high per-formance novel no flow underfills, rework-able underfills for ball grid array (BGA), chipscale packaging (CSP), system on a package(SOP), direct chip attach (DCA), flip chip(FC), paper-thin IC and 3D packaging, con-ductive adhesives (both ICA and ACA),embedded passives and nano-functionalmaterials. It is imperative that material sup-pliers, formulators and their users have athorough understanding of polymeric mate-rials and their importance in the advancesof the electronic packaging and intercon-nect technologies.
Course Outline:• Overview of semiconductor
packaging technology • Next generation of electronic
packaging • Common electronic packaging
materials: conformal coating,glob-top, potting and casting
• Novel no flow, advanced and reworkable underfills for flip chip applications
• Conductive adhesives for lead-free interconnects – fundamentals and recent advances
• Low-cost high-performance embedded passives materials and processes
• Recent advances on low dielectric (k) materials and nano-functional materials
Who Should Attend:Engineers, scientists and managers involvedin the design, process and manufacturing ofIC electronic components and hybrid pack-aging, electronic material suppliers involvedin materials manufacturing and research &development.
11.ACTIVE OPTICALCOMPONENTS
Instructor: Torsten WipiejewskiAgility Communications, Inc.
Course Objectives:Active optical components are key ele-ments in modern high-speed optical trans-mission systems. The objective of thiscourse is to give an overview of the variousactive optical components employed in ageneric optical transmission system. Theaudience should be able to understand theunderlying physical principle of these com-ponents. Rather than describing exhaustivelytechnical details of a specific component thephysical limitations will be explained. Anunderstanding should be created about why
certain components are chosen. Futuredevelopments of photonic devices will bediscussed.
Course Outline:• Introduction: modern optical
transmission systems • Laser diodes: basic design and
operation- Optical gain in semiconductors- Fabry-Perot laser diodes
(structure and fabrication,performance)
- Distributed Feedback (DFB) lasers (properties and appli-cations)
- Vertical-cavity surface-emit-ting lasers (VCSELs)
- Tunable lasers (tuning scheme, applications)
- Comparison of different light sources for optical communi-cation
• Modulators: different types and speed limitations- Mach-Zehnder modulator- Electro-absorption modula-
tor (chirp performance)• Photodetectors: the receiving
side of a transmission system- PIN photodiodes (bandwidth
limitation)- Avalanche photodiodes
(gain and noise perform-ance)
- Other concepts: MSM pho-todetectors, traveling wave photodetectors, heterodyne detection
• Integration: technical chal-lenges and economic boundary conditions - Types of integration and lim-
itations- Laser diode and electro-
absorption modulator
Who Should Attend:Engineers and technical managers who wantto gain a fundamental understanding of thecharacteristics and limitations of the variousactive optical components used in modernoptical transmission systems.
12.WAFER LEVEL-CHIP SCALEPACKAGING
Instructor: Luu NguyenNational Semiconductor Corporation
Course Objectives:Wafer level-chip scale packaging (WL-CSP)has gained momentum in the small chiparena lately, driven by needs for cost reduc-tion, form factor shrinkage, and enhancedperformance. This course will provide anoverview of the WL-CSP technology. Themarket drivers, benefits, and challenges fac-ing industry-wide adoption will be dis-cussed. The current WL-CSP configurationswill be reviewed in terms of their construc-tion, manufacturing process, and publishedelectrical/thermal performance, togetherwith package and board level reliability.Since the technology marks the conver-gence of fab, assembly, and test, discussionwill also address some fundamental issuessuch as:
• Where would it fit best (front end or back end)?
• Will it be applicable and cost-effective for complex devices such as microprocessors?
• Are current standards (design rules, outline, reliability, etc.) applicable?
Course Outline:• Wafer level-chip scale packag-
ing (WL-CSP) – definition• Market drivers for WL-CSPs• Benefits of WL-CSPs• Barriers and challenges for WL-
CSPs• Review of current WL-CSPs in
the industry• Wafer level testing – status and
challenges• Infrastructure service providers• Future trends: lead-free, large
die size, wafer level underfill
Who Should Attend:The course will be useful to the followingthree groups of engineers and scientists: 1.Newcomers to the field who would like toobtain a general overview of WL-CSP; 2.Those who are already practicing researchand development of IC packaging andwould like to learn new methods for solvingCSP problems; and, 3. Those who are cur-rently considering WL-CSP as a potentialCSP alternative for their interconnect sys-tems.
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13. MICROVIAS & CHIP SCALEPACKAGES FOR LOW-COST HIGH
DENSITY INTERCONNECTSInstructor: Ricky Lee, Ph.D.
Electronic Packaging Laboratory,HKUST
Course Objectives:This course will introduce the cutting-edgeinformation on the most important devel-opment and latest research results in apply-ing chip scale packaging and microviatechnologies to substrate/PCB level assem-blies. For professionals active in microelec-tronic packaging research and development,those who wish to master high densityinterconnect technologies, and those whoneed to choose a cost effective design andhigh-yield manufacturing process for theirelectronic systems, this is a timely summaryof progress in all aspects of this fascinatingfield. The lecture contents are based on theinstructor’s books on electronic packaging,his recent research results, and interactionswith the packaging and assembly industries.The scope of course covers flip chip andCSP technologies, wafer-level packaging,microvias and build-up substrates, emerginghigh-density interconnect technologies, andboard-level solder joint reliability. With theinformation provided in this lecture, theattendees will acquire a practical under-standing in the design, materials, processes,equipment, analysis, and reliability issues oflow-cost and high-density interconnectiontechnologies.
Course Outline:• Overview of area array and high
density interconnect technologies• Solder-bumped flip chip & wafer
level chip scale packages (WLCSP)• Microvias by mechanical and
laser drilling• Microvias by photo-imaging
and etching• Conductive paste/ink-filled
microvias• Special high-density interconnects
for flip chip applications• PCB/substrate with sequential
build-up layers• Solder joint reliability of flip chip and
WLCSP on build-up PCB/substrate with microvias
Who Should Attend:This short course is intended for researchscientists, professional engineers and techni-cal managers who are involved in IC pack-aging, component assembly, materials andprocessing, contract manufacturing and mar-keting.
14. PACKAGING CHALLENGESFOR 10GB/S AND 40GB/S SYSTEMS
Instructors: Roberto Coccioli, InphiCorporation and Hassan Hashemi,
Mindspeed Technologies,A ConexantBusiness
Course Description:The objectives of this course are to reviewchallenges in 10G and 40G IC packagingconsidering requirements posed by mixedIC technologies and system architecture.Moreover, it is intended to review the tech-nologies available to realize package andboard interconnects assessing their relativeperformance and their impact on signalintegrity on high speed digital signaling.Thecourse material is based upon the instruc-tors’ experience on current practices usedfor GHz IC packaging for telecom and data-com infrastructure applications.
Course Outline:• Review of requirements for 10G
and 40G interconnect technologies posed by mixed IC technologies andsystem architecture
• Substrate technologies for 10Gb/s and 40Gb/s applications- Ceramic- Thick-film, thin-film,
HTCC, LTCC, etched thick film
- Organic- PTFE glass fiber, PTFE
ceramic• Effects of interconnects on
signal integrity- Wirebonds vs. flip chip - Transmission lines: CPW,
Microstrip, Stripline• 10Gbps and 40Gbps IC package
examples• Connectorized packages for
10 and 40Gbps ICs- Connector types- Threaded, push-on
• Assembly and backside design • Examples• Issues and challenges
- Manufacturing tolerances and their effects
- Controlled impedance lines - Transitions
• Conclusions
Who Should Attend:The course is designed for engineers orengineering managers who want to under-stand more about technical challenges ofhigh-speed packaging, and the uniquerequirements posed on technology selec-tion and design to assure the achievementof stringent electrical and thermal perform-ance in cost-performance efficient manufac-turing.
Continuing EducationUnits
The IEEE Components, Packaging andManufacturing Technology Society(CPMT) has been authorized to offerContinuing Education Units (CEUs)by the International Association forContinuing Education and Training(IACET) for all Short Courses thatwill be presented at the 53rd ECTC.CEUs are recognized by employersfor continuing professional develop-ment as a formal measure of partici-pation and attendance in non-creditself-study courses, tutorials, symposiaand workshops. IEEE CPMT CEUs canbe applied towards the newly createdIEEE CPMT ProfessionalDevelopment Certificate. Completedetails including voluntary enrollmentforms will be available at the confer-ence. All costs associated with ECTCShort Courses CEUs will be under-written by the conference, i.e. thereare no additional costs for ShortCourses attendees to obtain CEUcredit.
IMPORTANT NOTICEA.M. Short Courses 1 through 7 or
P.M. Short Courses 8 through 14 runconcurrently. Make sure you indicatespecific course numbers you plan toattend on page 31. The cost of eachsession (A.M. or P.M.) is $325. If youplan to attend both A.M. and P.M.
courses, registration for all-day is $525.The student all-day course registration
fee is $50.
Wednesday, May 28Session 1: Leading Edge PackagingTechnology8:00 a.m. - 11:40 a.m.Committee:Advanced Packaging
Session Co-Chairs:Joseph W. Soucy – Draper LaboratoryTel: +1-617-258-2953Fax: +1-617-258-1779Email: [email protected]
Sudipta K. Ray – IBM MicroelectronicsTel: +1-845-894-6240 Fax: +1-845-892-6799Email: [email protected]
Wiring Optimization for Propagation Delayand Power Consumption of MultichipModules with Free-Space OpticalInterconnectChung-Seok Seo,Abhijit Chatterjee, and TimothyJ. Drabik – Georgia Institute of Technology
Advanced Packaging Solution of OC-768, 40Gb/s Utilizing IBM Standard Alumina MLCTechnologyWarren Dyckman and Edward Pillai – IBMCorporation
Electrical Repair of MLC SubstratesJon Casey, Brian Sundlof,Thomas Wassick,Richard Surprenant, Herb Stoller, Harvey Hamel,Kathy Wiley, Jerome Cohen, Michael Berger, andDonald Scheider – IBM Corporation
High-Performance Flex Two-Layer SubstrateUsing the Interconnected Mesh PowerSystem (IMPS)Leonard Schaper – University of Arkansas
Embedded IC Packaging Technology forUltra-thin and Highly Compact RF ModuleStephane Pinel, Sangwoong Yoon, Kyutae Lim, andJoy Laskar – Georgia Institute of Technology;Chang-Ho Lee – RF Solution
Constrained-Sintered, Low-TemperatureCofired Ceramic for Interconnect and ICPackaging ApplicationsChristopher Needes, Carl Wang, Michael Barker,Patricia Ollivier, Kenneth Hang,Yong Cho, andKenneth Souders – DuPont Company
Advances in LTCC for IncreasingMicroelectronic ApplicationsSteve Annas – Kyocera
Wednesday, May 28Session 2: Pb-Free Interconnections I8:00 a.m. - 11:40 a.m.Committee: Interconnections
Session Co-Chairs:Paul A.Totta – IBM (Retired)Tel: +1-845-297-7992 Fax: +1-845-297-7992Email: [email protected]
Sung K. Kang – IBM -TJ Watson RessearchCenterTel: +1-914-945-3932 Fax: +1-914-945-2141Email: [email protected]
Lead-free Solder Assembly: Impact andOpportunityEdwin Bradley – Motorola, Inc.
Lead-Free Solders: Issues of Toxicity,Availability, and Impacts of ExtractionJulie Schoenung – University of California, Davis;Anna Ku – SOMA Environmental Engineering,Inc.; Oladele Ogunseitan and Jean-DanielSaphores – University of California, Irvine;Andrew Shapiro – Jet Propulsion Laboratory
Creep Properties of Sn-Rich SoldersJohn Morris and Ho Geon Song – University ofCalifornia, Berkeley; Fay Hua – Intel Corporation
Pb-free Solder Challenges in ElectronicPackaging and AssembliesFay Hua – Intel Corporation
Formation of Ag3Sn Plates in Sn-Ag-Cu Alloysand Optimization of their Alloy CompositionSung Kang,Won Kyoung Choi, Da-Yuan Shih,Donald Henderson,Timothy Gosselin,AmitSarkhel, Charles Goldsmith, and Karl Puttlitz –IBM Corporation
Unique Phase Change Induced byElectromigration in Solder JointsK. N.Tu, Gu Xu, and Hua Gan – University ofCalifornia, Los Angeles
Package Level Reliability of Pb-free Bumpand Assembly ProcessesC. J. Berry, David McCann, Danny Brady, andPatrick Kim – Amkor Technology, Inc.
Wednesday, May 28Session 3: Quality and Reliability Issuesof Portable Products8:00 a.m. - 11:40 a.m.Committee: Quality & Reliability
Session Co-Chairs:Sridhar Canumalla – Nokia Mobile PhonesTel: +1-469-767-9808 Fax: +1-972-894-4988Email: [email protected]
Harry K. Charles – The Johns HopkinsUniversity APLTel: +1-443-778-8050 Fax: +1443-778-6119Email: [email protected]
Advanced Simulation Methodology for BoardLevel Fatigue Life Predictions of 3.0Sn37.0Pband 95.5Sn4.0Ag0.5Cu Solder Materials inMultiple Microelectronic Package StructuresBret Zahn – ChipPAC Inc.
Study of Microvia Failure under PWB FlexingLoadsKah Woon Seah, Chwee Teck Lim, and VincentTan – National University of Singapore; Siew EngQuah – Motorola Singapore
Modeling Technique for ReliabilityAssessment of Portable Electronic ProductSubject to Drop Impact LoadLiping Zhu – Sony Ericsson MobileCommunication, Inc.
Package to Board Interconnection ShearStrength (PBISS) Test Method forCharacterizing Interconnection QualitySridhar Canumalla, Hee Dong Yang, andPuligandla Viswanadham – Nokia Mobile Phones
Investigating The Board Level Response InPortable Electronic Products During DropImpactC.T. Lim, S. K.W. Seah,V. B. C.Tan, and V. P.W.Shim – National University of Singapore; E. H.Wong – Institute of Microelectronics (IME)
Board Level Drop Test and Simulation ofTFBGA Packages for TelecommunicationApplicationsTong Yan Tee and Hun Shen Ng –STMicroelectronics, Inc.; Chwee Teck Lim andEric Pek – National University of Singapore;Zhaowei Zhong – Nanyang TechnologicalUniversity
Solder Joint Behavior of Area Array Packagesin Board Level Drop for Handheld DevicesDongji Xie, Minna Arra, Sammy Yi, and DanRooney – Flextronics
Program Sessions
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Wednesday, May 28Session 4: High-Density Substrates andEmbedded Components8:00 a.m. - 11:40 a.m.Committee: Materials & Processing
Session Co-Chairs:Ceferino Gonzalez – DuPont AdvancedFibers SystemsTel: +1-919-248-5062 Fax: +1-919-248-5341Email: [email protected]
Yeong Lee – Dow CorningTel: +1-989-496-7032 Fax: +1-989-496-7084Email: [email protected]
Evaluation of Low Stress Dielectrics forBoard ApplicationsSwapan Bhattacharya, Swapn Bhattacharya, C. P.Wong, and Rao Tummala – Georgia Institute ofTechnology
Laser Processing of Polymer Layers ofLaminated and Flexible SubstratesZsolt Illyefalvi-Vitez, Richard Berenyi, PeterGordon, Zsolt Nyitrai, Janos Pinkola, and MiklosRuszinko – Budapest University of Technologyand Economics (BUTE)
In-situ Stress and Warpage Measurements toInvestigate Reliability of Flip Chip on BoardAssembly Without UnderfillShubhra Bansal, P Markondeya Raj, BhattacharyaSwapan, and Rao Tummala – Georgia Institute ofTechnology; Shinotani Ken-ichi – MatsushitaElectric Works; Michael Lance – OakridgeResearch National Laboratory
Quantitative Analysis of Resistance Variationsin As-Deposited Nickel-Phosphorus (NiP)Embedded ResistorsP. L. Cheng, S.Y.Y. Leung, C. K. Liu,T.W. Law, I.T.Chong, and D. C. C. Lam – Hong KongUniversity of Science and Technology
Process and Characterizations ofCrx(SiNy)1-x Thin Film Resistors forIntegrated Passive ApplicationFan Wu – Microelectronic Center, Medtronic,Inc.; James Morris – Portland State University
Integral Capacitor Dielectrics Based onPolymer Composites with SpecialtyConductive FillersLianhua Fan – Georgia Institute of Technology
Development of a Novel Aluminum-FilledComposite for Embedded PassiveApplicationsJianwen Xu and C. P.Wong – Georgia Institute ofTechnology
Wednesday, May 28Session 5: Leaded and Lead-Free SolderCharacterization and Modeling8:00 a.m. - 11:40 a.m.Committee: Modeling & Simulation
Session Co-Chairs:Pradeep Lall – Auburn UniversityTel: +1-334-844-3424 Fax: +1-334-844-3307Email: [email protected]
W.Scott Burton – Agilent Technologies, Inc.Tel: +1-970-288-1186 Fax: +1-970-288-3450Email: [email protected]
Field-Use Conditions vs.Thermal Cycles, APhysics-Based Mapping StudyKrishna Tunga, James Pyland, Raghuram Pucha,and Suresh Sitaraman – Georgia Institute ofTechnology
BGA Reliability in Automotive UnderhoodEnvironmentsPradeep Lall, Jeff Suhling, John Evans,WayneJohnson, and Nokib Islam – Auburn University
Microstructural Dependence of ConstitutiveProperties of Eutectic SnAg and SnAgCuSoldersSteffen Wiese and Ekkehard Meusel – DresdenUniversity of Technology
Reliability Assessment of a High-PerformanceFlip Chip BGA Package (organic substratebased) using Finite Element AnalysisDesmond Y.R. Chong, Rahul Kapoor, and AnthonyY.S. Sun – United Test & Assembly Center Ltd
Solder Joint Life Prediction Model Based onthe Strain Energy Density CriterionErdogan Madenci and Joshua Tor – University ofArizona
Finite Element Analysis to Develop a NewAccelerating Test Method for Board LevelSolder Joints for High TemperatureElectronicsWolfgang Neher and Wolfgang Kempe –DaimlerChrysler AG;Wilfried Sauer – DresdenUniversity of Technology
Constitutive Equations and Reliability ofLead-Free Solders and JointsJohn H. Lau – Agilent Technologies
Wednesday, May 28Session 6:Application of Statistical Toolsin Manufacturing for Inprocess Control,Test and Product Cycle8:00 a.m. - 11:40 a.m.Committee: ManufacturingTechnology
Session Co-Chairs:Sharad Bhatt – Shanta Systems Inc.Tel: +1-814-362-6996 Fax: +1-814-362-9933Email: [email protected]
Kitty Pearsall – IBM CorporationTel: +1-512-838-7215 Fax: +1-512-823-7544Email: [email protected]
In-Process Stress Characterization of FlipChip Assembly on Warped Organic SubstrateJian Zhang, Hai Ding, Daniel F. Baldwin, and I.Charles Ume – Georgia Institute of Technology
Flip Chip Assembly on PCB Substrates withCoined Solder BumpsJae-Woong Nah and Kyung W. Paik – KoreaAdvanced Institute of Science and Technology(KAIST); Soon-Jin Cho – SamsungElectro-Mechanics
Solder Shear Strength for Process ControlGlenn Rinne, Krishna Nair, and Nat Perkinson –Unitive, Inc.
Novel Algorithm For Fiber-Optic AlignmentAutomationRong Zhang – University of California, Irvine
Multiport Optical Filter Packages forDWDM ApplicationsHeinrich Muller, Paul Townley-Smith, and ScottHellman – Corning Inc.
Reducing RF Parameter Tests for Test CostReduction: Device Modeling, HypothesisTesting and Experiment VerificationMariette Awad, John Ferrario, and Jing Li – IBMMicroelectronics
Forecasting Supply Chain Components withTime Series AnalysisLara Martin and John Frei – Motorola, Inc.
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Wednesday, May 28Session 7: Optoelectronic Modules1:30 p.m. - 5:10 p.m.Committee: Optoelectronics
Session Co-Chairs:Mario Dagenais – Quantum PhotonicsTel: +1-240-456-7101 Fax: +1-240-456-7200Email: [email protected]
Dariusz Sieniawski – Achray PhotonicsTel: +1-613-823-2211 Fax: +1-613-823-1322Email: [email protected]
A Bi-Directional Single Fiber 1.25 Gb/sOptical Transceiver Module with SFPPackage using PLCToshikazu Hashimoto,Atsushi Kanda, RyoichiKasahara, Ikuo Ogawa,Yoshito Shuto, MasahiroYanagisawa,Akira Ohki, Shinji Mino, MotohayaIshii,Yasuhiro Suzuki, Ryo Nagase, and TakeshiKitagawa – Nippon Telegraph and TelephoneCorporation
High Reliability 2.5 Gbit/s Modules usingSilicon Platform TechnologyJean-Noël Reygrobellet, Patricia Volto,YvesHernandez, Philippe Berthier,Yannick Samson,Agnès Viala,André Coquelin,Alain Tournereau,Vincent Lecocq, Laurent Lièvre, and DominiqueLaffitte – Alcatel Optronics
Receptacle Transceiver Module using SilicaWaveguide for Bi-Directional Transmissionover a Single FiberNaoki Kimura, Koji Shinozaki, Naoki Kitamura,Yasuhiro Fukutomi,Yuji Minota, and HaruyasuAndo – NEC Corporation; Hideki Tanaka – NECEngineering Corporation;Atsushi Sato – NECYamanashi Corporation
Process Development for 10 Gb/s SmallFootprint Butterfly TransmitterDelin Li,Tieyu Zheng, Eric Zbinden, SivaYegnanarayanan, Jimmy Chen, Jeff Bennett, MarcFinot,Askew Emmett, Jay Walker, Hat Nguyen,Marc Epitaux, and Jean-Marc Verdiel – IntelCorporation
Design Optimization for 10Gbps ElectroAbsorption Modulator LD PackagingSudharsanam Krishnamachari, RamanaPamidigantham,Yeo Muiseng,Yiyi Ma, PinjalaDamaruganath, Mahadevan Iyer and Xie Ling –Institute of Micro-electronics (IME)
CPW Transmission Lines on SiliconSupporting 10G/40G InP EAM Chip onCarrier ApplicationsScott Pollard, Deepukumar Nair, KarenMatthews, Lawrence Hughes, Graeme Maxwell,and Peter Wigley – Corning Inc.; Songsheng Tan– Corning Intellisense Inc.
Thin Film Coolers for Localized TemperatureControl in Optoelectronic Integrated CircuitsYan Zhang, James Christofferson, DaryooshVashaee, Phuong Nguyen, and Ali Shakouri –University of California, Santa Cruz; GehongZeng, Chris Labounty,Yae Okuno, and John E.Bowers – University of California Santa Barbara
Wednesday, May 28Session 8: Experimental Assessment ofQuality and Reliability1:30 p.m. - 5:10 p.m.Committee: Quality & Reliability
Session Co-Chairs:George G. Harman – NISTTel: +1-301-975-2097 Fax: +1-301-948-4081Email: [email protected]
Dongji Xie – Flextronics InternationalTel: +1-408-576-7597 Fax: +1-408-576-7988Email: [email protected]
Lead Free Solders with High MechanicalReliabilityMasazumi Amagai – Texas Instruments, Inc.;Yoshitaka Toyoda – Senju Metal IndustryCompany
A Reliability Comparison of Lead Free andEutectic Solder for Stencil Printing Based Flip Chip ApplicationsEsther Yau, Jing Feng Gong, Fung Wa Hong, andPhilip C. H. Chan – Hong Kong University ofScience and Technology
Solder Joint Reliability of Lead-Free SolderBalls Assembled with SnPb Solder PasteHorst Theuss and Thomas Kilger – InfineonTechnologies
Copper Doped Eutectic Tin-Leas Bump ForPower Flip Chip ApplicationsShing Yeh – Delphi Delco Electronics
Board Level Reliability of Components withMatte Tin Lead FinishLuu Nguyen, Randall Walberg, Zhou Lin, andTerence Koh – National SemiconductorCorporation
Peel Test Metrology for Solder JointReliability of FCBGA PackagesJinlin Wang and Tom Miller – Intel Corporation;H. K. Lim, H. S. Lew,Woon Theng Saw, and ChewHong Tang – Intel Technology (M) Sdn. Bhd
Evaluation of Manufacturing AssemblyProcess Impact on Long Term Reliability of aHigh-Performance ASIC Using Flip ChipHyperBGATM PackageJie Xue, Ken Hubbard, Phillip Li, Jimmy Poon,Jennifer Tang and Mark Brillhart – Cisco Systems,Inc.; Dave Alcoe, Robert Kunz, and RandyStutzman – EIT; David Mendez – Solectron
Wednesday, May 28Session 9: MEMS, Sensors andMicrostructures1:30 p.m. - 5:10 p.m.Committee:Advanced Packaging
Session Co-Chairs:Karen W. Markus – JDS UniphaseTel: +1-919-806-4682 Fax: +1-919-806-4990Email: [email protected]
Tim Adams – Dow Corning Corp.Tel: +1-989-496-8867 Fax: +1-989-496-4586Email: [email protected]
Development of Transfer Molding Technologyfor Package with Die Active Side PartiallyExposedEric Kuah and Baozong Zhao – ASM technologySingapore;Tiao Zhou, Michael Hundt, andKum-Weng Loo – STMicroelectronics, Inc.
Packaging of a Electronic-MicrofluidicHybrid SensorErik Jung and Ralf Assmann – FraunhoferInstitute for Reliability and Microintegration IZM
A Mechanical Approach to Overcome RFMEMS Switch Stiction ProblemLei Mercado, Shun-Meen Kuo, and Tien-Yu TomLee – Motorola, Inc.
Gold Bump Attachment of MEM Sensor DieUsing Thermocompression BondingJoseph Soucy and Thomas Marinis – DraperLaboratory
Design and Development of a NewThermally Stable High Vacuum IR BolometerMEMS PackageC. S. Premachandran, Navas Khan OrattiKalandar, Xiaowu Zhang, and Chong Ser Choong– Institute of Microelectronics (IME)
Homogeneous Integration of Off the ShelfSi-Based ICs on a Si SubstrateMihaela Balseanu, Jon Duster, and KevinKornegay – Cornell University
Silicon Optical MicroBench Technology withIntegrated Micromachined InterconnectsRiki Banerjee – University of Minnesota,University of Maryland; Rhonda Franklin Drayton– University of Minnesota
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Wednesday, May 28Session 10:Thermal andThermo-Mechanical Modeling1:30 p.m. - 5:10 p.m.Committee: Modeling & Simulation
Session Co-Chairs:Tony Mak – Dallas SemiconductorCorporationTel: +1-972-371-4364 Fax: +1-972-371-4381Email: [email protected]
Moises Cases – IBM CorporationTel: +1-512-838-6225 Fax: +1-512-823-5938Email: [email protected]
A Finite Element Modeling Methodology forThermomechanical Analysis of Printed WiringBoard AssembliesHai Ding, Reinhard Powell, Carl Hanna, and I.Charles Ume – Georgia Institute of Technology
Power Cycling Simulation of IC Package:Considering Electromigration andThermal-Mechanical FailureYong Liu and Scott Irving – FairchildSemiconductor Corporation
Thermo-mechanical Reliability Evaluation ofHigh I/O CBGA (Ceramic Ball Grid Array)and CCGA (Ceramic Column Grid Array)PackagesAndy Perkins and Suresh K. Sitaraman – GeorgiaInstitute of Technology
Thermal Modeling and Design ofLiquid-Cooled Heat Sinks Assembled withFlip Chip BGA PackagesHengyun Zhang and Damaruganath Pinjala –A*STAR-Institute of Microelectronics;YogendraJoshi – Georgia Institute of Technology;TeckNeng Wong and Kok Chuan Toh – NanyangTechnological University
Thermal Modeling and Measurement ofAlGaN/GaN HFETs Built on Sapphire andSiC SubstratesJeong Park, Dimitri Kakovitch, and Chin Lee –University of California, Irvine; Moo Shin –Myeong Ji University
Time Evolution of Temperature Distributionof a Flip Chip No-Flow Underfill PackageDuring Solder Reflow ProcessZhuqing Zhang, Suresh Sitaraman, and C. P.Wong– Georgia Institute of Technology;AdisakVorakunpinij – Institute of Paper Science andTechnology
Electronic Components in Cellular Phones:Thermal Simulations and Evaluation ofModeling AssumptionsElie Awad and John Ferrario – IBM Corporation
Wednesday, May 28Session 11: RF Modules and Performance1:30 p.m. - 5:10 p.m.Committee: Components & RF
Session Co-Chairs:Craig Gaw – Motorola, Inc.Tel: +1-480-413-5920 Fax: +1-480-413-3481Email: [email protected]
Lih-Tyng Hwang – Motorola, Inc.Tel: +1-847-576-5182 Fax: +1-847-435-3780Email: [email protected]
Design of Multilayer Spiral InductorResonator FilterGye-An Lee and De Flaviis Franco – Universityof California, Irvine; Mohamed Megahed –Skyworks, Inc.
High Frequency SAW Correlator ModuleRobert Brocato, Edwin Heller, David Palmer andJoel Wendt – Sandia National Laboratories;Stephanie Jones and Glenn Omdahl – L&MTechnologies
Embedded Passives in Organic Substrate forBluetooth (TM) Transceiver ModuleLi Li, Phil Bowles, Lih-Tyng Hwang, and StevePlager – Motorola, Inc.
A Novel Integrated Dielectric ResonatorAntenna for Circular PolarizationAlexandre Popov and Mihai Rotaru – Institute ofMicroelectronics (IME)
Integration of Miniaturized Patch Antennaswith High Dielectric-Constant MultilayerPackages and Soft and Hard Surfaces (SHS)RongLin Li, Gerald DeJean, Manos Tentzeris, andJoy Laskar – Georgia Institute of Technology
An Investigation of the Properties ofAdvanced MCM-L Process and Materials upto 100GHzJanusz Grzyb, Didier Cottet, Ivan Ruiz, andGerhard Troester – ETH, Electronics Labs
RF Circuit Integration Using High Q CopperInductors on Organic Substrate andSolder-Bumped Flip Chip TechnologyGuo-Wei Xiao, Xiao Huo, and Philip Chan –Hong Kong University of Science and Technology
Wednesday, May 28Session 12: Novel Packaging EducationPrograms1:30 p.m. - 5:10 p.m.Committee: Education
Session Co-Chairs:Paul Wesling Tel: +1-408-252-9051 Fax: +1-408-285-9670Email: [email protected]
Andrew A. O.Tay – National University ofSingaporeTel: +65-6874-2207 Fax: +65-6791-1459Email: [email protected]
A Web-Based Course on Integrated PassiveComponent TechnologyRichard Ulrich – University of Arkansas
Educational Modules on RF MEMs and RFMicrosystemsAnh-Vu Pham – University of California, Davis
Internet-based Performance CentredInstruction: The Link between Work andEducation in MicroelectronicsSlavka Tzanova – Technical University of Sofia;Christian Schaeffer – CIME - INPG; Michel Royer– ELSYS Design;Ton Mouthaan – University ofTwente; Zsolt Illyefalvi-Vitéz – BudapestUniversity of Technology and Economics
Development and Dissemination of KEEP -Kentucky Electronics Education ProjectJanet Lumpp – University of Kentucky
Improving Graduate Packaging EducationThrough International CooperationJohn L. Prince and Kathleen L.Virga – Universityof Arizona; Gert Winkler – TechnischeUniversitat Ilmenau
Role of Independent Study in Creating anEffective Graduate-Level Program inElectronic PackagingHarry Charles – The Johns Hopkins University
Innovative Self-study Tools in MicrosystemsPackaging Education at Dresden Universityof TechnologyThomas Zerna, Martin Oppermann, KlausWolter, and Wilfried Sauer – Dresden Universityof Technology
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Thursday, May 29Session 13: Flip Chip Packaging8:00 a.m. - 11:40 a.m.Committee:Advanced Packaging
Session Co-Chairs:Raj N. Master – AMDTel: +1-408-982-7023 Fax: +1-408-982-6164Email: [email protected]
E. Jan Vardaman – TechSearchInternational, Inc.Tel: +1-512-372-8887 Fax: +1-512-372-8889Email: [email protected]
Large Die Flip Chip Packaging On OrganicSubstrates:The Role of Finite ElementAnalysis (FEA), Materials Characterization,Failure Analysis (FA) and Test Vehicles inDevelopment SpinsJason Goodelle,Ahmed Amin, Jeffery Gilbert,Christopher Horvath, Ed Nease, and BrianVaccaro – Agere Systems
Differences in the Sub-Processes of Ultra FinePitch Stencil Printing due to Type-6 andType-7 Pb-free Solder Pastes Used for FlipChipMike Hendriksen, Gavin Jackson, Ndy Ekere, andRajkumar Durairaj – University of Greenwich
Impact Properties of Flip ChipInterconnection Using AnisotropicallyConductive Film on the Glass and FlexSubstrateYiping Wu and Yan Cheong Chan – CityUniversity of Hong Kong; Bo Yi Wu – HuazhongUniversity of Science & Technology
HyperBGATM Success on the ManufacturingFloor - Meeting the Ramping Challenges ofComplex Product Assemblies with anAdvanced Flip Chip PackageJennifer Sweterlitsch, Dave Alcoe, and VirenJadhav – Endicott Interconnect Technologies Inc.
Bumpless Flip Chip Package forCost/Performance Driven DevicesCharles W.C Lin, Sam C.L Chiang, and T.KAndrew Yang – Bridge SemiconductorCorporation
Transfer Layer Technology for the Packagingof High Power ModulesMarco Balucani and Aldo Ferrari – University ofRome; Roberto Bellu – Semikron
Development of a 4-Layer Low-Cost FlipChip Packaging TechnologyAnand Govind and Farshad Ghahghahi – LSILogic Corporation
Thursday, May 29Session 14:Analytical Assessment ofReliability8:00 a.m. - 11:40 a.m.Committee: Quality & Reliability
Session Co-Chairs:Darvin R. Edwards – Texas InstrumentsTel: +1-972-995-3569 Fax: +1-972-995-2658Email: [email protected]
Xiaoling He – University of Wisconsin,MilwaukeeTel: +1-414-229-6772 Fax: +1-414-229-6958Email: [email protected]
Solder Joint Reliability Model with ModifiedDarveaux’s Equations for the Micro SMDWafer Level-Chip Scale Package FamilyLi Zhang,Viraj Patwardhan, Luu Nguyen, andNikhil Kelkar – National SemiconductorCorporation; Ram Sitaraman – State Universityof New York at Binghamton
Predictive Failure Model of Flip Chip onBoardJennifer Muncy and Ted Lazarakis – GeorgiaInstitute of Technology; Daniel Baldwin – SiemensDematic
Effect of Package and Board Characteristics onSolder Joint Reliability of MicroStar BGA ™Manjula Variyam,Vish Sundararaman, Cheng Chiu,and Darvin Edwards – Texas Instruments, Inc.
Effect of Intergrated Heat Spreader on FlipChip Ball Grid Array (FCBGA) Package SolderJoint ReliabilityChee Wai Wong, Cheng Siew Tay, Siew Sang Tan,Chee Kan Lee, and Tee Onn Chong – IntelProducts (M) Sdn. Bhd.; Luke Garner and VinayakPandey – Intel Corporation
Structural and Material System Design for aHighly Reliable 3D Die-Stacked Module withCu Through ViasNaotaka Tanaka,Yasuhiro Yamaji,Tomotoshi Sato,and Kenji Takahashi – Association ofSuper-Advanced Electronics Technologies (ASET)
Fatigue Life Models for SnAgCu and SnPbSolder Joints Evaluated by Experiment andSimulationAndreas Schubert, Rainer Dudek,AstridGollhardt, Ellen Auerswald, Bernd Michel, andHerbert Reichl – Fraunhofer Institute forReliability and Microintegration IZM
Damage Accumulation and MicrocrackNucleation in Solder under Applied ShearStress FieldSridhar Canumalla and Tommi Reinikainen –Nokia Mobile Phones
Thursday, May 29Session 15: MEMs8:00 a.m. - 11:40 a.m.Committee: Interconnections
Session Co-Chairs:Goran Matijasevic – University ofCalifornia, IrvineTel: +1-949-824-9830 Fax: +1-949-824-3732Email: [email protected]
Matt Schwiebert – Agilent Technologies,Inc.Tel: +1-408-553-2385 Fax: +1-408-246-5925Email: [email protected]
Novel Multi-layer Through-Die Connectionsfor Package-to-Chip Power and GroundConnectionsSwaroop Kommera,Wayne Woods, and PeterKrusius – Cornell University
A Novel Electrically Conductive WaferThrough Hole Filled Vias InterconnectFormation for 3D MEMS PackagingC. S. Premachandran, Ranganathan Nagarajan,Chong Ser Chong, and Chen Yu – Institute ofMicroelectronics (IME)
IC Stacking Technology Using Fine Pitch,Nanoscale Through Silicon ViasSilke Spiesshoefer and Leonard Schaper –University of Arkansas
Batch Fabrication of Through-Wafer Vias inCMOS Wafers for 3D Packaging ApplicationsFrank Engel Rasmussen and Ole Hansen –Mikroelektronik Centret,Technical University ofDenmark; Matthias Heschel – Hymite A/S
High Density Electroplating BondingInterconnect Technology: Chip Packaging andHigh Aspect Ratio Passive ElementsYeun-Ho Joung and Mark Allen – GeorgiaInstitute of Technology
High-Density Packaging Technologies onSilicon SubstratesMiyuki Akazawa, Satoru Kuramochi, KouichiNakayama, and Atsushi Takano – Dai NipponPrinting Co.,ltd.;Yoshitaka Fukuoka – WorldwideElectronic Integrated Substrate Technology Inc.
Using PDMS MicroTransfer Molding (uTM)for Polymer Flip ChipCell KY Wong, Bing Xu, and Matthew M. F.Yuen– Hong Kong University of Science andTechnology
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Thursday, May 29Session 16: Pb-Free Solders8:00 a.m. - 11:40 a.m.Committee: Materials & Processing
Session Co-Chairs:Chin C. Lee – University of CaliforniaTel: +1-949-824-7462 Fax: +1-949-824-3732Email: [email protected]
Kyung-Wook Paik – Korean AdvanceInstitute of Science and TechnologyTel: +82-42-869-3335 Fax: +82-42-869-3310Email: [email protected]
Improvement in the Properties of Sn-ZnEutectic Based Pb-free SolderKwang-Lung Lin, Hui-Min Hsu, and Chia-LingShih – National Cheng Kung University; Kang-IChen – Tung-Fang Institute of Technology
Pb-free Bumping Process by AlloyingElectroplated Metal StacksHirokazu Ezawa, Masahiro Miyata, and MasaharuSeto – Toshiba Corporation SemiconductorCompany
New Fluxless Bonding Process in Air UsingSn-Bi with Au CapDongwook Kim and Chin Lee – University ofCalifornia, Irvine
Bulk Solder and Solder Joint Properties forLead Free 95.5Sn-3.8Ag-0.7Cu AlloyJohn H. L. Pang, B. S. Xiong, C. C. Neo, X. R.Zhang, and T. H. Low – Nanyang TechnologicalUniversity
Mechanical Tensile Fracture Behaviors ofSolid-State-Annealed Eutectic SnPb andLead-Free Solder Flip Chip BumpsJin-Wook Jang,Ananda De Silva, Jong-Kai Lin, andDarrel Frear – Motorola, Inc.
A Reliability Comparison of Electroplatedand Stencil Printed Flip Chip Solder BumpsBased on UBM Related IntermetallicCompound Growth PropertiesJing-Feng Gong, Guo-Wei Xiao, Philip Chan,Ricky Lee, and Matthew Yuen – Hong KongUniversity of Science and Technology
3D Nonlinear Stress Analysis of Tin WhiskerGrowth on Lead-Free ComponentsJohn H. Lau – Agilent Technologies, Inc.; StephenPan – Optimal Corporation
Thursday, May 29Session 17: New Materials and InterfaceDelamination Modeling andExperiments8:00 a.m. - 11:40 a.m.Committee: Modeling & Simulation
Session Co-Chairs:Suresh K. Sitaraman – Georgia Institute ofTechnologyTel: +1-404-894-3405 Fax: +1-404-894-9342Email: [email protected]
Erdogan Madenci – University of ArizonaTel: +1-520-621-6113 Fax: +1-520-621-8191Email: [email protected]
Experimental and Modeling Analysis of theReliability of Anisotropic Conductive FilmsChunyan Yin, Hua Lu, and Chris Bailey – TheUniversity of Greenwich;Yan Cheung Chan –City University of Hong Kong
An Energy-Based Method to PredictDelamination in Electronic PackagingHaibo Fan, Hon Bun Tang, Matthew M. F. Yuen,and Philip C. H. Chan – Hong Kong University ofScience and Technology
Mechanical Characterization and Modelingof Low-Dielectric-Constant Films usingNano-Indentation:Time- andTemperature-EffectsJaap Den Toonder and Auke Van Dijken – PhilipsResearch Laboratories;Viktor Gonda and LeoErnst – Delft University of Technology; JohanBeijer and Kouchi Zhang – Philips Center forIndustrial Technology
Interfacial Fracture Analysis of UnderfillDelamination and Flip Chip ReliabilityOptimizationCharlie Zhai, Sidharth Sidharth, Richard Blish, RajMaster, and Srinivasan Parthasarathy – AdvancedMicro Devices, Inc.
Measurements and Modeling of theTemperature Dependent Material Behaviorof Underfill EncapsulantsSaiful Islam, Baohua Xu, R.Wayne Johnson,Pradeep Lall, and John L. Evans – AuburnUniversity
Effect of Packaging on Interfacial Cracking inCu/ Low k Damascene StructuresGuotao Wang and Paul Ho – University of Texasat Austin; Steven Groothuis – Micron TechnologyTexas LLC
Analytical Solution for Moisture-InducedInterface Delamination in ElectronicPackagingXuejun Fan – Philips Research - USA; G. Q.Zhang – Philips-CFT;W.Van Driel – ATOInnovation/Philips Semiconductors; L. J. Ernst –Delft University of Technology
Thursday, May 29Session 18: Multimedia PackagingEducation8:00 a.m. - 11:40 a.m.Committee: Education
Session Co-Chairs:Albert F. Puttlitz – Mechanical Eng.ConsultantTel: +1-802-899-4692 Fax: +1-802-899-4692Email: [email protected]
Rao R.Tummala – Georgia Institute ofTechnologyTel: +1-404-894-9097 Fax: +1-404-894-3842Email: [email protected]
Development of a Web-based Course onLead Free Solders for Electronics PackagingJohan Liu – Chalmers University of Technology
Mechanical Properties of PackagingMaterials -The Need and a Strategy for anEducational ModuleSteffen Wiese and Klaus-Juergen Wolter –Dresden University of Technology
Flip Chip Packaging Interconnect Technologyand ReliabilityXiaoling He – University of Wisconsin,Milwaukee
Multimedia for MEMS Technologies andPackaging EducationGabor Harsanyi, Gergely Ballun, Peter Bojta, andPeter Gordon – Budapest University ofTechnology and Economics (BUTE)
Development of Graduate LevelOptoelectronic Packaging Courses at SJSUGuna Selvaduray and Joseph Becker – San JoseState University
Educational Development for Mixed SignalDesign and TestKimberly Newman and Gerald Edelstein –University of Denver
International Web Course on Mixed-SignalIC TestBruce Kim – Arizona State University
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Thursday, May 29Session 19: Devices for WavelengthDivision Multiplexing1:30 p.m. - 5:10 p.m.Committee: Optoelectronics
Session Co-Chairs:Martin Groeneveld – JDS UniphaseTel: +31-40-2578736 Fax: +31-40-2578401Email:[email protected]
Randy Heyler – Newport CorporationTel: +1-949-862-3465 Fax: +1-949-862-3534Email: [email protected]
The Optical Challenges in Next GenerationNetworksMichael Socher – Siemens Information andCommunication Networks, Inc.
Tunable Optical Filters for DynamicNetworksBob Cormack – Micron Optics, Inc.
Micro-Electro-Mechanically TunableTwo-Chip VCSELs for 1.55 umFrank Riemenschneider, Hubert Halbritter, andPeter Meissner – Technische UniversitätDarmstadt; Isabelle Sagnes and ClementineSymonds – LPN-CNRS; Gerhardt Böhm, MarkusMaute, and Markus-Christian Amann –Technische Universität München
Performance and Reliability of WidelyTunable Laser DiodesTorsten Wipiejewski – Agility Communications
Integrated Tunable Transmitter for 10Gb/sLong-Haul DWDM ApplicationsJon Hall, Colin Edge, Fred Randle, Steve Pope, JimFraser, and Jason Loosely – Bookham Technology
WDM Power Level Monitor with MicroPyramid Mirrors formed in Arrayed OpticalWaveguideHikaru Kouta, Mikio Oda,Taro Kaneko, andYutaka Urino – NEC Corporation;TadahikoHanada – NEC FiberOptech, Inc.
Development of Internal Wavelength Lockersfor Tunable Laser ApplicationsHongtao Han, Barney Hammond, Robert Boye,Bingzhi Su, Jay Mathews, Bob TeKolste,AlvaroCruz, Doug Knight, and Dave Aichele – DigitalOptics Corporation
Thursday, May 29Session 20: Pb-Free Interconnections II1:30 p.m. - 5:10 p.m.Committee: Interconnections
Session Co-Chairs:Christine Kallmayer – TU BerlinTel: +49-30-46403-228Fax: +49-30-46403-161Email: [email protected]
Lei L. Mercado – Intel CorporationTel: +1-480-552-1383 Fax: +1-480-554-7171Email: [email protected]
Microstructure Aspects and PerformanceImplications of Sn/Ag/Cu/Sb Solder Joints inthe Presence of GoldWei Peng, Steven Dunford,ViswanadhamPuligandla, and Stephen Quander – Nokia
Electromigration Behaviors of Pb-free SolderBumps for Flip Chip TechnologyJin-Wook Jang, Jerry White, Jong-Kai Lin, andDarrel Frear – Motorola, Inc.
Tin Whisker Formation - Results,TestMethods and CountermeasuresMarc Dittes – Infineon Technologies AG; PascalOberndorff – Philips CFT; Luc Petit –STMicroelectronics, Inc.
Thermo-Mechanical Fatigue Reliability ofLead Free Ceramic Ball Grid Arrays:Experimental Data and Lifetime PredictionModelingMukta Farooq, Lewis Goldmann, Gregory Martin,Charles Goldsmith, and Christian Bergeron –IBM Corporation
100 Micron Pitch Bumping Process for WaferLevel PackagingRavi Doraiswami, Ankur Aggarwal, Jing Li, PiyushGupta, Sandeep Sankararaman, Z. Zhang,Y. Sun,Lianhua Fan, C. P.Wong, and Rao Tummala –Georgia Institute of Technology
Fluxless Flip Chip Technique Using Sn-AuSolder Bumps on Thin Si ChipsDongwook Kim and Chin Lee – University ofCalifornia, Irvine; Witold Sokolowski – JetPropulsion Laboratories
Board Level Reliability of Components withMatte Tin Lead FinishLuu Nguyen, Randall Walberg, Lin Zhou, andTerence Koh – National SemiconductorCorporation
Thursday, May 29Session 21:Wafer Level and Chip ScalePackaging1:30 p.m. - 5:10 p.m.Committee:Advanced Packaging
Session Co-Chairs:Daniel Baldwin – Georgia Institute ofTechnologyTel: +1-404-894-4135 Fax: +1-404-894-9342Email: [email protected]
Luu T. Nguyen – Helsinki University ofTechnologyTel: +358-9-451-5905 Fax: +358-9-451-5776Email: [email protected]
Room Temperature Bonding of Ultra-FinePitch and Low-Profiled Cu Electrodes forBump-Less InterconnectAkitsu Shigetou,Toshihiro Itoh, KatsuyaOkumura, and Tadatomo Suga – Tokyo Univ.RCAST; Mie Matsuo and N. Hayasaka – ToshibaCorp. Semiconductor Company
Improvement in WL-CSP Reliability by WaferThinningLi Wetz, Beth Keser, and Jerry White – Motorola,Inc.
An Analysis of the Reliability of a Wafer LevelPackage (WLP) Using a Silicone Under theBump (SUB) ConfigurationMario Gonzalez, Bart Vandevelde, MathieuVanden Bulcke, Christophe Winters, and EricBeyne – IMEC; Yeong Lee, Lyndon Larson, BrianHarkness, Mustafa Mohamed, Herman Meynen,and Eric Vanlathem – Dow Corning
Multi-Chip Memory Module with a FlipChip-On-Chip Structure and an OptionalCenter Via Hole for Underfill DispensingRicky Lee,Yat Kit Tsui, and Raymond So – HongKong University of Science and Technology; LeLuo – SIMIT
Development of a High-Speed SMTCompatible Dispenseless Underfill Processfor CSP BGA Flip Chip AssemblyJian Zhang and Daniel Baldwin – GeorgiaInstitute of Technology
Processability and Electrical Characteristicsof Glass Substrates for RF Wafer Level Chip Scale PackagesAlexander Polyakov, Saoer Sinaga, Marian Bartek,Behzad Rejaei, and Joachim Burghartz – DelftUniversity of Technology; Paulo Mendes and JoseCorreia – University of Minho
Highly Reliable and Low-Cost Multi-ChipModule Composed of Wafer ProcessPackagesYasuhiro Naka and Takahiro Naito – Hitachi, Ltd.;Naotaka Tanaka – Mechanical EngineeringResearch Laboratory, Hitachi, Ltd.
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Thursday, May 29Session 22:Advances in Test Methods1:30 p.m. - 5:10 p.m.Committee: Quality & Reliability
Session Co-Chairs:Andreas Schubert – Fraunhofer Institutefor Reliability and Microintegration (IZM)BerlinTel: +49-30-46403-134Fax: +49-30-46403-211Email: [email protected]
Jo Caers – Philips Electronics SingaporePte Ltd.Tel: +65-6357-9370 Fax: +65-6356-6741Email: [email protected]
A Non-Destructive Visual Failure AnalysisTechnique for Cracked BGA InterconnectsJason Bragg, Justine Bookbinder, George Sanders,and Blake Harper – Celestica International Inc.
Vibration Fatigue Reliability of BGA-ICPackage with Pb-free solder and Pb-SnSolderYoung-Bae Kim and Young-Bae Kim – KyushuUniversity; Masazumi Amagai – Texas InstrumentsJapan
Mechanism-Based Improvements to FatigueModeling of Packages Using Thermal Shockand Intrinsic Material PropertiesShubhada Sahasrabudhe, Eric Monroe, andShalabh Tandon – Intel Corporation
Characterization of Die Stresses in Flip Chipon Laminate Assemblies Using (111) SiliconStress Test ChipsJeff Suhling, M. Kaysar Rahim, Scott Copeland, R.Wayne Johnson, Pradeep Lall, John L. Evans, andRichard C. Jaeger – Auburn University
A New Defect Detection Technique usingTransient Thermography for High DensityPackage and InterconnectionsT. C. Chai and Alastair Trigg – Institute ofMicroelectronics (IME); Brian Stephen Wong,W.M. Bai, and Y. K. Lam – Nanyang TechnologicalUniversity
Dynamic Resistance Thermal Stress Cycling(DRTSC) and Reliability For Printed CircuitBoardsNitin Desai, Jim Zollo, and Paul Crandall –Motorola, Inc.; Pradeep Lall – Auburn University
Implementation Of Low-Cost FailureDetection System Using ResistanceSpectroscopyJames Constable,Ashish Batra, and Lee Fang –State University of New York at Binghamton
Thursday, May 29Session 23: Underfills for Flip Chip1:30 p.m. - 5:10 p.m.Committee: Materials & Processing
Session Co-Chairs:C.P.Wong – Georgia Institute ofTechnologyTel: +1-404-894-8391 Fax: +1-404-894-9140Email: [email protected]
Chandra Jayaram – Intel Products (M)Sdn. Bhd.Tel: +604-408-2240 Fax: +604-408-2088Email: [email protected]
Novel Reworkable Fluxing Underfill for BoardLevel AssemblyZhuqing Zhang, Haiying Li, and C. P.Wong –Georgia Institute of Technology
The Effects of Rheological Properties onUnderfill ProcessingJinlin Wang – Intel Corporation
Nanocomposite Underfills for Flip ChipApplicationKathleen Gross, Steve Hackett,William Schultz,and Wendy Thompson – 3M; Zhuqing Zhang andC. P.Wong – Georgia Institute of Technology
Underfill Induced Stresses in Flip ChipAssembliesJames Hurley,Tanya Berfield, and Mark Wilson –Cookson Electronics; Jeffrey C. Suhling, M.Kaysar Rahim, and R.Wayne Johnson – AuburnUniversity
Lead-free Molded Underfill Technology forExpose Die Flip Chip Packages Assembled ina Molded Matrix Array Package FormChoong Kooi Chee,Vethanayagam Rudge, HwaWei Chan, Shanggar Periaman, Szu Shing Lim,AiLin Ong, and Edward Then – Intel TechnologySdn. Bhd.
Characterization of the Curing Properties ofNo-Flow Underfill and B-Stage FeasibilityStudy for Wafer Level ApplicationZhuqing Zhang and C. P.Wong – GeorgiaInstitute of Technology
Materials Characterization andRequirements of the Package AppliedUnderfillJay Shah, Paul Morganelli, and Brian Wheelock –Emerson & Cuming
Thursday, May 29Session 24: Electrical Modeling1:30 p.m. - 5:10 p.m.Committee: Modeling & Simulation
Session Co-Chairs:John L. Prince – University of ArizonaTel: +1-520-621-6187 Fax: +1-520-621-2999Email: [email protected]
Andreas Cangellaris – University of Ilinoisat Urbana-ChampaignTel: +1-217-333-6037 Fax: +1-217-333-5962Email: [email protected]
Electrical Modeling of Global Interconnectswith Electromagnetic AccuracyAndreas Cangellaris and Aosheng Rong –University of Illinois at Urbana-Champaign
Accurate HSPICE Modeling of ArbitraryPackage Geometries Using Transmission LineEquivalent TechniquesTimothy Budell, Paul Clouser, and Eric Tremble –IBM Corporation; Brian Welch – CornellUniversity
Investigation of the Impact of ConductorSurface Roughness on InterconnectFrequency-Dependent Ohmic LossAndreas Cangellaris and Leonid Proekt –University of Illinois at Urbana-Champaign
Waveguide Type Shield Model for LSI Chipthat Reduces EMI and TemperatureHideo Kikuchi and Osamu Ibaragi – Associationof Super-Advanced Electronics Technologies
3GHz Through-Hole Signal Via ModelConsidering Power/Ground Plane ResonanceCoupling and Via Neck EffectJun So Pak and Joungho Kim – Korea AdvancedInstitute of Science and Technology (KAIST)
Extension of the Hybrid Phase PoleMacromodel to Frequency-Dependent LossyTransmission LinesBing Zhong, Steven Dvorak, and John Prince –University of Arizona
Accurate Modeling of Multilayer PackagingStructures with Multiple Ground PlanesIncluding Metal and Dielectric LossCharacteristicsEdan Dalton, Nathan Bushyager, and ManosTentzeris – Georgia Institute of Technology;Marco Kunze and Wolfgang Heinrich –Ferdinand-Braun-Institut fürHöchstfrequenztechnik
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Friday, May 30Session 25: Optical Backplane and ParallelInterconnects8:00 a.m. - 11:40 a.m.Committee: Optoelectronics
Session Co-Chairs:Jean Trewhella – IBM T. J.Watson ResearchCenterTel: +1-914-945-2786 Fax: +1-914-945-1974Email: [email protected]
Torsten Wipiejewski – AgilityCommunicationsTel: +1-805-690-1781 Fax: +1-805-690-1855Email: [email protected]
Multi-Channel Optical Interconnects forShort Reach ApplicationsDavid Dolfi – Agilent Technologies, Inc.
10 Gbit/s per Channel Parallel OpticalTransmitter and Receiver Modules forHigh-Capacity InterconnectsMasato Shishikura,Takuma Ban, HirokazuIchikawa,Tatemi Ido, Makoto Takahashi, KojiNakahara, Etsuko Nomoto,Yasunobu Matsuoka,Kyosuke Ishikawa, Masahiro Ito, Ryoji Takeyari,and Hirohisa Sano – Hitachi, Ltd.
High Speed Optical Interconnection usingEmbedded PDs on Electrical BoardsSang-Yeon Cho, Jeff Hall,AnanthasayanamChellappa, Nan Jokerst, and Martin Brooke –Georgia Institute of Technology
Planar Glass Wave Guides for HighPerformance Electrical-Optical-Circuit-Boards (EOCB) -The Photonic-LayerConceptHenning Schröder – Fraunhofer Institute forReliability and Micro-integration IZM; NorbertArndt-Staufenbiel – Brandenburgische TechnischeUniversität Cottbus; Manfred Cygon – Isola AG
Performance Comparison of Parallel OpticalInterconnects for Enterprise ServersCasimer DeCusatis – IBM Corporation; RobAtkins – Princeton University
Status and Progress of Optical BackplaneSolutions for Terabit DXCsRobert Fuerst and Axel Beier – InfineonTechnologies
Opto-Electonic Backplane Technology forCost-Effective Bandwidth ManagementMichael Meis – 3M Company
Friday, May 30Session 26: 3D Packaging Technologies8:00 a.m. - 11:40 a.m.Committees:Advanced Packaging andInterconnections
Session Co-Chairs:Jeffrey A. Knight – IBM CorporationTel: +1-607-757-1015 Fax: +1-607-757-1860Email: [email protected]
S.W. Ricky Lee – Hong Kong University ofScience & TechnologyTel: +852-2358-7203 Fax: +852-2358-1543Email: [email protected]
Chip-to-Wafer Stacking Technology for 3DSystem IntegrationArmin Klumpp, Reinhard Merkel, RobertWieland, and Peter Ramm – Fraunhofer Institutefor Reliability and Microintegration IZM
Ultra-High-Density 3D Chip StackingTechnologyKazumasa Tanida, Mitsuo Umemoto,YoshihiroTomita,Yoshihiko Nemoto, Masamoto Tago,Tatsuya Ando, and Kenji Takahashi – Associationof Super-Advanced Electronics Technologies(ASET)
Planar Metallization Interconnected 3DMulti-Chip ModuleZhenxian Liang – CPES,Virginia Tech; J. D. VanWyk – Virginia Tech
Design and Stacking of an Extremely ThinChip-Scale PackageAkito Yoshida – Amkor Technology, Inc.; KazuoIshibashi – Nokia Mobile Phones
Stacked Multi-Chip Package with Plastic BallVertical InterconnectionsJani Miettinen, Jarmo Tanskanen, and EeroRistolainen – Tampere University of Technology
Three-Dimensional System in PackagingTechnologyTakuya Sugiyama,Yano Yuji, Seiji Ishihara,YasukiFukui, Hiroyuki Juso, Koji Miyata,Yoshiki Sota, andTomoshi Kimura – Sharp Corporation
Development of Distributed Sensing Systemsof Autonomous Micro-ModulesJohn Barton, Kieran Delaney, and Cian ÓMathúna – NMRC; Joseph Paradiso and AriBenbasat – MIT Media Lab
Friday, May 30Session 27: Novel Interconnections8:00 a.m. - 11:40 a.m.Committee: Interconnections
Session Co-Chairs:Dennis Olsen – ConsultantTel: +1-480-994-9926 Fax: +1-480-994-8013Email: [email protected]
David McCann – Amkor Technology, Inc.Tel: +1-480-821-5000-5029Fax: +1-480-821-2389Email: [email protected]
Development of a Novel Technology forBuilding Flexible and Wearable IntegratedSystemsThomas Healy,Alan Mathewson, John Alderman,and Julie Donnelly – NMRC
New Assembly Technologies for TextileTransponder SystemsChristine Kallmayer – Fraunhofer Institute forReliability and Microintegration IZM; RubinPisarek and Sven Cichos – TU Berlin; AndreasNeudeck and Sabine Gimpel – TITV
Multi-Layer Flexible Substrate for MCMModuleHyuek-Jae Lee and Jin Yu – Korea AdvancedInstitute of Science and Technology (KAIST)
A Novel Technology for Stacking theMicrovias on the Printed Circuit BoardFuhan Liu, George White,Venky Sundaram,Ankur Aggarwal, Dean Sutter, and Rao Tummala– Georgia Institute of Technology
Laser Ablation as an Enabling Technology forOpto-BoardsPeter Van Daele, Geert Van Steenberge, PeterGeerinck, Steven Van Put, and Maarten Cauwe –IMEC - Ghent University
Demonstration of On-PCB OpticalInterconnection Using Surface-MountPackages and Polymer WaveguideYuzo Ishii,Tsuyoshi Hayashi, and HideyukiTakahara – NTT
Embedded Optical Interconnections onPrinted Wiring BoardsTakeshi Suzuki,Toshihisa Nonaka, Sang-Yeon Cho,and Nan Jokerst – Georgia Institute ofTechnology
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Friday, May 30Session 28: Reliability Issues in Polymersand Interfaces8:00 a.m. - 11:40 a.m.Committee: Quality & Reliability
Session Co-Chairs:Charles Zhang – Intel CorporationTel: +1-480-552-0453 Fax: +1-480-554-7171Email: [email protected]
Ephraim Suhir – University of Illinois atChicagoTel: +1-650-969-1530Fax: 650-968-4611Email: [email protected]
Prediction of Delamination in Bi-MaterialSystem Based on Free-Edge EnergyEvaluationHaibo Fan and Mathew M. F.Yuen – Hong KongUniversity of Science and Technology; EphraimSuhir – University of Illinois at Chicago
A Modified Button-Shear Method ofMeasuring Adhesion Strength ofPolymer-Metal Interfaces Encountered in ICPackagesAndrew Tay and Jyh Siong Phang – NationalUniversity of Singapore; Ee Hua Wong and RajooRanjan – Institute of Microelectronics (IME)
Failure Analysis of Full Delamination on theStacked Die Leaded PackagesTingyu Lin,Yu Feng Yao, Zheng Peng Xiong,TokLane, ZeYan Yu, Njoman Budi, and K. H. Chua –Agere Systems
Prediction of Moisture Induced Failures inFlip Chip on Flex Interconnections withNon-Conductive AdhesivesJo Caers and Xiujuan Zhao – Philips ElectronicsSingapore; Ee Hua Wong, Xiao Wu Zhang, ChuKuen Ong, and Ranjoo Ranjan – Institute ofMicroelectronics (IME)
Evaluation of RF PA Module ReliabilityRobert Darveaux, Jicheng Yang, and Ahmer Syed– Amkor Technology, Inc.
Reliability Study for Low-CostSemiconductor Packaging for Long LifeApplicationsElie Awad, Francisco Vicenty, and Niki Spencer –IBM Corporation
Reliability Evaluation Structures for StackedThin Dice PackagingPaivi Karjalainen, Jarmo Tanskanen, and EeroRistolainen – Tampere University of Technology
Friday, May 30Session 29: Interconnect Metallurgies8:00 a.m. - 11:40 a.m.Committee: Materials & Processing
Session Co-Chairs:Rajen Chanchani – Sandia National LabsTel: +1-505-844-3482 Fax: +1-505-844-7011Email: [email protected]
Eric Perfecto – IBM MicroelectronicsTel: +1-845-894-4400 Fax: +1-845-892-6208Email: [email protected]
Comparison of Interfacial Reactions andReliabilities of Sn3.5Ag, Sn4.0Ag0.5Cu, andSn0.7Cu Solder Bumps on Electroless Ni-PUBMsYoung-Doo Jeon and Kyung-Wook Paik – KoreaAdvanced Institute of Science and Technology(KAIST); Adreas Ostmann and Herbert Reichl –Fraunhofer Institute for Reliability andMicrointegration IZM
Investigation of Electroplating Ni UBM forPb-Free SoldersShu-Ming Chang, Ruoh-Huey Uang, Dau-ChiLiou, Hsu-Tien Hu, Kuo-Chuan Chen,Yu-FangChen, and Yu-Hua Chen – Industrial TechnologyResearch Institute (ITRI)
Growth and Selection of Intermetallic Speciesin Sn-Ag-Cu no-Pb Solder Systems Based onPad Metallurgies and Thermal Histories.Lawrence Lehman and Eric Cotts – StateUniversity of New York at Binghamton
UBM Integrity Studies on Copper/Low-kDielectrics for Fine Pitch Flip Chip PackagingSeung Wook Yoon,Vaidyanathan Kripesh,WaiKwan Wong, Xian Tong Chen, Dong Gui,Mahadevan K. Iyer – Institute ofMicroelecttronics (IME); Ignatius J. Rasiah –Honeywell
Investigation of Co UBM for Direct Flip ChipBumping on Cu/lowK DiesRiet Labie, Eric Beyne, and Petar Ratchev – IMEC
Effects of Antimony on the Growth ofIntermetallic Compounds in Sn-Ag-CuPb-free Solder JointsGuoyuan Li and Binling Chen – NanyangTechnological University
Interfacial Reaction of Eutectic AuSi Solderwith Si (100) and Si (111) SurfacesJin-Wook Jang, Scott Hayes, Jong-Kai Lin, andDarrel Frear – Motorola, Inc.
Friday, May 30Session 30: Electrical Characterizationand Validation8:00 a.m. - 11:40 a.m.Committee: Modeling & Simulation
Session Co-Chairs:Michael Lamson – Texas InstrumentsTel: +1-972-995-2490 Fax: +1-972-995-2658Email: [email protected]
Madhavan Swaminathan – GeorgiaInstitute of TechnologyTel: +1-404-894-3340 Fax: +1-404-894-9959Email: [email protected]
Model-to-Hardware Correlations in theDesign of a 50Gb/s PackageLei Shan, Mounir Meghelli,Alexander Rylyakov,Jean Trewhella, and Modest Oprysko – IBMCorporation
Analysis of RF Flip Chip On-chip Inductancewith Novel Measurement TechnologyGye-An Lee and De Flaviis Franco – Universityof California, Irvine; Mohamed Megahed –Skyworks, Inc.
Broadband Characterization of PackageDielectricsHenning Braunisch and Dong-Ho Han – IntelCorporation
High Frequency Modeling andCharacterization of Pin and Land Grid ArraySocketsDong-Ho Han,Victor Prokofiev, Leigh Wojewoda,Thomas Ruttan, and Polka Lesley – IntelCorporation
Electrical Modeling and Characterization ofPackaging Solutions Utilizing Lead-FreeSecond Level InterconnectsDaniel O’Connor, Harvey Hamel, andChristopher Spring – IBM Corporation
Simple and Accurate Determination ofComplex Permittivity and Skin Effect of FR4Material in Gigahertz RegimeKarl Bois, Brian Kirk, Michael Tsuk, and DavidQuint – Hewlett-Packard
Effect of Decoupling Capacitors on SignalIntegrity in Applications With ReferencePlane ChangeJunho Lee,Albert C.W Lu,Wei Fan, and Lai L.Wai – Singapore Institute of ManufacturingTechnology (SIMTech); Joungho Kim – TerahertzMedia and System Lab., KAIST
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Friday, May 30Session 31: Low Cost Manufacturing ofOptoelectronics1:30 p.m. - 5:10 p.m.Committee: Optoelectronics
Session Co-Chairs:James E.Watson – 3M CompanyTel: +1-651-733-3890 Fax: +1-651-733-6631Email: [email protected]
Andrew Shapiro – University ofCalifornmia, IrvineTel: +1-949-824-8086 Fax: +1-949-824-2541Email: [email protected]
Micro Photonic Integrated Circuits forLow-Cost Optical SystemsWaguih Ishak – Agilent Technologies, Inc.
High Performance and Highly FunctionalSemiconductor Optical Amplifiers Based onHybrid and Monolithic IntegrationMario Dagenais, Peter S. Heim, Stewart Wilson,Simarjeet Saini, Dennis Bowler,Timothy Horton,Yimin Hu,Anthony Yu, Dennis Stone, and VinceLuciani – Quantum Photonics, Inc.
Automated Assembly and Packaging ofHybrid Optical ModulesHenrik Madsen, Lior Shiv, and Matthias Heschel –Hymite A/S; Gordon Elger,Andreas Hase, andJochen Kuhmann – Hymite GMBH
Quasi-Hermetic Photonic Packages withPolymer Sealants in a Central OfficeEnvironmentFrank Xu – Chorum Technologies
Direct Coupling Fiber Retention Using LaserSoldering:Technical and Economic BenefitsCathal Flanagan, Scott Trask, and Randy Heyler –Newport Corporation
High Coupling Efficiency Actively AlignedLaser Modules Using Micro-Heaters andPre-CompensationMadhumita Datta and Mario Dagenais –University of Maryland
Silicon Microlens on V-groove Platform forLow-Cost and High-Performance OpticalModulesDaisuke Shimura, Masahiro Uekawa, KyokoKotani,Yoshinori Maeno, Hironori Sasaki, andTakeshi Takamori – Oki Electric Industry Co.,Ltd.
Friday, May 30Session 32:Wire Bonding1:30 p.m. - 5:10 p.m.Committee: Interconnections
Session Co-Chairs:Rajen Dias – Intel CorporationTel: +1-480-554-5202 Fax: +1-480-554-7171Email: [email protected]
Mark V. Brillhart – Cisco Systems Tel: +1-408-525-7466 Fax: +1-408-527-8535Email: [email protected]
Novel Method of Separating Probe and WireBond Regions without Increasing Die SizeTu Anh Tran, Chu-Chung Lee, Bill Williams, andJody Ross – Motorola, Inc.
Dynamic and Quasi-Static Three-Dimensional Simulation of Wire LoopingProcess in WirebondingAndrew Tay and Beng Hung Ng – NationalUniversity of Singapore; Soon Huat Ong –National Semiconductor Singapore
Wire Looping Optimization in Fine PitchWire Bonded Staggered Pad DevicesTu Anh Tran, Lois Yong, and Fuaida Harun –Motorola, Inc.
Reliability of Wirebond Over Active Circuitryfor 0.13um CMOS TechnologyKevin Hess, Susan Downey, James Miller, DavidWontor, Geoffrey Hall,Willson Ng, and LeiMercado – Motorola, Inc.
Wirebonding Problems on Probe Marks andPossible SolutionsWolfgang Sauter – IBM Corporation;ToyohiroAoki,Takashi Hisada, and Hiromitsu Miyai – IBMJapan; Kevin Petrarca and Jennifer Power – IBMUSA; Frederic Beaulieu – IBM Canada
Improving the Deflection of Wire Bonds inStacked Chip Scale Package (CSP)Yufeng Yao,Tinyu Lin, and Simon Chua – AgereSystems Singapore Pte Ltd
Design Optimization of Wire Bonding forAdvanced Packaging ApplicationsC.W Lu and Lai L.Wai and Wei Fan – SingaporeInstitute of Manufacturing Technology
Friday, May 30Session 33:Adhesives1:30 p.m. - 5:10 p.m.Committee: Materials & Processing
Session Co-Chairs:Johan Liu – Chalmers University ofTechnologyTel: +46-31-706-6294 Fax: +46-31-706-6289Email: [email protected]
Jim Morris – Portland State UniversityTel: +1-503-725-9588 Fax: +1-503-725-3807Email: [email protected]
Effect of Sacrificial Anodic Fillers on ContactResistance Stability of ElectricallyConductive Adhesives onto Lead-Free AlloySurfacesHaiying Li, Kyoung-Sik Moon, and C. P.Wong –Georgia Institute of Technology
Investigation of Conductive Adhesive BondingUsing UV Curable ACFs at Different CuringConditionsKa Ka Lee, Sai Choo Tan,Yan Cheong Chan, NinHong Yeung, and Kai Kay Chan – City Universityof Hong Kong
Thermal Conductivity and RF SignalTransmission Properties of Ag-Filled EpoxyResinTadashi Kimura,Tsukasa Nakai, Haruo Ishikawa,Chizuko Ooyama, Keiichi Oosawa, and ShigeruKohinata – Sumitomo Metal Mining Co., Ltd.
A Reworkable Epoxy Resin for IsotropicallyConductive AdhesiveHaiying Li and C. P.Wong – Georgia Institute ofTechnology
Flip Chip Interconnection Using AnisotropicConductive Adhesives for RF and HighFrequency ApplicationsMyung Jin Yim, In Ho Jung, Ki Joong Kim, Jin SangHwang, Jin Gu Kim, and Jin Yong Ahn – Telephus,Inc; Woonsung Kwon and Kyung Wook Paik –Korea Advanced Institute of Science andTechnology (KAIST)
Improvements in the Reliability andManufacturability of an Integrated RF PowerAmplifier Module System-In-Package, viaImplementation of Conductive EpoxyAdhesive for Selected SMT Components.Daniel Cavasin, Ken Brice-Heames, and AnwarArab – Motorola, Inc.
Thermo-Mechanical Behavior of a NovelLight ModulatorZhimin Mo, Shiming Li, and Johan Liu – ChalmersUniversity of Technology; Helge Kristiansen –SINTEF Electronics and Cybernetics; MortenEliassen – Photonyx
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Friday, May 30Session 34: System Design ElectricalIssues1:30 p.m. - 5:10 p.m.Committee: Modeling & Simulation
Session Co-Chairs:Ravi Kaw – Agilent TechnologiesTel: +1-408-345-8893 Fax: +1-408-345-8088Email: [email protected]
George A. Katopis – IBM CorporationTel: +1-914-435-6719 Fax: +1-914-435-1593Email: [email protected]
Modeling the Performance of EmbeddedGridded Plane Structures in LTCCGuang Chen and Kathleen Virga – University ofArizona; Gert Winkler – Technische UniversitätIlmenau, Ilmenau, Germany; John Prince – ECEDept, University of Arizona
Substrate Design Optimization for HighSpeed LinksDaniel de Araujo – IBM Corporation; MoisesCases – IBM xSeries eServer; Nam Pham – IBMCorporation eServer; Barry Rubin – IBMResearch
Dependence of Bus Performance on theChoice of BGA Package Used for aFormatter Chip in a Printer CardRavi Kaw, Robert Batey, Michael Kelly, and JosephCasprowiak – Agilent Technologies, Inc.
Pentium™ 4 Processor Package Design andDevelopmentAltaf Hasan,Ajit Sathe, Ram Viswanath, andDustin Wood – Intel Corporation
Split-Ground Effect of Electronic Package onthe Input-Level of High-Speed DRAMJongjoo Lee, Junghwan Choi, and Dong-Ho Lee –Samsung Electronics Co. Ltd.
Electrical Design and Characterization ofDifferential Pairs in PBGA Packages for10Gb/s ApplicationsXingling Zhou and Nancy J. Fang – Agere Systems
Package Electrical Specifications for Giga BitSignaling I/OsUdy Shrivastava,Victor Prokofiev, Chee Hoo Lee,Anne Augustine, and Lesley Polka – IntelCorporation
Friday, May 30Session 35:Advancements in WaferThinning, Bumping and Interconnect inSupport of Wafer Level PackagingManufacturing1:30 p.m. - 5:10 p.m.Committee: ManufacturingTechnology
Session Co-Chairs:Tom Poulin – Aerie EngineeringTel: +1-909-248-1237Email: [email protected]
Claude Ladouceur – IBM Canada, Ltd.Tel: +1-450-534-7314 Fax: +1-450-534-6773Email: [email protected]
Wafer Deposition/Metalization and BackGrinding Process-Induced WarpageSimulationScott Irving and Yong Liu – FairchildSemiconductor Corporation
Cost-Performance Wafer Thinning TechnologyLarry Wu, Jacky Chan, C. F Chen, David Tseng,and C. S Hsiao – Siliconware Precision IIndustryCo., Ltd
New Concepts of Material DepositionTechnologies for 300mm Wafer BumpingJoachim Kloeser and Thomas Oppert – EKRAEduard Kraft GmbH
Establishing Control Factors of IntermetallicFormation within Pb-Free SolderInterconnections at Flip Chip GeometriesGavin Jackson, Budiman Salam, and Ndy Ekere –University of Greenwich; Mike Hendriksen –Celestica; Nick Hoo – ITRI
The Study on the Improvement of LeadBroken Failure in TCP Using New SnPre-Plating ProcessDae-Woo Son, Kwan Jai Lee, Jin Hyuk Lee andYeJung Chung – Samsung Electronics Co. Ltd.
Development of Interconnect Technologiesfor Embedded Organic PackagesMasahiro Sunohara, Kei Murayama, MitsutoshiHigashi, and Mitsuharu Shimizu – Shinko ElectricIndustries Co., Ltd.
Thermal Simulation and Testing of Standardand Wide Mold Body Drop-In Heat SinkPlastic Ball Grid Array Packages forEnhanced Heat Transfer PerformanceBret Zahn – ChipPAC Inc.
Friday, May 30Session 36: Component Technology1:30 p.m. - 5:10 p.m.Committee: Components & RF
Session Co-Chairs:Leonard W. Schaper – University ofArkansasTel: +1-479-575-8408 Fax: +1-479-575-2719Email: [email protected]
Rao Bonda – Motorola, Inc.Tel: +1-480-413-6121 Fax: +1-480-413-4511Email: [email protected]
Design Rule Development for ElectricalModeling of RF Multilayer PackagingInductorsMekita F. Davis, Rana J. Pratap, Stephane Pinel,Umesh Jalan, Dung-Kunm Kim, Joy Laskar, andGary May – Georgia Institute of Technology
A New System-on-a-Chip (SOC) TechnologyVHigh Q Post Passivation InductorsM. S. Lin, Ling Chen, J.Y. Lee, K. H.Wan, H. M.Chen, Kevin Chou, Roger Hsiao, and Eric Lin –Megic Corp
Analysis of High Q Inductors Realised UsingWafer-Level Packaging TechniquesXiao Sun, Geert Carchon,Walter De Raedt, andEric Beyne – IMEC
New Design for High Reliability, Fillet-LessThick Film Chip ResistorsYaron Kadim and Leonid Akhtman – Vishay IsraelLtd.
Integration and High FrequencyCharacterization of PWB-Compatible PureBarium Titanate Films Synthesized by ModifiedHydrothermal Techniques (< 100 C).Devarajan Balaraman, P. Markondeya Raj, SwapanBhattacharya, Lixi Wan, Madhavan Swaminathan,and Rao R.Tummala – Georgia Institute ofTechnology
Development of a PWB with Resin Capacitorfor RF Module SubstrateYasushi Shimada, Kazuhisa Otsuka, and YoshitakaHirata – Hitachi Chemical Co., Ltd.
Tunable Ferroelectric Capacitor withLow-Loss Electrodes Fabricated using ReverseSide ExposureYong-Kyu Yoon Yoon and Mark Allen – GeorgiaInstitute of Technology
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Wednesday, May 28 andThursday, May 29Sessions 37 and 38: Posters1:30 p.m. - 6:00 p.m.Committee: Posters
Session Co-Chairs:Michael Caggiano – Rutgers UniversityTel: +1-732-445-0678 Fax: +1-732-445-2820Email: [email protected]
Swapan Bhattacharya – GeorgiaInstitute of TechnologyTel: +1-404-385-0708 Fax: +1-404-894-0957Email: [email protected]
Testing Technique for Early Evaluation ofCompression or Land Grid ArrayConnectorsWilliam Brodsky – IBM Corporation
Design of RF and Wireless Packages UsingFast Hybrid Electromagnetic/StatisticalMethodsNathan Bushyager and Manos Tentzeris –Georgia Institute of Technology; Lara Martin –Motorola, Inc.
Test Structure Free Modeling Method forDe-embedding the Effects of Pads onDevice ModelingCheolung Cha, Zhaoran Huang, Nan M.Jokerst, and Martin A. Brooke – GeorgiaInstitute of Technology
Microwave Curing of AnisotropicConductive Film - Effects of PrincipalParameters on Curing SituationKai Kay Chan, Nin Hong Yeung,Yan CheongChan, Sai Choo Tan, and Ka Ka Lee – CityUniversity of Hong Kong
Innovative Method of Resolving AdhesionIssues on Between Molding Compoundand SubstrateDennis Prem Kumar Chandran and MohdJaffri Razai – Intel Technology Sdn. Bhd.; FweiKeat Yap – Intel Technology
RF Evaluation of Low-Cost LeadlessPackages and Development of DistributedElectrical ModelsArun Chandrasekhar, Eric Beyne, and WalterDe Raedt – IMEC vzw; Bart Nauwelaers –Katholieke Universiteit Leuven
Electronics and the EnvironmentHarry Charles – The Johns HopkinsUniversity
Fracture Toughness of Cu-Sn IntermetallicCompounds in Electronic PackagesZhong Chen and Tommy Cahyadi – NanyangTechnological University; Bavani Balakrisnanand Chan Choy Chum – Institute of MaterialsResearch and Engineering; Ming Li – PhotonicPackaging Lab, Chinese University of HongKong
Study of IMC Morphologies and PhaseCharacteristics Affected by the Reactionsof Ni and Cu Metallurgies with Pb-FreeSolder JointsWon Kyoung Choi, Sung K Kang,Yoon CSohn, and Da-Yuan Shih – IBM Corporation
Intermittency Study of a Stressed MetalMicro-Spring Sliding Electrical ContactEugene Chow, Kevin Klein, David K. Fork, andThomas Hantschel – Palo Alto ResearchCenter (PARC)
Microwave Bonding of Silicon Dies withThin Metal Films for MEMS ApplicationsJason Clendenin and Steve Tung – Universityof Arkansas
Characterization of Intermetallic Aging inFine-Pitch Lead-Free Flip Chip JointsPaul Conway, Dezhi Li, and Paul Conway –Loughborough University
Optimization of Variable FrequencyMicrowave Curing Using Neural Networksand Genetic AlgorithmsCleon Davis,T. Sung, and Ravi Tanikella –Georgia Institute of Technology
RLC Effects in Fine Pitch AnisotropicConductive Film ConnectionsGuang Bin Dou,Yan Cheong Chan, and NinHong Yeung – City University of Hong Kong;James E. Morris – Portland State University
Optimization of Stencil Printing WaferBumping for Fine-Pitch Flip ChipApplicationsJing-Feng Gong, Esther Yau, Philip Chan, RickyLee, and Matthew Yuen – Hong KongUniversity of Science and Technology
A High-Throughput OEO SwitchImplemented in a Single BGA PackageIchiro Hatakeyama,Takashi Yoshikawa,Kazunori Miyoshi, Kei Tanaka, Junich Sasaki,Takara Sugimoto, and Kazuhiko Kurata – NECCorporation; Hideki Tanaka – NECEngineering, Ltd.
Investigations of Void Forming and ShearStrength of Sn42Bi58 Solder Joints for LowCost ApplicationsThomas Herzog, Klaus-Jürgen Wolter, andFrank Poetzsch – Dresden University ofTechnology
Variations in Package Radiation Due toChanges in On-Die and On-PackageCapacitanceMichael J. Hill and Jiangqi He – IntelCorporation
Optical Solder Effects of Self-WrittenWaveguides in Optical Circuit DevicesCouplingNaohiro Hirose and Osamu Ibaragi –Association of Super-Advanced ElectronicsTechnologies (ASET)
Spinning and Shocking SMT Devices;Results of Centrifuge and Hi-G Testing forMilitary ApplicationsTerri Houston, Jim Mills, Jonathan Carter, andEmad Zidan – ATK
A Limiting Amplifier Module Using WaferLevel Package for 10Gbps OpticalTransmission SystemChul-Won Ju, Kyu-Ha Pack, Hee-Tae Lee,Eun-Su Nam, and Kyoung-Ik Joe – ETRI
Crack Length and Orientation Analysis ofSnPb and SnAg Solder Joints in Plastic BallGrid Array Packages from Dye PenetrationStudiesDonghyun Kim, Changyoung Park, GlennMasada, and Tess Moon – University of Texasat Austin; Jose Dias – Universite Federal deMinas Gerais Brazil; Andrew Mawer –Semiconductor Products Sector, Motorola Inc.
Electrical Analysis and Simulation Solutionfor RF SAW Filter PackageDongyoung Kim, Sungkil Hwang, and HeuisungJang – LG innotek
Characteristics of the Pb-free Solder Bumpon Electroless Ni Under BumpMetallurgiesNamseog Kim, Jangwon Han, and Seyong Oh– Samsung Electronics Co. Ltd.
Model-Based Alignment of WaveguideArraysSue Law and Leon Poladian – University ofSydney
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Electrical Effects of Floating Plane inMultiple Power PlanesDong-Ju Lee,Yong-Ju Kim, Jong-Ho Jang,Kun-Woo Park,Young-Suk Suh, Hwa-Jung Kim,and Kwang-yoo Byun – Hynix Semiconductor
A New Efficient Equivalent CircuitExtraction Method for Multi-Port HighSpeed Package using Multi-InputMulti-Output Transmission Matrix andPolynomial Curve FittingHeeseok Lee, Kiwon Choi, Kyoung-Lae Jang,and Taeje Cho – Samsung Electronics Co. Ltd.
Characterization of High-FrequencyPlane-to-Plane Coupling Through Cutoutin Multi-Layer PackagesJunwoo Lee and Joungho Kim – KoreaAdvanced Institute of Science and Technology(KAIST); Mui Seng Yeo, Mihai Dragos Rotaru,and Mahadevan K. Iyer – Institute ofMicroelectronics (IME)
Accurate Predictions of Flip Chip BGAWarpageYuan Li – Altera Corporation
Intelligent Network Communicator: HighlyIntegrated System-On-Package (SOP)Testbed for RF/Digital/Opto ApplicationsKyutae Lim, Mekita F. Davis, Moonkyun Maeng,Stephane Pinel, Lixi Wan, Joy Laskar, VenkySundatam, George E.White, MadhavanSwaminathan, and Rao R.Tummala – GeorgiaInstitute of Technology
Prediction of Interfacial DelaminationFailures of a Stacked IC Structure UsingCombined Experimental and SimulationMethodsChuanjun Liu and L. J. Ernst – Delft Universityof Technology; Guoqi Zhang, M.Van Gils, andR.Van Silfhout – CFT Philips; W.Van Driel –Philips Semiconductors
Delamination Modeling for IC Packagewith Multiple Initial CracksYong Liu, Scott Irving, Mark Rioux, AndrewSchoenberg, and Ewe Lim – FairchildSemiconductor Corporation
Analysis of Flip Chip Packaging Challengeson Copper Low-k InterconnectsLei Mercado, Cindy Goldberg, Shun-MeenKuo,Tien-Yu Lee, and Scott Pozder –Motorola, Inc.
Adhesion of Thermoplastic ConductiveAdhesives Under Humid Environment ByIncorporating Self-Assembled MonolayerMoleculeKyoung-sik Moon, Chris Rockett, and C. P.Wong – Georgia Institute of Technology;William Burgoyne and Christine Kretz – AirProducts and Chemicals, Inc.
Unique White LED Packaging SystemsAtsushi Okuno,Yoshiteru Miyawaki andNoritaka Oyama – Sanyu Rec Co., Ltd.
Degradation Factors for Eye DiagramsUsing FDTD-SPICENeven Orhanovic, Dileep Divekar, and NorioMatsui – Applied Simulation Technology
Digital Speckle Correlation Method forThermal Deformation Analysis of a FlipChip AssemblyJohn H. L. Pang and X. R. Zhang – NanyangTechnological University; X. Q. Shi – SingaporeInstitute of Manufacturing Technology
Microwave Measurements on DielectricConstantsJeong Park and Chin Lee – University ofCalifornia, Irvine
Multilayer Power Delivery Network Designfor High-Speed Microprocessor SystemSeong-Geun Park, Jong-Gwan Yook, andHan-Kyu Park – Yonsei University; JiSeongKim – Samsung Electronics Co. Ltd.
Measurement and Prediction of Reliabilityfor Double-Sided Area Array AssembliesJames Pitarresi and Satish Parupalli – StateUniversity of New York at Binghamton;Anthony Primavera and Mike Meilunas –Universal Instruments Corp; Shiva KalyanMandepudi – Binghamton University
Use of Dendrimers to ControlNanoparticle Size in Polymer-MetalNanocomposites for Embedded CapacitorApplicationSuresh Pothukuchi and C. P. Wong – GeorgiaInstitute of Technology
Comparison of the Adhesion Strength ofEpoxy- and Silicone-Based ThermalInterface MaterialsAnanth Prabhakumar and K. Srihari – StateUniversity of New York at Binghamton; AnnitaZhong, Sandeep Tonapi, Donna Sherman,Herbert Cole, and Florian Schattenmann – GEGlobal Research
A Neural Network Model for SensitivityAnalysis of Circuit Parameters for FlipChip InterconnectsRana Pratap, Stephane Pinel, DanielaStaiculescu, and Joy Laskar – Georgia Instituteof Technology
Copper Foils for High-Density IC Packages- Starting from Foil/Dielectric AdhesionShichun Qu – 3M Company
Optimization and Stochastic Proceduresfor Robust Design of Photonic Packageswith Applications to a GenericOptoelectronic PackageSatish Radhakrishnan and Ganesh Subbarayan– Purdue University; Luu Nguyen and WilliamMazotti – National SemiconductorCorporation
Design and Electrical Characterization ofa Novel Wafer Level Package for RFMEMS ApplicationsMihai Rotaru, C. S. Premachandran, and IyerMahadevan – Institute of Microelectronics(IME)
Viscoelastic Properties of Underfill forNumerical Analysis of Flip Chip PackagesMan-Lung Sham and Jang-Kyo Kim – HongKong University of Science and Technology;Joo-Hyuk Park – Sejong University
Thermal-Electrical Simulations forTwo-Node Optoelectronics ModulesLei Shan – IBM Corporation
Comparison of Electrical Interconnect andOptical InterconnectJaemin Shin, Chung-Seok Seo,AnanthasayanaChellappa, Martin Brooke,Abhijit Chatterjee,and Nan M. Jokerst – Georgia Institute ofTechnology
Impact of Ingressed Moisture and HighTemperature Warpage Behavior on theRobust Assembly Capability for LargeFootprint PBGAsRichard Shook, Jeff Gilbert, Ebyson Thomas,Adesoji Dairo, Brian Vaccaro, and DaveCrouthamel – Agere Systems
Electrical and Mechanical Properties ofCarbon Black Filled Ethylene PropyleneRubber during Thermo-Oxidation AgingYangyang Sun – Georgia Institute ofTechnology; Shijian Luo – Micron Technology,Inc.
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Lead-Free Wave Soldering Developmentfor PCB AssemblyVasudivan Sunappan and Peter Collier –Singapore Institute of ManufacturingTechnology (SIMTech)
Thermal Limits in Reflow SolderingProcessPaul Svasta, Daniel Simion-Zanescu, and PabloReyes-Turcu – Politehnica University ofBucharest
Demonstration of a Microwave Analogueto a Subwavelength All Optical SwitchLuke Sweatlock and Harry Atwater – HarvardUniversity; Stefan Maier – California Instituteof Technology
A Study on Epoxy-Based High-kComposite for Embedded Capacitor withSilver Fillers Coated Self AssemblyMonolayer Insulating MaterialsKe Tang,Yang Rao, Lianhua Fan, and C. P.Wong – Georgia Institute of Technology
Lead-Free Solder Bumping Process forHigh Temperature Automotive ApplicationThorsten Teutsch and Ronald G. Blankenhorn– Packaging Technologies, Inc.; Elke Zakel –Packaging Technologies, Inc., GmbH
Development of Microwave Devices andModules on Liquid Crystal Polymer (LCP)Substrates for SOP ApplicationsDane Thompson, John Papapolymerou, andManos Tentzeris – Georgia Institute ofTechnology
Interfacial Interactions of Lead-FreeSolder Alloys and the Effect of PCB Finishon Mechanical PropertiesChee Meng Thong and Guoyuan Li – NanyangTechnological University; Andrew Spowage –SIMTech; Peter Collier – Singapore Institute ofManufacturing Technology (SIMTech)
Development of Low Stress Materials ForLow-k Copper Integrated CircuitPackagingMichael Todd, Larry Crane, George Carson,Jack Zhang,Vincent Villeda, and Kathy Costello– Henkel Loctite Corporation
Interfacial Adhesion Analysis of BCB / TiW/ Cu / PbSn Technology in Wafer LevelPackagingMichael Toepper and Herbert Reichl –Fraunhofer Institute for Reliability andMicrointegration IZM; Albert Achen – DowDeutschland GmbH & Co. OHG,Rheinmünster, Germany
A Thermal Aging Study on Both Au-Cu andAu-Al Wire-Bonded InterfacesTu Anh Tran, Lois Yong, Fuaida Harun, and C.C.Yong – Motorola
Qualitative Analysis of CoupledTransmission LinesWenliang Tseng, Sonfu Yeh, and Huang Pojen –National Central University; Chauchin Su –National Chiao Tung University
Application of Embedded EdgeTerminations to Reduce the EdgeRadiation and Noise in High-SpeedPrinted Circuit BoardsSujeet Vaidya – SUNY-Binghamton/GeorgiaInsitute of Technology; Virendra Adsure –SUNY-Binghamton/Eastman Kodak; MadhavanSwaminathan – Georgia Insitute ofTechnology; Harry Kroger – SUNY -Binghamton
Optimal Choice of the FEM DamageVolumes for Estimation of the Solder JointReliability for Electronic PackageAssembliesBart Vandevelde, Mario Gonzalez, and EricBeyne – IMEC; Kouchi Zhang and Jo Caers –Philips CFT
Advanced Equipment Control (AEC) - UseKnowledge Management Concept inSemiconductor EquipmentJong Wang and Min-Liang Huang – Yuan-ZeUniversity
Technique and Equipment for a Rework ofFlip Chip with No Flow UnderfillerKlaus Wolter and Gunter Kuerbis – DresdenUniversity of Technology
Optimization of Electroplating, StencilPrinting, Ball Placement Solder-BumpingFlip Chip Process TechnologiesGuo-Wei Xiao, Jing-Feng Gong, Esther Yau,Philip Chan, Ricky Lee, and Matthew Yuen –Hong Kong University of Science andTechnology
A New Low-Cost Optical TransmitterPackage with Uncooled Thermal Solutionand J-Down AssemblyLing Xie, Damaruganath Pinjala,Krishnamachari Sudharsanam, and MahadevanK. Iyer and Ramana Pamidighantam – Instituteof Microelecttronics (IME); Eitaro Ishimura –Mitsubishi Electric Corporation, Japan
High-Precision Adhesives for Free SpaceMicro-Optics ApplicationsFrank Xu – Chorum Technologies
TopFinder: A New and Efficient Tool forTopology Construction and ParameterExtraction for RF/Microwave TransistorsMustapha Yagoub and Mustapha Yagoub –University of Ottawa
Evaluation of the Oven Reflow Bondingand the Thermo-Compression Bonding ofLead-Free Sn0.7Cu Solder Bumps onLow-Cost FR-4 Substrate for Flip ChipApplicationsEsther Yau, Fung Wa Hong, and Philip C. H.Chan – Hong Kong University of Science andTechnology
Efficient Inductance Calculation withGround PlaneYu-Ting Yeh, Jack Ou, and Michael F. Caggiano– Rutgers University
Effect of Void in the AnisotropicConductive AssembliesNin Hong Yeung, Yan Cheong Chan, Sai ChooTan, Ka Ka Lee, and Kai Kay Chan – CityUniversity of Hong Kong
Magnetic/Semiconductor MultilayerMillimeter-Wave Bandstop FilterHui Jae Yoo, Chin C Lee, Chen S.Tsai, andFranco De Flaviis – University of California,Irvine
Lead-Free Solder Bump Evaluation onLarge Die Flip Chip ApplicationLeilei Zhang, Lan Hoang, and AbhayMaheshwari – Xilinx
Viscoplastic Constitutive Properties andEnergy-Partitioning Durability Model ofPb-Free Sn3.9Ag0.6Cu Solder AlloyQian Zhang,Abhijit Dasgupta, and PeterHaswell – University of Maryland
Design, Material and Process Optimizationfor a New Thermally Enhanced BGA -C2BGATiao Zhou, Claudio Villa, and Haibin Du –STMicroelectronics, Inc.
3D Nonlinear Thermal Stress Analysis ofVCSEL Assemblies with Lead-Free SolderFlip Chip InterconnectsYida Zou – Cisco Systems; John H. Lau –Agilent Technologies, Inc.
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53rd ECTC CorporateConference Sponsors
How To Register
By Internet: Submit your registration electronically viawww.ectc.net/reg.htm. Your registration must be received bythe cutoff date, May 12, 2003, to qualify for the early registra-tion discounts.
By Mail: Return your completed registration form toEIA/ECA, 2500 Wilson Boulevard, Arlington,VA 22201-3834with payment by company check, money order, or credit card.Your registration must be received by the cutoff date to qualifyfor the early registration discounts.
By Fax: Fax your completed registration form with creditcard payment to (703) 875-8908. Your fax must be received bythe cutoff date to qualify for the early registration discounts.
Sheraton New Orleans Hotel53rd Electronic Components and Technology Conference • May 27 - 30, 2003
Detach and return to the Sheraton New Orleans Hotel Reservations Department, 500 Canal Street, New Orleans, LA 70130
Print or Type
Name(s) Company
Address M/S
City State/Country Zip
Telephone Fax Signature
____Main House 1-2 Person $155.00 plus tax____Club Level 1-2 Person $175.00 plus tax ____No Smoking ____Handicapped$25.00 additional charge per person(4 people maximum per room)
All reservations must be guaranteed for late arrival with a credit card or one night’s deposit plus 12% tax.(a) Enclosed is a check or money order for $_______________(make check payable to Sheraton New Orleans Hotel)(b) Credit card for guarantee (check credit card used) ___ Am. Ex ___ Discover ___ MC ___ Visa
Card # ______________________________________________________________________
Print name as shown on card ____________________________________________________
Expiration Date ___________ Signature ___________________________________________
No penalty on reservations cancelled 72 hours prior to date of arrival. Deposits are non-refundable if reservations are cancelled within 72 hours of arrival.
(Rate does not include tax. 12% Room Tax and $3.00 Occupancy Tax Apply.) If requested rate is not available, next available rate will be confirmed.Reservations received after April 28, 2003 will be on a space and rate availablebasis. The Sheraton New Orleans Hotel phone # is 504-525-2500 or toll free 1-800-253-6156. Fax # is 504-595-5550.
Hotel reservations are to be made with hotel only.
53rd Electronic Components & Technology ConferenceAdvance Registration Form
Send your advance registration to EIA/ECA, 2500 Wilson Boulevard, Arlington,VA 22201-3834 or fax (credit card only)(703) 875-8908 to be received no later than May 12, 2003. You may call (703) 907-8027 for additional information.
On-line registration is available at www.ectc.net/reg.htm
Last Name Badge First Name First Name Title
Company Mail Stop
Address City State/Country Zip
Telephone Fax #
ECTC Advance RegistrationCheck one or more of the following:Registration includes printed proceedings or CD-ROM(see below) and lunch each day:
IEEE Member * No. __________________ . . . . . . . . . . . .$450
Non-Member* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$550
One Day (Circle W T F ) . . . . . . . . . . . . . . . . . . . . . . . . . .$350
Speaker/Session Chair* Session#___________ . . . . . . . . .$350
Speaker/One Day . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$225
Student . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$125
* Door Registration will be an additional $100As part of my registration fee, I request:the printed proceedings orthe CD-ROM orboth ($50.00 additional fee)
Professional Development Course Registration
Single AM or PM Short Course includes luncheon . . . .*$325
AM & PM Short Course includes luncheon . . . . . . . . .*$525
Student (AM and/or PM Short Course) includes luncheon . . . .$50
Check course(s) you plan to attend (Pages 10-14)
AM Courses 1___ 2___ 3___ 4___ 5___ 6___ 7___
PM Courses 8___ 9___ 10___ 11___ 12___ 13___ 14___
*Door rate will be an additional $50.
** See hours of registration on Advance Registration page 3.
IMPORTANT TO REGISTER IN ADVANCE TO AVOID DELAYS AT
REGISTRATION DESK. COURSE SIZES LIMITED.
Join IEEE and the Components, Packaging and Manufacturing Technology Society and Save!• Non-IEEE members can join IEEE and save $100 on ECTC registration and receive CPMT Society membership free for 2003.• IEEE members can join the CPMT Society free for the remainder of 2003 with ECTC registration.A membership application must be completed to obtain an IEEE member number before sending registration form to EIA. For details contact Marsha Tickman, IEEE CPMT Society, phone 732-562-5529,fax 732-981-1769, email: [email protected] or visit the CPMT booth in the ECTC Registration area if registering at the door.
Credit Card and Payment InformationPlease make all checks for Advance Registration payable to the 53rd ECTC. Mail your check together with this form to EIA/ECA,2500 Wilson Blvd., Arlington,VA 22201-3834. There will be no refunds on cancellations after May 12, 2003. Substitutions can be made at anytime. DO NOT MAIL CHECKS AND REGISTRATIONS TO ANY OTHER ADDRESS. You may fax this form and your credit card information to:(703) 875-8908.
Coffee Break Sponsor . . . . . . . .$350
Printed Proceedings & CD-ROM OnlyU.S. postpaid . . . . . . . . . . . . . . . . . . . . . . . . . . .$300
Foreign via air mail . . . . . . . . . . . . . . . . . . . . . . .$350
MC Visa AMX
Credit Card #
Signature
Exp. date
If a selection is not made,you will receive a CD.
Extra Luncheon Tickets#_____ Wed. $38 each#_____ Thur. $38 each#_____ Fri. $38 each
Please indicatehow many
luncheon ticketsare needed.
PRIMARY AREA OF INTEREST (Check One)___Advanced Packaging ___Interconnections ___Modeling & Simulation___Components & RF ___Manufacturing Technology ___Optoelectronics___Connectors & Contacts ___Materials & Processing ___Quality & Reliability
Academic Workshop RegistrationAcademic Workshop, includes luncheonAcademic Workshop participants must register for aminimum one day’s attendance at the ECTC Conference.
Please also check the applicable fee in the ECTC Advance Registration section.
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Electronic Industries Alliance2500 Wilson Boulevard
Arlington,VA 22201-3834
FIRST CLASSU.S. POSTAGE
PAIDGREENVILLE, SCPERMIT NO. 113
Sponsored by:
Electronic Industries Alliance2500 Wilson Boulevard
Arlington,VA 22201-3834a
PAR AVION
INTERNATIONAL PRIORITY AIRMAIL
FIRST CLASSU.S. POSTAGE
PAIDGREENVILLE, SCPERMIT NO. 113
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