introduction to assembly language...

4/20/2009

1

INTRODUCTION TO

ASSEMBLY LANGUAGE PROGRAMMING

CS271

Introduction to Assembly Language Programming

INTEL ARCHITECTURE: IA-32

IA-32 BASICS

Two processors in one

integer unit

floating-point unit

can work in parallel (co-processors)

Separate instruction sets

Separate data registers

different configuration

Separate ALUs

4/20/2009

2

MODES OF OPERATION

Real-address mode

native MS-DOS

Protected mode

native mode (Windows, Linux)

Virtual-8086 mode

hybrid of Protected

each program has its own 8086 computer

System management mode

power management, system security, diagnostics

BASIC EXECUTION ENVIRONMENT

Addressable memory

General-purpose registers

Index and base registers

Specialized register uses

Status flags

Floating-point, MMX, XMM registers

ADDRESSABLE MEMORY

Protected mode

4 GB

32-bit address

Real-address and Virtual-8086 modes

1 MB space

20-bit address

4/20/2009

3

GENERAL-PURPOSE REGISTERS

EBP

ESP

ESI

EDI

EBX

ECX

EDX

EAX

32-bit General Purpose Registers

EFLAGS

EIP

ES

FS

GS

CS

SS

DS

16-bit Segment Registers

ACCESSING PARTS OF REGISTERS

Use 32-bit, 16-bit or 8-bit names

Applies to EAX, EBX, ECX, EDX

EAX 32-bit

AX 16-bit

AH AL 8-bit + 8-bit

INDEX AND BASE REGISTERS

Some registers on have 16-bit names for their

lower halves

32-bit 16-bit

ESI SI

EDI DI

EBP BP

ESP SP

4/20/2009

4

SPECIAL USES (1 OF 2)

EAX – accumulator

ECX – loop counter

ESP – stack pointer

ESI, EDI – index registers

EBP – extended base pointer (stack)

SPECIAL USES (2 OF 2)

CS – code segment

DS – data segment

SS – stack segment

ES, FS, GS – additional segments

EIP – instruction pointer

EFLAGS

status and control flags

each flag is a single binary bit

STATUS FLAGS

Carry unsigned arithmetic out of range

Overflow signed arithmetic out of range

Sign result is negative

Zero result is zero

Auxiliary Carry carry from bit 3 to bit 4

Parity sum of 1 bits is an even number

4/20/2009

5

FLOATING-POINT, MMX, XMM REGISTERS

Eight 64-bit registers for use with MMX

Eight 128-bit registers for use with XMM SIMD operations

ST(0)

ST(1)

ST(2)

ST(3)

ST(4)

ST(5)

ST(6)

ST(7)

80-bit Data Registers

Opcode Register

FPU Instruction Pointer

FPU Data Pointer

48-bit Pointer Registers

Tag Register

Control Register

Status Register

16-bit Control Registers


A BRIEF HISTORY OF INTEL PROCESSORS

EARLY INTEL MICROPROCESSORS

Intel 8080

64K addressable RAM

8-bit registers

CP/M operating system

S-100 BUS architecture

8-inch floppy disks!

Intel 8086/8088

IBM-PC Used 8088

1 MB addressable RAM

16-bit registers

16-bit data bus (8-bit for 8088)

separate floating-point unit (8087)

4/20/2009

6

THE IBM-AT

Intel 80286

16 MB addressable RAM

Protected memory

several times faster than 8086

introduced IDE bus architecture

80287 floating point unit

INTEL IA-32 FAMILY

Intel386

4 GB addressable RAM, 32-bit registers, paging (virtual

memory)

Intel486

instruction pipelining

Pentium

superscalar, 32-bit address bus, 64-bit internal data

path

INTEL P6 FAMILY

Pentium Pro

advanced optimization techniques in microcode

Pentium II

MMX (multimedia) instruction set

Pentium III

SIMD (streaming extensions) instructions

4/20/2009

7

INTEL NETBURST ARCHITECTURE

Pentium 4 and Xeon

Intel NetBurst micro-architecture, tuned for

multimedia

INTEL IA-64 FAMILY

Itanium

Itanium 2

Pentium 4F

Pentium D

Pentium Extreme Edition

Xeon

CORE ARCHITECTURE FAMILY

Xeon

Intel Core 2 Duo / Quad

2 to 4 cores on single die

Pentium Dual Core

Celeron M

Core i7

front side bus replaced with QuickPath up to 6.4GT/s

781 million transistors

4/20/2009

8

REVIEW (1 OF 3)

1. What are the IA-32 processor’s three basic

modes of operation?

2. Name all eight 32-bit general purpose

registers

3. Name all six segment registers

4. What special purpose does the ECX register

serve?

5. Name at least four CPU status flags

REVIEW (2 OF 3)

6. Which flag is set when the result of an

unsigned arithmetic operation is too large to

fit into the destination?

7. Which flag is set when the result of an signed

arithmetic operation is either too large or too

small to fit into the destination?

8. Which flag is set when an arithmetic or logical

operation generates a negative result?

REVIEW (3 OF 3)

9. Which part of the CPU performs floating-point

arithmetic?

10. How many bits long are the FPU data

registers?

11. Describe the CISC approach

12. Describe the RISC approach

4/20/2009

9


IA-32 MEMORY MANAGEMENT

IA-32 MEMORY MANAGEMENT

Real-address mode

Calculating linear addresses

Protected mode

Multi-segment model

Paging

REAL-ADDRESS MODE

1 MB RAM maximum addressable

Application programs can access any area of

memory

Single tasking

Supported by MS-DOS operating system

4/20/2009

10

SEGMENTED MEMORY

00000

10000

20000

30000

40000

50000

60000

70000

80000

90000

A0000

B0000

C0000

D0000

E0000

F0000

8000:0000

8000:FFFF

8000:0250

0250

seg off

Lin

ea

r A

dd

ress

CALCULATING LINEAR ADDRESSES

Given a segment address, multiply it by 16 (add

a hexadecimal zero), and add it to the offset

Example: convert 08F1:0100 to a linear

address

Adjusted Segment value: 0 8 F 1 0

Add the offset: 0 1 0 0

Linear address: 0 9 0 1 0

PROTECTED MODE (1 OF 2)

4 GB addressable RAM

(0000 0000 to FFFF FFFFh)

Each program assigned a memory partition

which is protected from other programs

Designed for multitasking

Supported by Linux & MS-Windows

4/20/2009

11

PROTECTED MODE (2 OF 2)

Segment descriptor tables

Program structure

code, data, and stack areas

CS, DS, SS segment descriptors

global descriptor table (GDT)

MASM Programs use the Microsoft flat memory

model

FLAT SEGMENT MODEL

In flat model all segments are mapped to entire 32-bit address space

At least 2 segments required:

code

data

Each segment is defined by a segment descriptor

Segment descriptor is a 64-bit number stored in the global descriptor table (GDT)

GLOBAL DESCRIPTOR TABLE

no

t use

dp

hys

ica

l RA

M

FFFF FFFF

(4GB)

0000 0000

0000 0000 0 0040

base address limit

- - -

access

0004 0000

4/20/2009

12

MULTI-SEGMENT MODEL

Each process is given its own table of segment

descriptors call a Local Descriptor Table (LDT)

Each segment has its own address space

Each segment descriptor describes the exact

size of its segment

LOCAL DESCRIPTOR TABLE

3000

RAM

8000

2 6000base limit access

0002 6000 0 0010 - - -0000 8000 0 00A0 - - -0000 3000 0 0002 - - -

Local Descriptor Table

PAGING

Supported directly by the CPU

Divides each segment into 4096-byte blocks called pages

Sum of all programs can be larger than physical memory

Part of running program is in memory, part is on disk

Virtual memory manager (VMM) – OS utility that manages the loading and unloading of pages

Page fault – issued by CPU when a page must be loaded from disk

4/20/2009

13

REVIEW (1 OF 3)

1. What is the range of addressable memory in protected mode?

2. What is the range of addressable memory in read-address mode?

3. In real-address mode, convert the following hexadecimal segment-offset address to a linear address: 0950:0100

4. In real-address mode, convert the following hexadecimal segment-offset address to a linear address: 0CD1:02E0

REVIEW (2 OF 3)

5. In the flat memory model, how many bits hold the address of an instruction or variable?

6. In protected mode, which register references the descriptor for the stack segment?

7. In protected mode, which table contains pointers to the memory segments used by a single program?

8. In the flat memory model, which table contains pointers to at least two segments?

REVIEW (3 OF 3)

9. What is the main advantage to using the

paging feature of IA-32 processors?

10. Can you think of a reason why MS-DOS was

not designed to support protected-mode

programming?

11. In real-address mode, demonstrate two

segment-offset address that point to the same

linear address

4/20/2009

14


INPUT-OUTPUT SYSTEM

INPUT-OUTPUT SYSTEM

Applications routinely read input from keyboard

and disk files and write output to files and

screen

I/O is available at different access levels:

high-level languages

operating system

BIOS

HIGH-LEVEL LANGUAGE (HLL) I/O

HLL such as C++ or Java contain functions for

performing I/O

System.out.println("Hello World!");

cout << "Hello World!" << endl;

These functions are portable as they work on a

variety of computer systems and are not

dependant on any one operating system

4/20/2009

15

OPERATING SYSTEM I/O

Programmers can call operating system (OS)

functions from a library known as the

Application Programming Interface (API)

OS provides high-level operations such as:

writing strings to files

reading string from the keyboard

allocating blocks of memory

BIOS I/O

The Basic Input/Output System (BIOS) is a

collection of low-level subroutines that

communicate directly with hardware

The BIOS is installed by the computer’s

manufacturer and is tailored to fit the

computers hardware

Operating systems generally communicate with

the BIOS

DEVICE DRIVERS

Software that communicates directly with a

piece of hardware

Allows devices unknown to the BIOS to be

integrated with the computer

Works much like BIOS providing I/O functions

tailored to a particular device or family of

devices

4/20/2009

16

I/O HIERARCHY

Level 4 •Statement in program calls HLL library function to write string to standard output

Level 3•Library function calls an OS function, passing a string pointer

Level 2

•OS uses a loop to call a BIOS subroutine, passing it the ASCII code and color of each character; OS also calls BIOS subroutine to advance cursor to next position on screen

Level 1

•BIOS receives character, maps it to a particular system font, and sends it to hardware port attached to video card

Level 0

•Video card generated timed hardware signals to the monitor that control the displaying of pixels

PROGRAMMING AT MULTIPLE LEVELS

Assembly language programs can choose to use any of the following levels

level 3: call library functions to perform I/O (we will do this, at least to begin)

level 2: call OS functions to perform text and file-based I/O

level 1: Call BIOS functions to control device-specific features such as color, graphics, and keyboard input

level 0: send and receive data from hardware ports

TRADEOFFS – LEVEL 2

Programming at level 2 works on any computer

running a given OS

If a device lacks a certain capability the OS do

its best to approximate it

Level 2 is not particularly fast because each I/O

call must go through several layers before it

executes

4/20/2009

17


Works on all systems having a standard BIOS but will not produce the same result on all systems

different systems may run at different resolutions

As a programmer you must write code to detect the user’s hardware and adjust your program to match

Much faster than level 2 as it is only one level above the hardware


Works with generic devices such as serial ports and with specific I/O devices produced by known manufacturers

Programs must be written to handle variations in I/O devices

Programs execute quickly as they are directly manipulating the hardware

Not all OS allow this level of access to hardware (Windows XP, Vista, 7, 2000, etc)

REVIEW

1. Of the three levels of I/O, which is the most

universal and portable?

2. What characteristics distinguish BIOS-level I/O?

3. Why are device drivers necessary, given that the

BIOS already has code that communicates with

the computer’s hardware?

4. Is it likely that the BIOS for a computer running

Windows would be different from that used by a

computer running Linux?

introduction to assembly language...

Documents