introduction to asynchronous circuit design: specification and synthesis
DESCRIPTION
Introduction to asynchronous circuit design: specification and synthesis. Jordi Cortadella, Universitat Politècnica de Catalunya, Spain Michael Kishinevsky, Intel Corporation, USA Alex Kondratyev, Theseus Logic, USA Luciano Lavagno, Università di Udine, Italy. Outline. - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/1.jpg)
Introduction to asynchronous circuit design:
specification and synthesis
Jordi Cortadella, Universitat Politècnica de Catalunya, Spain
Michael Kishinevsky, Intel Corporation, USA
Alex Kondratyev, Theseus Logic, USA
Luciano Lavagno, Università di Udine, Italy
![Page 2: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/2.jpg)
Outline
• I: Introduction to basic concepts on
asynchronous design
• II: Synthesis of control circuits from STGs
• III: Advanced topics on synthesis of controlcircuits from STGs
• IV: Synthesis from HDL and other synthesis paradigms
Note: no references in the tutorial
![Page 3: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/3.jpg)
Introduction toasynchronous circuit design:
specification and synthesis
Part I:
Introduction to basic concepts on asynchronous circuit design
![Page 4: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/4.jpg)
Outline
• What is an asynchronous circuit ?
• Asynchronous communication
• Asynchronous logic blocks
• Micropipelines
• Control specification and implementation
• Delay models
• Why asynchronous circuits ?
![Page 5: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/5.jpg)
Synchronous circuit
R R R RCL CL CL
CLK
Implicit synchronization
![Page 6: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/6.jpg)
Asynchronous circuit
R R R RCL CL CL
Explicit synchronization: Req/Ack handshakes
Req
Ack
![Page 7: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/7.jpg)
Synchronous communication
• Clock edges determine the time instants where data must be sampled
• Data wires may glitch between clock edges (set-up/hold times must be satisfied)
• Data are transmitted at a fixed rate(clock frequency)
1 1 0 0 1 0
![Page 8: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/8.jpg)
Dual rail
• Two wires per bit– “00” = spacer, “01” = 0, “10” = 1
• n-bit data communication requires 2n wires
• Each bit is self-timed
• Other delay-insensitive codes exist
1 1
0 0
1
0
![Page 9: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/9.jpg)
Bundled data
• Validity signal– Similar to an aperiodic local clock
• n-bit data communication requires n+1 wires
• Data wires may glitch when no valid
• Signaling protocols– level sensitive (latch)– transition sensitive (register): 2-phase / 4-phase
1 1 0 0 1 0
![Page 10: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/10.jpg)
Example: memory read cycle
• Transition signaling, 4-phase
Valid address
Address
Valid data
Data
A A
DD
![Page 11: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/11.jpg)
Example: memory read cycle
• Transition signaling, 2-phase
Valid address
Address
Valid data
Data
A A
DD
![Page 12: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/12.jpg)
Asynchronous modules
• Signaling protocol:reqin+ start+ [computation] done+ reqout+ ackout+ ackin+reqin- start- [reset] done- reqout- ackout- ackin-
(more concurrency is also possible, e.g. by overlapping the return-to-zero phase of step i-1 with the evaluation phase of step i)
Data IN Data OUT
req in req out
ack in ack out
DATAPATH
CONTROL
start done
![Page 13: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/13.jpg)
Asynchronous latches: C element
CA
BZ
A B Z+
0 0 00 1 Z1 0 Z1 1 1
Vdd
Gnd
A
A
A
AB
B
B
B
Z
Z
Z
![Page 14: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/14.jpg)
Dual-rail logic
A.t
A.f
B.t
B.f
C.t
C.f
Dual-rail AND gate
Valid behavior for monotonic environment
![Page 15: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/15.jpg)
Completion detection
•••
•••
C done
Completion detection tree
![Page 16: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/16.jpg)
Differential cascode voltage switch logic
start
start
A.t
B.t
C.t
A.fB.fC.f
Z.tZ.f
done
3-input AND/NAND gate
![Page 17: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/17.jpg)
Bundled-data logic blocks
•••
•••
delaystart done
logic
Conventional logic + matched delay
![Page 18: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/18.jpg)
Micropipelines (Sutherland 89)
L L L Llogic logic logic
Rin
Aout
C C
C C
Rout
Aindelay
delay
delay
![Page 19: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/19.jpg)
Data-path / Control
L L L Llogic logic logic
Rin RoutCONTROL AinAout
![Page 20: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/20.jpg)
Control specification
A+
B+
A-
B-
A
B
A inputB output
![Page 21: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/21.jpg)
Control specification
A+
B+
A-
B-
A B
![Page 22: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/22.jpg)
Control specification
A+
B-
A-
B+
A B
![Page 23: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/23.jpg)
Control specification
A+
C-
A-
C+A
C
B+
B- B
C
![Page 24: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/24.jpg)
Control specification
A+
C-
A-
C+A
C
B+
B-B
C
![Page 25: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/25.jpg)
Control specification
CC
Ri
Ro
Ai
Ao
Ri+
Ao+
Ri-
Ao-
Ro+
Ai+
Ro-
Ai-
Ri Ro
Ao Ai
FIFOcntrl
![Page 26: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/26.jpg)
A simple filter: specification
y := 0;loop x := READ (IN); WRITE (OUT, (x+y)/2); y := x;end loop
RinAin
Aout Rout
ININ
OUTOUT
filter
![Page 27: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/27.jpg)
A simple filter: block diagram
x y+
controlRin
Ain
Rout
Aout
Rx AxRy Ay Ra Aa
ININOUTOUT
• x and y are level-sensitive latches (transparent when R=1)• + is a bundled-data adder (matched delay between Ra and Aa)• Rin indicates the validity of IN• After Ain+ the environment is allowed to change IN• (Rout,Aout) control a level-sensitive latch at the output
![Page 28: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/28.jpg)
A simple filter: control spec.
x y+
controlRin
Ain
Rout
Aout
Rx AxRy Ay Ra Aa
ININOUTOUT
Rin+
Ain+
Rin-
Ain-
Rx+
Ax+
Rx-
Ax-
Ry+
Ay+
Ry-
Ay-
Ra+
Aa+
Ra-
Aa-
Rout+
Aout+
Rout-
Aout-
![Page 29: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/29.jpg)
A simple filter: control impl.
Rin+
Ain+
Rin-
Ain-
Rx+
Ax+
Rx-
Ax-
Ry+
Ay+
Ry-
Ay-
Ra+
Aa+
Ra-
Aa-
Rout+
Aout+
Rout-
Aout-
C
Rin
Ain
Rx Ax RyAy AaRa
Aout
Rout
![Page 30: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/30.jpg)
Control: observable behavior
Rx+
Rin+
Ax+ Ra+ Aa+ Rout+ Aout+ z+ Rout- Aout- Ry+
Ry- Ay+Rx-Ax-Ay-
Ain-
Ain+
Ra-
Rin-
Aa-z-
C
Rin
Ain
Rx Ax RyAy AaRa
Aout
Rout
z
![Page 31: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/31.jpg)
Taking delays into account
x+
x-
y+
y-
z+
z- xz
yx’
z’
Delay assumptions:• Environment: 3 times units• Gates: 1 time unit
events: x+ x’- y+ z+ z’- x- x’+ z- z’+ y-
time: 3 4 5 6 7 9 10 12 13 14
![Page 32: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/32.jpg)
Taking delays into account
x+
x-
y+
y-
z+
z- xz
yx’
z’
Delay assumptions: unbounded delays
events: x+ x’- y+ z+ x- x’+ y-
time: 3 4 5 6 9 10 11
very slow
failure !
![Page 33: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/33.jpg)
Gate vs wire delay models
• Gate delay model: delays in gates, no delays in wires
• Wire delay model: delays in gates and wires
![Page 34: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/34.jpg)
Delay models for async. circuits
• Bounded delays (BD): realistic for gates and wires.– Technology mapping is easy, verification is difficult
• Speed independent (SI): Unbounded (pessimistic) delays for gates and “negligible” (optimistic) delays for wires.– Technology mapping is more difficult, verification is easy
• Delay insensitive (DI): Unbounded (pessimistic) delays for gates and wires.– DI class (built out of basic gates) is almost empty
• Quasi-delay insensitive (QDI): Delay insensitive except for critical wire forks (isochronic forks).– Formally, it is the same as speed independent
– In practice, different synthesis strategies are used
BD
SI QDI
DI
![Page 35: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/35.jpg)
Motivation (designer’s view)
• Modularity– Plug-and-play interconnectivity
• Reusability– IPs with abstract timing behaviors
• High peformance– Average-case performance (no worst-case delay
synchronization)– No clock skew (local timing assumptions)
• Many interfaces are asynchronous– Buses, networks, ...
![Page 36: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/36.jpg)
Motivation (technology aspects)
• Low power– Automatic clock gating
• Electromagnetic compatibility– No peak currents around clock edges
• Robustness– High immunity to technology and environment
variations (in-die variations, temperature, power supply, ...)
![Page 37: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/37.jpg)
Dissuasion
• Concurrent models for specification– CSP, Petri nets, ...: no more FSMs
• Difficult to design– Hazards, synchronization
• Complex timing analysis– Difficult to estimate performance
• Difficult to test– No way to stop the clock
![Page 38: Introduction to asynchronous circuit design: specification and synthesis](https://reader036.vdocument.in/reader036/viewer/2022081512/56813d04550346895da6a7bb/html5/thumbnails/38.jpg)
But ... some successful stories
• Philips
• AMULET microprocessors
• Sharp
• Intel (RAPPID)
• IBM (interlocked pipeline)
• Start-up companies:– Theseus Logic, Cogency
• ...