introduction to chapter 7 ffs and logic gates are combined to form various counters and registers. ...

Introduction to Chapter 7 FFs and logic gates are combined to form various

counters and registers. Part 1 covers counter principles, various counter

circuits, and IC counters. Part 2 covers several types of IC registers and shift

register counter troubleshooting.

Ronald Tocci/Neal Widmer/Gregory MossDigital Systems: Principles and Applications, 10e

Copyright ©2007 by Pearson Education, Inc.Columbus, OH 43235

All rights reserved..

7-1 Asynchronous (Ripple) Counters Review of four bit counter operation (refer to Figure 7-1)

Clock is applied only to FF A. J and K are high in all FFs.

Output of FF A is CLK of FF B and so forth. FF outputs D, C, B, and A are a 4 bit binary number with

D as the MSB. After the NT of the 15th clock pulse the counter recycles

to 0000. This is an asynchronous counter because state is not

changed in exact synchronism with the clock.




7-1 Asynchronous (Ripple) Counters Schematics are normally drawn from left to right, but

counters will be drawn from right to left so that the MSB and LSB appear in the appropriate positions.

MOD number is equal to the number of states that the counter goes through before recycling. Adding FFs will increase the MOD number.

Frequency division – each FF will have an output frequency of ½ the input. The output frequency of the last FF of any counter will be the clock frequency divided by the MOD of the counter.




7-2 Propagation Delay in Ripple Counters Ripple counters are simple, but the cumulative

propagation delay can cause problems at high frequencies.

For proper operation the following apply: TclockN x tpd

Fmax=1/N x tpd




7-2 Counters with MOD Number <2N

The MOD of a counter can be changed by designing the counter to normal parts of the counting sequence.

Refer to figure 7-4. When outputs B and C are high the counter will be reset.

Notice the “glitch” in the waveform when the count reaches 6. This represents the brief time required to reset the counter.


Copyright ©2004 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

7-4 Counters with MOD Number < 2N

Changing the MOD number. Find the smallest MOD required so that 2N is less than or

equal to the requirement. Connect a NAND gate to the asynchronous CLEAR

inputs of all FFs. Determine which FFs are HIGH at the desired count and

connect the outputs of these FFs to the NAND gate inputs.




7-4 Counters with MOD Number < 2N

Decade counters/BCD counters A decade counter is any counter with 10 distinct states,

regardless of the sequence. Any MOD-10 counter is a decade counter.

A BCD counter is a decade counter that counts from binary 0000 to 1001.

Decade counters are widely used for counting events and displaying results in decimal form.




7-3 Synchronous (Parallel) Counters All FFs are triggered by CPs simultaneously Figure 7-5 illustrates operation of a synchronous

counter. Each FF has J and K inputs connected so they are HIGH

only when the outputs of all lower-order FFs are HIGH. The total propagation delay will be the same for any

number of FFs. Synchronous counters can operate at much higher

frequencies than asynchronous counters.




7-5 Synchronous Down and Up/Down Counters

The synchronous counter can be converted to a down counter by using the inverted FF outputs to drive the JK inputs.

A synchronous counter can be made an up/down counter by connecting as illustrated in Figure 7-11.




7-6 Presettable Counters A presettable counter can be set to any desired

starting point either asynchronously or synchronously.

The preset operation is also called parallel loading the counter.

Figure 7-12 illustrates an asynchronous preset. There are several TTL and CMOS devices that

provide both synchronous and asynchronous presetting.




7-7 IC Asynchronous Counters TTL 74ALS160

The counter contains four FFs. The FFs are triggered by a PGT at the CLK input. The IC has an active-low asynchronous CLEAR input. The counter can be preset to any value (applied to the A,

B, C, and D inputs) by applying an active-low LOAD input.

The counter is controlled using the various input combinations shown in Figure 7-13c.




7-8 Decoding a Counter Decoding is the conversion of a binary output to a

decimal value. The active high decoder shown in Figure 7-20 could

be used to light an LED representing each decimal number 0 to 7.

Active low decoding is obtained by replacing the AND gates with NAND gates.




7-9 Analyzing Synchronous Counters Figure 7-23 is a synchronous up counter.

The control inputs are as follows: JC = A B, KC = C, JB = KB = A, JA = KA =

The count sequence is illustrated by Table 7-1 and the waveforms shown in Figure 7-24.

A synchronous counter built using D-type FFs is shown in Figure 7-25. The count sequence is shown in Table 7-2.

C




7-10 Synchronous Counter Design Determine desired number of bits and desired counting

sequence Draw the state transition diagram showing all possible

states Use the diagram to create a table listing all PRESENT states

and their NEXT states Add a column for each JK input. Indicate the level required

at each J and K in order to produce transition to the NEXT state.

Design the logic circuits to generate levels required at each JK input.

Implement the final expressions.




7-11 Basic Counters Using HDL Overview Synchronous counter design with D FF State Transition Description Methods State descriptions in AHDL State descriptions in VHDL Behavioral Descriptions

AHDL VHDL




7-12 Full Featured Counters in HDL Overview

How to make it count up and down How to clear it asynchronously How to load it synchronously How to include synchronous cascade controls

AHDL full-featured counter VHDL full-featured counter




7-13 Wiring HDL Modules Together Decoding the AHDL MOD-5 counter




7-13 Wiring HDL Modules Together




AHDL

MOD-5

counter

7-13 Wiring HDL Modules Together

VHDL

MOD-5

counter




7-14 State Machines Counter circuits used to generate a sequence of states

without regard to their binary value are often called state machines. The washing machine states of idle, fill, agitate, and spin will be used in the examples. AHDL state machines VHDL state machines

Each method of describing logic circuits has advantages.




7-14 State Machines

AHDL state machine




7-14 State Machines

VHDL state machine




7-15 Integrated-Circuit Registers Registers can be classified by the way data is entered

for storage, and by the way data is outputted from the register. Parallel in/parallel out(PIPO) Serial in/serial out (SISO) Parallel in/serial out (PISO) Serial in/parallel out (SIPO)




7-16 PIPO – The 74ALS174/74HC174 Refer to Figure 7-62

Six bit register Parallel inputs D5 through D0

Parallel outputs Q5 through Q0

Parallel data loaded to the register on the PGT of CP Master reset can reset all FFs asynchronously




7-17 SISO – The 74HC166 Refer to Figure 7-64

The chip contains an 8-bit shift register The serial input is labeled SER Only the QH output is accessible.

Clock input responds to PGT A buffer is used to provide greater output current. Inputs A-H provide the means for parallel data entry

into register FFs




7-18 PISO – The 74ALS165/74HC165 Refer to figure 7-66

8 bit register Serial data entry via DS

Asynchronous parallel data entry P0 through P7

Only the outputs of Q7 are accessible CP is clock input for shifting Clock inhibit input Shift load input




7-19 SIPO – The 74ALS164/74HC164

Refer to Figure 7-68 8 bit shift register Each FF output is externally accessible A and B inputs are combined in an AND gate for

serial input. Shift occurs on NGT of the clock input.




7-19 SIPO – The 74ALS164/74HC164 Other similar devices

74194/ASL194/HC194 4 bit bi-directional universal shift register Performs shift left, shift right, parallel in and parallel out.

74373/ALS373/HC373/HCT373 8 bit PIPO with 8 D latches Tristate outputs

74374/ALS374/HC374 8 bit PIPO with 8 edge triggered D FFs Tristate outputs




7-20 Shift Register Counters Ring Counter

Refer to Figure 7-70 Last FF shifts its value to first FF Uses D-type FFs (JK FFs can also be used)

Must start with only one FF in the 1 state and all others in the 0 state.




7-20 Shift Register Counters Johnson counter

Refer to Figure 7-72 Also called a twisted ring counter Same as ring counter but the inverted output of

the last FF is connected to input of the first FF




7-21 Troubleshooting Sequential logic systems are more complex,

but basic troubleshooting procedures still apply. Observe system operation Use analytical reasoning to determine possible

causes Use test equipment to isolate the exact fault




7-22 HDL Registers Using bit arrays to describe register data

Example 7-24 involves the design of a universal 4 bit shit register. Requirements are: 4 synchronous modes of operation: hold, shift left,

shift right, and parallel load 2 input bits select operation to be performed on PGT

of the clock AHDL solution VHDL solution




7-23 HDL Ring Counters Recall that a ring counter is a shift register

that circulates a single active logic level through all its FFs. AHDL solution (Figure 7-85) VHDL solution (Figure 7-86)




7-24 HDL One-Shots Non-retriggerable, level sensitive one-shot

AHDL solution VHDL solution

Retriggerable edge-triggered one-shot AHDL solution VHDL solution




introduction to chapter 7 ffs and logic gates are combined to form various counters and registers. ...

Documents

counter principles

asynchronous counter

counter operation

counter troubleshooting

mod number

various counter circuits

pearson education

binary number