introduction to cmos digital logic...
TRANSCRIPT
![Page 1: Introduction to CMOS Digital Logic Circuitsweb02.gonzaga.edu/faculty/talarico/EE304/DOCS/CMOS...Typical voltage-transfer characteristic (VTC) of a logic inverter, illustrating the](https://reader036.vdocument.in/reader036/viewer/2022071507/6127900191307e6cb9768f85/html5/thumbnails/1.jpg)
Microelectronic Circuits, Seventh Edition (chapter 14) Sedra/Smith Copyright © 2015 by Oxford University Press
Introduction to CMOS Digital Logic Circuits
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Microelectronic Circuits, Seventh Edition Sedra/Smith Copyright © 2015 by Oxford University Press
Figure 14.1 Operation of the (a) NMOS and (b) PMOS transistor as an on/off switch. The gate voltage controls the operation of the transistor switch, with the voltage VDD representing a logic 1 and 0 V representing a logic 0. Note that the connections of the drain and source terminals are not shown.
MOSTs as switches
For a transistor in triode region if VGS – Vt << VDS:
𝑅"# ≡ 𝑅%& ≈1
𝜇𝐶"+𝑊𝐿 𝑉/& − 𝑉1
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Microelectronic Circuits, Seventh Edition Sedra/Smith Copyright © 2015 by Oxford University Press
Figure 14.2 (a) Block representation of the logic inverter; (b) its CMOS realization; (c) operation when the input is a logic 1; (d) operation when the input is a logic 0.
The CMOS inverter
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General CMOS logic gate structure
The PUN and the PDN are complementary
VDD
The PUN is made only of pMOSTs
The PDN is made only of nMOSTs
GND
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Microelectronic Circuits, Seventh Edition Sedra/Smith Copyright © 2015 by Oxford University Press
Figure 14.4 Examples of pull-down networks.
Examples of pull-down networks
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Microelectronic Circuits, Seventh Edition Sedra/Smith Copyright © 2015 by Oxford University Press
Figure 14.5 Examples of pull-up networks.
Examples of pull-up networks
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MOSTs symbols used in “digital logic”The body terminal of all pMOSTs is “assumed” connected to VDD
The body terminal of all nMOSTs is “assumed” connected to GND
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Microelectronic Circuits, Seventh Edition Sedra/Smith Copyright © 2015 by Oxford University Press
Figure 14.7 A two-input CMOS NOR gate.
Example: CMOS NOR gate
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Microelectronic Circuits, Seventh Edition Sedra/Smith Copyright © 2015 by Oxford University Press
Figure 14.8 A two-input CMOS NAND gate.
Example: CMOS NAND gate
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Microelectronic Circuits, Seventh Edition Sedra/Smith Copyright © 2015 by Oxford University Press
Figure 14.9 CMOS realization of a complex gate.
Example: a composite CMOS gate A B C D Y0 0 0 0 10 0 0 1 10 0 1 0 10 0 1 1 10 1 0 0 10 1 0 1 10 1 1 0 10 1 1 1 11 0 0 0 11 0 0 1 11 0 1 0 11 0 1 1 01 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 0
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Microelectronic Circuits, Seventh Edition Sedra/Smith Copyright © 2015 by Oxford University Press
Figure 14.2 (a) Block representation of the logic inverter; (b) its CMOS realization; (c) operation when the input is a logic 1; (d) operation when the input is a logic 0.
CMOS inverter: logic symbol, implementation, and simplified model
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Microelectronic Circuits, Seventh Edition Sedra/Smith Copyright © 2015 by Oxford University Press
Figure 14.16 The VTC of an ideal inverter.
DC transfer characteristic of the ideal inverter
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Typical voltage-transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.
DC transfer characteristic of “real” inverter
VDD − |Vtp|
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Microelectronic Circuits, Seventh Edition Sedra/Smith Copyright © 2015 by Oxford University Press
DC parameters of the logic inverter
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Implementation of CMOS inverter
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Microelectronic Circuits, Seventh Edition Sedra/Smith Copyright © 2015 by Oxford University Press
CMOS inverter with vI = VDD
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Microelectronic Circuits, Seventh Edition Sedra/Smith Copyright © 2015 by Oxford University Press
CMOS inverter with vI = GND
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Microelectronic Circuits, Seventh Edition Sedra/Smith Copyright © 2015 by Oxford University Press
Figure 14.25 The voltage-transfer characteristic of the CMOS inverter when QN and QP are matched.
DC transfer characteristic of a “real” inverter (with QP and QN matched)
vO vs. vI
“Robustness” of the inverter
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“Robustness” of the inverter
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DC transfer characteristic of a “real” inverter(with QP and QN mismatched)
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Microelectronic Circuits, Seventh Edition Sedra/Smith Copyright © 2015 by Oxford University Press
Figure 14.29 Definitions of propagation delays and transition times of the logic inverter.
Speed of the logic inverter (Transient behavior)