introduction to cmos vlsi design - ewu...
TRANSCRIPT
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Slides adapted from:
N. Weste, D. Harris, CMOS VLSI Design, © Addison-Wesley, 3/e, 2004
Introduction to CMOS VLSI Design
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Outline
A Brief HistoryMOS transistorsCMOS LogicCMOS Fabrication and LayoutDesign Flow
System DesignLogic DesignPhysical DesignDesign VerificationFabrication, Packaging and Testing
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CMOS Fabrication
CMOS transistors are fabricated on a thin silicon wafer that serve as both a mechanical support and electrical common point called substrateLithography process similar to printing pressOn each step, different materials are deposited or etchedEasiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process
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Inverter Cross-sectionTypically use p-type substrate for nMOS transistorsRequires n-well for body of pMOS transistors
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Well and Substrate TapsSubstrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor connection called Shottky DiodeUse heavily doped well and substrate contacts / taps
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Inverter Mask Set
Transistors and wires are defined by masksCross-section taken along dashed line
GND VDD
Y
A
substrate tap well tapnMOS transistor pMOS transistor
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Detailed Mask Views
Six masksn-wellPolysiliconn+ diffusionp+ diffusionContactMetal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
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Fabrication StepsStart with blank waferBuild inverter from the bottom upFirst step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide)Remove layer where n-well should be builtImplant or diffuse n dopants into exposed waferStrip off SiO2
p substrate
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Photoresist
Spin on photoresistPhotoresist is a light-sensitive organic polymerSoftens where exposed to light
p substrate
SiO2
Photoresist
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Lithography
Expose photoresist through n-well maskStrip off exposed photoresist
p substrate
SiO2
Photoresist
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Etch
Etch oxide with hydrofluoric acid (HF)Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
p substrate
SiO2
Photoresist
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n-welln-well is formed with diffusion or ion implantationDiffusion
Place wafer in furnace with arsenic gasHeat until As atoms diffuse into exposed Si
Ion ImplanatationBlast wafer with beam of As ionsIons blocked by SiO2, only enter exposed Si
n well
SiO2
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Strip Oxide
Strip off the remaining oxide using HFBack to bare wafer with n-wellSubsequent steps involve similar series of steps
p substraten well
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PolysiliconDeposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)Forms many small crystals called polysiliconHeavily doped to be good conductor
Thin gate oxidePolysilicon
p substraten well
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Polysilicon PatterningUse same lithography process to pattern polysilicon
Polysilicon
p substrate
Thin gate oxidePolysilicon
n well
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Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be diffused or implantedN-diffusion forms nMOS source, drain, and n-well contact
p substraten well
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N-diffusionPattern oxide and form n+ regionsSelf-aligned process where gate blocks diffusionPolysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing
p substraten well
n+ Diffusion
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N-diffusion cont.
Historically dopants were diffusedUsually ion implantation todayBut regions are still called diffusion
n wellp substrate
n+n+ n+
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N-diffusion cont.
Strip off oxide to complete patterning step
n wellp substrate
n+n+ n+
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P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact
p+ Diffusion
p substraten well
n+n+ n+p+p+p+
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ContactsNow we need to wire together the devicesCover chip with thick field oxideEtch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+n+ n+p+p+p+
Contact
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MetalizationSputter on aluminum over whole wafer, filling the contacts as wellPattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+n+ n+p+p+p+
M etal
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LayoutChips are specified with set of masksMinimum dimensions of masks determine transistor size (and hence speed, cost, and power)Feature size f = distance between source and drain
Set by minimum width of polysiliconFeature size improves 30% every 3 years or soNormalize for feature size when describing design rulesExpress rules in terms of λ = f/2
E.g. λ = 0.3 µm in 0.6 µm process
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Layout Design Rules
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Design Rules Summary
Metal and diffusion have minimum width and spacing of 4λContacts are 2λ x 2λ and must be surrounded by 1λ on the layers above and belowPolysilicon uses a width of 2λPolysilicon overlaps diffusions by 2λ where a transistor is desired and has spacing or 1λ away where no transistor is desiredPolysilicon and contacts have a spacing of 3λ from other polysilicon or contactsN-well surrounds pMOS transistors by 6λ and avoid nMOStransistors by 6λ
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Gate Layout
Layout can be very time consumingDesign gates to fit together nicelyBuild a library of standard cells
Standard cell design methodologyVDD and GND should abut (standard height)Adjacent gates should satisfy design rulesnMOS at bottom and pMOS at topAll gates include well and substrate contacts
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Inverter LayoutTransistor dimensions specified as W / L ratio- Minimum size is 4λ / 2λ, sometimes called 1 unit
- In f = 0.6 µm process, this is 1.2 µm wide, 0.6 µm long
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Example: Inverter Standard Cell Layout
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Example: 3-input NAND Standard Cell Layout
Horizontal n-diffusion and p-diffusion stripsVertical polysilicon gatesMetal1 VDD rail at topMetal1 GND rail at bottom32 λ by 40 λ
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Stick DiagramsStick diagrams help plan layout quickly
Need not be to scaleDraw with color pencils or dry-erase markers
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Wiring TracksA wiring track is the space required for a wire
4 λ width, 4 λ spacing from neighbor = 8 λ pitchTransistors also consume one wiring track
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Well spacingWells must surround transistors by 6 λ
Implies 12 λ between opposite transistor flavorsLeaves room for one wire track
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Area EstimationEstimate area by counting wiring tracks
Multiply by 8 to express in λ
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Design Challenges
The greatest challenge in modern VLSI is not in designing the individual transistors but in managing system complexityModern System-on-Chip designs use:
Many millions (soon billions!) of transistorsTens to hundreds of engineers
How to cope with Complexity ?Abstraction LevelStructured DesignDesign Flow
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Design Abstraction Levels
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Structured Design Tenets
HierarchyDivide and Conquer
RegularityReuse modules wherever possibleEx: standard cell library
ModularityWell-formed interface allows modules to be treated as black boxes
LocalityPhysical and Temporal
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Design FlowArchitecture: User’s perspective, what does it do?
Instruction set, MIPS, x86, Alpha, PIC, ARM, …Microarchitecture
Single cycle, multi cycle, pipelined, superscalar?Logic: how are functional blocks constructed ?
Ripple carry, carry look ahead, carry select addersCircuit: how are transistors used ?
Static CMOS, pass transistors, domino logic, …Physical: chip layout
Datapaths, memories, random logic
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Design Flow: Gajski’s Y-Diagram
The design process can be viewed as making transformations from one domain to another while maintaining the equivalency of the domains
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Architecture: MIPS exampleInstruction SetInstruction encoding formats
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Architecture: MIPS example cont.
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Microarchitecture: MIPS example
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Logic Design: MIPS exampleStart at the top level
Define the top-level interfaceTop level block diagramHierarchically decompose top level into unitsDesign the units (e.g. HDL)
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Logic Design: MIPS top level block diagram
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Logic Design: MIPS Hierarchy
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Logic Design using HDLs
Hardware Description LanguagesWidely used in logic designVerilog and VHDL
Describe hardware using codeDocument logic functionsSimulate logic before buildingSynthesize code into gates and layout
Requires a library of standard cells
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Circuit DesignHow should logic be implemented?
NANDs and NORs vs. ANDs and ORs?Fan-in and fan-out?How wide should transistors be?
These choices affect speed, area, power
Logic synthesis makes these choices for youGood enough for many applicationsBut when a system has critical requirement Hand-crafted circuits are still better
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Example: Full Adder
Transistors? Gate Delays?
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Example: Carry circuit
VERILOG:assign cout = (a&b) | (a&c) | (b&c);
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Gate-level Netlist
module carry(input a, b, c, output cout)
wire x, y, z;
and g1(x, a, b);and g2(y, a, c);and g3(z, b, c);or g4(cout, x, y, z);
endmodule
ab
ac
bc
cout
x
y
z
g1
g2
g3
g4
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Transistor-Level Netlist
a b
c
c
a b
b
a
a
b
coutcn
n1 n2
n3
n4
n5 n6
p6p5
p4
p3
p2p1
i1
i3
i2
i4
module carry(input a, b, c, output cout)
wire i1, i2, i3, i4, cn;
tranif1 n1(i1, 0, a);tranif1 n2(i1, 0, b);tranif1 n3(cn, i1, c);tranif1 n4(i2, 0, b);tranif1 n5(cn, i2, a);tranif0 p1(i3, 1, a);tranif0 p2(i3, 1, b);tranif0 p3(cn, i3, c);tranif0 p4(i4, 1, b);tranif0 p5(cn, i4, a);tranif1 n6(cout, 0, cn);tranif0 p6(cout, 1, cn);
endmodule
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SPICE Netlist.SUBCKT CARRY A B C COUT VDD GNDMN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5PMN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5PMN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5PMN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P AS=0.5PMN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15PMP1 I3 A VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1 PMP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1PMP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1PMP4 I4 B VDD VDD PMOS W=2U L=0.18U AD=0.3P AS=1PMP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3PMN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1PMP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2PCI1 I1 GND 2FFCI3 I3 GND 3FFCA A GND 4FFCB B GND 4FFCC C GND 2FFCCN CN GND 4FFCCOUT COUT GND 2FF.ENDS
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Physical Design
FloorplanStandard cells
Place & routeDatapaths
Slice planningArea estimation
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MIPS floorplan
Does the design fit the chip area budgeted ?Estimates area of major units and defines their relative placementEstimate wire lengthsEstimates wiring congestion
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MIPS layout
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Taxonomy of On-Chip structures
Random logicData pathsArraysAnalogInput/output (I/O)
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Synthesized MIPS Controller
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Hand-Crafted MIPS Datapath
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Standard Cells
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Synthesized MIPS
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Area EstimationNeed area estimates to make floorplan
Compare to another block you already designedOr estimate from transistor countsBudget room for large wiring tracks
Some cell library vendor specify cell layout densities in Kgates/mm2
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Design Verification
Fabrication is slow & expensiveMOSIS 0.6µm masks: $1000, 3 monthsState of art masks (130nm): $1M, 1 month
Debugging chips is very hardLimited visibility into operation
Prove design is right before building!System simulation (C/C++)Logic simulation (HDL testbench)Circuit simulation / formal verificationLayout vs. schematic comparisonDesign & electrical rule checks
Verification is > 50% of effort on most chips !
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Fabrication
Tapeout final layoutFormats for mask descriptions:CIF (academia) and GDS II (industry)
Fabrication6, 8, 12” wafers (bare wafer costs $1000-$5000)Optimized for throughput, not latency (turnaround times up to 10weeks !)Cut into individual dice
Fabs cost billions of dollars and become obsolete in a few yearsFabless semiconductor companiesManufacturing Companies: TSMS, UMC, IBM
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Packaging
Bond gold wires from die I/O pads to package
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Testing
Test that chip operatesDesign errorsManufacturing errors
A single dust particle or wafer defect kills a dieYields from 90% to < 10%Depends on die size, maturity of processTest each part before shipping to customer
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Summary
Many chip designers spend much of their time specifying circuits with HDL and seldom look at the actual transistorHowever:
Chip Design is not software engineeringIt requires a fundamental understanding of circuit and physical design
The best way to learn VLSI design is by doing it
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Summary cont.
Now you know everything to start designing a simple chip !