introduction to logic synthesis alan mishchenko uc berkeley
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Introduction Introduction to to
Logic SynthesisLogic Synthesis
Alan MishchenkoAlan Mishchenko
UC BerkeleyUC Berkeley
22
OverviewOverview
(1) (1) ProblemProblemss inin logic synthesis logic synthesis Representations and computationsRepresentations and computations
(2) And-Inverter Graphs (AIGs)(2) And-Inverter Graphs (AIGs) The foundation of innovative synthesisThe foundation of innovative synthesis
(3) (3) AIG-basedAIG-based solutions solutions Synthesis, mapping, verificationSynthesis, mapping, verification
33
(1) (1) ProblemProblemss InIn SSynthesisynthesis
What are the objects to be “synthesized”?What are the objects to be “synthesized”? Boolean functions (with or without don’t-cares)Boolean functions (with or without don’t-cares) State machines, relations, sets, etcState machines, relations, sets, etc
How to represent them efficiently?How to represent them efficiently? Depends on the task to be solvedDepends on the task to be solved Depends on the size of an objectDepends on the size of an object
How to create, transform, minimize the representations?How to create, transform, minimize the representations? Multi-level logic synthesis Multi-level logic synthesis Technology mappingTechnology mapping Verification Verification
44
TerminologyTerminology
Logic function Logic function (e.g. (e.g. F = ab+cdF = ab+cd)) Variables (e.g. Variables (e.g. bb)) Minterms (e.g. Minterms (e.g. abcdabcd)) Cube (e.g. Cube (e.g. abab))
Logic networkLogic network Primary inputs/outputsPrimary inputs/outputs Logic nodesLogic nodes Fanins/fanoutsFanins/fanouts Transitive fanin/fanout coneTransitive fanin/fanout cone Cut and window (defined later)Cut and window (defined later) Primary inputsPrimary inputs
Primary outputsPrimary outputs
FaninsFanins
FanoutsFanoutsTFOTFO
TFITFI
55
Logic (Boolean) FunctionLogic (Boolean) Function
Completely specified Completely specified logic functionlogic function
Incompletely specified Incompletely specified logic functionlogic function
0000 0101 1111 1010
0000 00 00 11 00
0101 00 00 11 00
1111 11 11 11 11
1010 00 00 11 00
0000 0101 1111 1010
0000 00 00 11 00
0101 00
1111 11 11 11
1010 00 00 11 00
0000 0101 1111 1010
0000 00 00 11 00
0101 00 00 00 00
1111 11 11 11 00
1010 00 00 11 00
0000 0101 1111 1010
0000 11 11 00 11
0101 11 00 00 00
1111 00 00 00 00
1010 11 11 00 11
0000 0101 1111 1010
0000 00 00 00 00
0101 00 11 11 11
1111 00 00 00 11
1010 00 00 00 00
On-set Off-set DC-set
abab
cdcd
cdcd
abab
66
RelationsRelations
Relation (a1,a2) Relation (a1,a2) (b1,b2) (b1,b2) (0,0) (0,0) (0,0) (0,0) (0,1) (0,1) (1,0)(0,1) (1,0)(0,1) (1,0) (1,0) (1,1) (1,1) (1,1) (1,1) (1,0) (1,0)
FSMFSM
0000 0101 1111 1010
0000 11 00 00 00
0101 00 11 00 00
1111 00 00 00 11
1010 00 11 11 00
0000 0101 1111 1010
0000 11 11 00
0101 11 11 11
1111
1010 11 00 00
a1 a2a1 a2
b1 b2b1 b2
01010000
1010
Current Current statestate
Next Next statestate
Characteristic function
77
Representation ZooRepresentation ZooFind each of these representations?Find each of these representations? Truth table (TT)Truth table (TT) Sum-of-products (SOP)Sum-of-products (SOP) Product-of-sums (POS)Product-of-sums (POS) Binary decision diagram (BDD)Binary decision diagram (BDD) And-inverter graph (AIG)And-inverter graph (AIG) Logic network (LN)Logic network (LN)
abcdabcd FF
00000000 00
00010001 00
00100010 00
00110011 11
01000100 00
01010101 00
01100110 00
01110111 11
10001000 00
10011001 00
10101010 00
10111011 11
11001100 11
11011101 11
11101110 11
11111111 11
F = ab+cdF = ab+cd
F = (a+c)(a+d)(b+c)(b+d)F = (a+c)(a+d)(b+c)(b+d)
1100
aa
bb
cc
dd
FFaa bb cc dd
FF
aa bb cc dd
FF
abab
x+cdx+cd
88
Representation OverviewRepresentation Overview TT are the natural representation of logic functionsTT are the natural representation of logic functions
Not practical for large functionsNot practical for large functions Still good for functions up to 16 variablesStill good for functions up to 16 variables
SOP is widely used in synthesis tools since 1980’sSOP is widely used in synthesis tools since 1980’s More compact than TT, but not canonicalMore compact than TT, but not canonical Can be efficiently minimized (SOP minimization by Espresso, ISOP Can be efficiently minimized (SOP minimization by Espresso, ISOP
computation) and translated into multi-level forms (algebraic factoring)computation) and translated into multi-level forms (algebraic factoring) BDD is a useful representation discovered around 1986BDD is a useful representation discovered around 1986
Canonical (for a given function, there is only one BDD)Canonical (for a given function, there is only one BDD) Very good, but only if (a) it can be constructed, (b) it is not too largeVery good, but only if (a) it can be constructed, (b) it is not too large Unreliable (non-robust) for many industrial circuitsUnreliable (non-robust) for many industrial circuits
AIG is an up-and-coming representation!AIG is an up-and-coming representation! Compact, easy to construct, can be made “canonical” using a SAT solverCompact, easy to construct, can be made “canonical” using a SAT solver Unifies the synthesis/mapping/verification flowUnifies the synthesis/mapping/verification flow The main reason to give this talk The main reason to give this talk
99
Problem Size
Time1950-1970 1980 1990 2000
CNFTT
SOP BDD
Historical PerspectiveHistorical Perspective
AIG16
50
100
100000
Espresso, MIS, SIS
SIS, VIS, MVSIS
ABC
1010
What Representation to Use?What Representation to Use? For small functions (up to 16 inputs)For small functions (up to 16 inputs)
TT works the best (local transforms, decomposition, factoring, etc)TT works the best (local transforms, decomposition, factoring, etc) For medium-sized functions (16-100 inputs)For medium-sized functions (16-100 inputs)
In some cases, BDDs are still used (reachability analysis)In some cases, BDDs are still used (reachability analysis) Typically, it is better to represent as AIGsTypically, it is better to represent as AIGs
Translate AIG into CNF and use SAT solver for logic manipulationTranslate AIG into CNF and use SAT solver for logic manipulation Interpolate or enumerate SAT assignmentsInterpolate or enumerate SAT assignments
For large industrial circuits (>100 inputs, >10,000 gates)For large industrial circuits (>100 inputs, >10,000 gates) Traditional LN representation is not efficientTraditional LN representation is not efficient AIGs work remarkably wellAIGs work remarkably well
Lead to efficient synthesis Lead to efficient synthesis Are a natural representation for technology mappingAre a natural representation for technology mapping Easy to translate into CNF for SAT solvingEasy to translate into CNF for SAT solving etcetc
1111
What are Typical Transformations?What are Typical Transformations?
Typical transformations of representationsTypical transformations of representations For SOP, minimize cubes/literalsFor SOP, minimize cubes/literals For BDD, minimize nodes/widthFor BDD, minimize nodes/width For AIG, restructure, minimize nodes/levelsFor AIG, restructure, minimize nodes/levels For LN, restructure, minimize area/delayFor LN, restructure, minimize area/delay
1212
Computations in Networks / AIGsComputations in Networks / AIGs
Divide-and-conquerDivide-and-conquer Traversal, windowing, cut computationTraversal, windowing, cut computation
GGuess-and-check uess-and-check BBit-wise simulationit-wise simulation
RReason-and-proveeason-and-prove Boolean satisfiabilityBoolean satisfiability
1313
TraversalTraversal TraversalTraversal is visiting nodes in is visiting nodes in
the network in some orderthe network in some order
Topological orderTopological order visits visits nodes from PIs to POsnodes from PIs to POs Each node is visited after its Each node is visited after its
fanins are visitedfanins are visited
Reverse topological orderReverse topological order visits visits nodes from POs to PIsnodes from POs to PIs Each node is visited after its Each node is visited after its
fanouts are visitedfanouts are visited Primary inputsPrimary inputs
Primary outputsPrimary outputs
Traversal in a topological orderTraversal in a topological order
44
11
33
88
77
55
6622
1414
WindowingWindowing
DefinitionDefinition A A windowwindow for a node is the for a node is the
node’s context, in which an node’s context, in which an operation is performedoperation is performed
A window includes A window includes k k levels of the TFI levels of the TFI mm levels of the TFOlevels of the TFO all re-convergent paths all re-convergent paths
between window PIs and between window PIs and window POswindow POs
Window POs
Window PIs
k = 3
m = 3
Pivot node
1515
Structural Cuts in AIGStructural Cuts in AIG
A cut of a node n is a set of nodes in transitive fan-in
such thatevery path from the node to PIs is blocked by nodes in the cut.
A k-feasible cut means the size of the cut must be k or less.
a b c
p q
n
The set {p, b, c} is a 3-feasible cut of node n. (It is also a 4-feasible cut.)
k-feasible cuts are important in FPGA mapping because the logic between root n and the cut nodes {p, b, c} can be replaced by a k-LUT
1616
Cut ComputationCut Computation
a b c
p q
{ {p}, {a, b} } { {q}, {b, c} }
{ {a} } { {b} } { {c} }
n
{ {n}, {p, q}, {p, b, c}, {a, b, q}, {a, b, c} }
The set of cuts of a node is a ‘cross product’ of the sets of cuts of its children.
Any cut that is of size greater than k is discarded.
Computation is done bottom-up
(P. Pan et al, FPGA ’98; J. Cong et al, FPGA ’99)
kk Cuts per Cuts per nodenode
44 66
55 2020
66 8080
77 150150
1717
Bitwise SimulationBitwise Simulation Assign particular (or random) Assign particular (or random)
values at the primary inputsvalues at the primary inputs Multiple simulation patterns are Multiple simulation patterns are
packed into 32- or 64-bit stringspacked into 32- or 64-bit strings Perform bitwise simulation at Perform bitwise simulation at
each node each node Nodes are ordered in a Nodes are ordered in a
topological ordertopological order
Works well for AIG due to Works well for AIG due to The uniformity of AND-nodesThe uniformity of AND-nodes Speed of bitwise simulationSpeed of bitwise simulation Topological ordering of memory Topological ordering of memory
used for simulation informationused for simulation information
aa bb cc dd
FF
00
11
11
11
11
00
00
11
00
00
11
00
11
00
11
11
00
00
11
00
00
00
00
11
00
00
11
11
11
22
33
44
11
22
33
44
11
22
33
44
11
22
33
44
1818
Boolean SatisfiabilityBoolean Satisfiability
Given a CNF formula Given a CNF formula (x)(x), , satisfiability problemsatisfiability problem is is to prove that to prove that (x) (x) 0 0, or to find a counter-, or to find a counter-example example x’x’ such that such that (x’) (x’) 1 1
Why this problem arises?Why this problem arises? If CNF were a canonical representation (like BDD), it would be If CNF were a canonical representation (like BDD), it would be
trivial to answer this question.trivial to answer this question. But CNF is not canonical. Moreover, CNF can be very But CNF is not canonical. Moreover, CNF can be very
redundant, so that a large formula is, in fact, equivalent to 0.redundant, so that a large formula is, in fact, equivalent to 0. Looking for a satisfying assignment can be similar to searching Looking for a satisfying assignment can be similar to searching
for a needle in the hay-stack.for a needle in the hay-stack. The problem may be even harder, if there is no needle there!The problem may be even harder, if there is no needle there!
1919
Example (Deriving CNF)Example (Deriving CNF)
(a + b + c)
(a + b + c’)
(a’ + b + c’)
(a + c + d)
(a’ + c + d)
(a’ + c + d’)
(b’ + c’ + d’)
(b’ + c’ + d)
0000 0101 1111 1010
0000 00 00 00 000101 00 11 00 001111 00 00 00 001010 00 00 00 00
ab
cd
Cube: bcd’
Clause: b’ + c’ + d
CNF
2020
SAT SolverSAT Solver
The best SAT solver is MiniSAT The best SAT solver is MiniSAT (http://minisat.se/) (http://minisat.se/) Efficient (won many competitions)Efficient (won many competitions) Simple (600 lines of code)Simple (600 lines of code) Easy to modify and extendEasy to modify and extend Integrated into ABCIntegrated into ABC
SAT solver typesSAT solver types CNF-based, circuit-basedCNF-based, circuit-based Complete, incompleteComplete, incomplete DPLL, saturation, etc.DPLL, saturation, etc.
A lot of magic is used to build an A lot of magic is used to build an efficient SAT solverefficient SAT solver Two literal clause watchingTwo literal clause watching Conflict analysis with clause Conflict analysis with clause
recording recording Non-chronological backtrackingNon-chronological backtracking Variable ordering heuristics Variable ordering heuristics Random restarts, etcRandom restarts, etc
Applications in EDAApplications in EDA VerificationVerification
Equivalence checkingEquivalence checking Model checkingModel checking
SynthesisSynthesis Circuit restructuringCircuit restructuring DecompositionDecomposition False path analysisFalse path analysis
RoutingRouting
2121
Example (SAT Solving)Example (SAT Solving)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
1
2
3
4
5
6
7
8
a(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
b
c
d d
b
c
d d
c
d(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
(¬b + ¬c + ¬d)
(a + b + c)
(a + b + ¬c)
(¬a + b + ¬c)
(a + c + d)
(¬a + c + d)
(¬a + c + ¬d)
(¬b + ¬c + d)
Courtesy Karem Sakallah, University of Michigan
2222
(2) And-Inverter Graphs (AIG)(2) And-Inverter Graphs (AIG)
DDefinition and examplesefinition and examples Several simple tricks that make AIGs workSeveral simple tricks that make AIGs work SSequential AIGsequential AIGs Unifying representationUnifying representation A typical synthesis application: AIG rewritingA typical synthesis application: AIG rewriting
2323
AIG DAIG Definition and efinition and EExamplesxamples
cdcdabab 0000 0101 1111 1010
0000 00 00 11 00
0101 00 00 11 11
1111 00 11 11 00
1010 00 00 11 00
F(a,b,c,d) = ab + d(ac’+bc)
F(a,b,c,d) = ac’(b’d’)’ + c(a’d’)’ = ac’(b+d) + bc(a+d)
cdcdabab 0000 0101 1111 1010
0000 00 00 11 00
0101 00 00 11 11
1111 00 11 11 00
1010 00 00 11 00
6 nodes
4 levels
7 nodes
3 levels
b ca c
a b d
a c b d b c a d
AIG is a Boolean network composed of two-input ANDs and inverters.AIG is a Boolean network composed of two-input ANDs and inverters.
2424
Three Simple TricksThree Simple Tricks Structural hashingStructural hashing
Makes sure AIG is always stored in a compact formMakes sure AIG is always stored in a compact form Is applied during AIG constructionIs applied during AIG construction
Propagates constantsPropagates constants Ensures each node is structurally uniqueEnsures each node is structurally unique
Complemented edgesComplemented edges Represents inverters as attributes on the edgesRepresents inverters as attributes on the edges
Leads to fast, uniform manipulationLeads to fast, uniform manipulation Does not use memory for invertersDoes not use memory for inverters Leads to efficient structural hashingLeads to efficient structural hashing
Memory allocationMemory allocation Uses fixed amount of memory for each nodeUses fixed amount of memory for each node
Can be done by a simple custom memory managerCan be done by a simple custom memory manager Even dynamic fanout manipulation is supported!Even dynamic fanout manipulation is supported!
Allocates memory for nodes in a topological orderAllocates memory for nodes in a topological order Optimized for traversal in the same topological orderOptimized for traversal in the same topological order Small static memory footprint for many applicationsSmall static memory footprint for many applications
a b
c d
a b
c d
Without hashingWithout hashing
With hashingWith hashing
2525
SSequential AIGsequential AIGs
Sequential networks have memory elements in Sequential networks have memory elements in addition to logic nodesaddition to logic nodes Memory elements are modeled as D-flip-flopsMemory elements are modeled as D-flip-flops Initial state {0,1,x} is assumed to be given Initial state {0,1,x} is assumed to be given
Several ways of representing sequential AIGsSeveral ways of representing sequential AIGs Additional PIs and POs in the combinational AIGAdditional PIs and POs in the combinational AIG Additional register nodes with sequential structural hashingAdditional register nodes with sequential structural hashing
Sequential synthesis (in particular, retiming) Sequential synthesis (in particular, retiming) annotates registers with additional informationannotates registers with additional information Takes into account register type and its clock domain Takes into account register type and its clock domain
2626
AIG: A Unifying RepresentationAIG: A Unifying Representation
An underlying data structure for various computationsAn underlying data structure for various computations Rewriting, resubstitution, simulation, SAT sweeping, Rewriting, resubstitution, simulation, SAT sweeping,
induction, etc are based on the same AIG managerinduction, etc are based on the same AIG manager
A unifying representation for the whole flowA unifying representation for the whole flow Synthesis, mapping, verification use the same data-structureSynthesis, mapping, verification use the same data-structure Allows multiple structures to be stored and used for mappingAllows multiple structures to be stored and used for mapping
The main functional representation in ABCThe main functional representation in ABC A foundation of new logic synthesis A foundation of new logic synthesis
2727
AIG RewritingAIG Rewriting
a b a c
Subgraph 1
b c
a
Subgraph 2
Pre-computing AIG subgraphsPre-computing AIG subgraphsConsider function Consider function f = abcf = abc
a c
b
Subgraph 3
Rewriting AIG subgraphsRewriting AIG subgraphs
Rewriting node A
Rewriting node B
a b a c
a b a c
A
Subgraph 1
b c
a
A
Subgraph 2
b c
a
B
Subgraph 2a b a c
B
Subgraph 1
In both cases 1 node is savedIn both cases 1 node is saved
AIG rewritingAIG rewriting aims at minimizing the number of AIG nodes aims at minimizing the number of AIG nodes without increasing the number of AIG levelswithout increasing the number of AIG levels
2828
(3) (3) AIG-AIG-BBased ased SolutionsSolutions
SynthesisSynthesisMappingMappingVerificationVerification
2929
AIG-Based Solutions (Synthesis)AIG-Based Solutions (Synthesis) Restructures AIG or logic network by the following transformsRestructures AIG or logic network by the following transforms
Algebraic balancingAlgebraic balancing Rewriting/refactoring/redecompositionRewriting/refactoring/redecomposition ResubstitutionResubstitution Minimization with don't-cares, etcMinimization with don't-cares, etc
SynthesisSynthesis
D2D2D1D1
Synthesis with choicesSynthesis with choices
D3D3HAIGHAIG
D2D2D1D1 D3D3 D4D4
D4D4
3030
AIG-Based Solutions (Mapping)AIG-Based Solutions (Mapping)Input: A Boolean network (And-Inverter Graph)
Output: A netlist of K-LUTs implementing AIG and optimizing some cost function
The subject graph The mapped netlist
TechnologyMapping
a b c d
f
e a b c d e
f
3131
AIG-Based Solutions (Verification)AIG-Based Solutions (Verification)
Property checkingProperty checking Takes design and property Takes design and property
and makes a miter (AIG)and makes a miter (AIG) Equivalence checkingEquivalence checking
Takes two designs and makes Takes two designs and makes a miter (AIG)a miter (AIG)
The goal is to transform AIG The goal is to transform AIG until the output is proved until the output is proved constant 0constant 0
D2D2D1D1
Equivalence checkingEquivalence checking
0
D1D1
Property checkingProperty checking
0
pp
3232
SummarySummary
Introduced pIntroduced problemroblemss inin logic synthesis logic synthesisRepresentations and computationsRepresentations and computations
Described And-Inverter Graphs (AIGs)Described And-Inverter Graphs (AIGs)The foundation of innovative synthesisThe foundation of innovative synthesis
Overviewed Overviewed AIG-basedAIG-based solutions solutionsSynthesis, mapping, verificationSynthesis, mapping, verification