introduction to soc

8/2/2019 Introduction to SOC

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Introduction to SoC

Instructor: NCTU


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System

A collection of all kinds of components and/or subsystems

that are appropriately interconnected to perform thespecified functions for end users.

o es gn s a pro uc crea on processwhich

-

Hardware

Software Ends at delivering a product with enough functional

satisfaction to overcome the payment from the end-user


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First phase Second phase Third phase


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Definition: integration of a complete systemonto a single IC


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MemoryRF

Processor

or JTAGEmbeddedSoftware

InterfaceOCB Archit ecture

RTOS

PeripheralsConfigurable


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Hardware:

Analog: ADC, DAC, PLL, TxRx, RFetc.

Digital: Processor, Interface, Acceleratoretc. Storage: SRAM, DRAM, FLASH, ROMetc.

Software: OS, Application


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Source: Semiconductor Research Corp.


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es er ay o ay

Sin le Chi

5~8Processors

Memory

FlashMemory

rap cs

Bluetooth GPS Radio

Radio

WLANProcessor

Voice only; 2 processors

4 year product life cycle

Short talk time

Voice, data, video, SMS


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Architecture strategy

Design-for-test strategy Validation strategy

Synthesis and backend strategy

Integration strategy


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CharacteristicsCharacteristics

Very large transistor counts

Why?Why?

Complex applications

Mixed technologies on thesame chip

em con uc or ens yper year, but design productivity

21% annually.

Process technology allows it , , ,

Hardware and software Multiple clock frequencies

Hierarchical desi n with

High performance Miniaturization

embedded reusable IP cores

Short market windows

Cost sensitivity


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Central processing core

DSP cores

On chip bus

- -

I/O, peripherals

-

Parameterization


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Com utation-intensive

Control-dominated

subsystem 6502Microcontroller Subsystem

Control-oriented function computation, signal processing

controls & coordinatessystem tasks

MCU-relatedCoprocesors

MIPS

ARM

Motorola

Oakprogrammemory

DSP Processors

MMX-likeDatapath

(e.g. user interface)

Data-dominated

foreground memory(Cache)

communication &

TIdata

memory

su system

regular & predictable

transformationaltasks

background memory

foregroundmemory ParallelFunctional

Configurable DSP Datapath

ASIC 4

ASIC 3

Dedicated Hardware

well-defined DSP kernelswith high parallelism

(SIU) UnitsASIC 2

ASIC 1

interfaceunit


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SOC Com lexit / Abstraction

Yesterday Today

Processor-centric (1 or 2)

Simple I/O

Many processing units

Large amount of I/O

Manageable Complexity Overwhelming Complexity!

Source: EI-SONICS


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Use a known real entity

A pre-designed component (IP, VC reuse) A platform (architecture reuse)

Partition

Based on functionality Hardware and software

o e ng

At different level


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Intellectual Property (IP)

Intellectual Property means products, technology, software,etc. that have been protected through patents, copyrights, or

trade secrets.

A block that meets the Virtual Socket Interface Specification

and is used as a com onent in the Virtual Socket desi n

environment. Virtual Components can be of three forms

Soft, Firm, or Hard. (VSIA)

Also named mega function, macro block, reusable

component


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System-on-Chip (SoC)

Semiconductor Intellectual Pro ert (IP) Also known as cores, virtual components (VCs)

Memory, processors, DSPs, I/O, perpherials

o = s


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, , , ,

Memory controller

Interru t controller

Power management controller

Bridges

Other functions


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, ,

Hard core Large logic circuits

E.g. ARM core

Soft core Tiny logic circuits Synthesize layout using standard cells with ASIC flow E. . IPs

Firm core Medium logic circuits

Tile-based layout like Hard core E.g. FPGA CAD tools


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gate level or synthesizable RTlevel data

Some technology and/orphysical constraints

some flexibility on form &function

Predictable size and speed

Hard IP:Hard IP:

(physical)(physical)

Soft IP: (Core)Soft IP: (Core)

Technology specific Fixed form & function

Well characterized

Technology portable

Flexible form &function

s ma e s ze anspeed


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Differences in Design Between

Limitation of IC design Number of I/O pin Desi n and Im lement all the functionalit in the silicon

Soft IP No limitation on number of I/O pin

but implement desired parts in the silicon IP compiler/Generator: select what you want !! More hi h level auxiliar tools to verif desi n More difficult in chip-level verification

Hard IP

Provide multiple level abstract model Design and Implement all the functionality in the layout

Reusability


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Foundation IP Cell, MegaCell

Star IP ARM ( low ower )

Niche IP JPEG, MPEGII, TV, Filter

, , ,

..


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Legacy IP

- from previous IC New IP

- specifically designed for reuse

Licensed IP- from IP vendors


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Dont know how to do it

Cannot wait for new in-house develo ment

Standard/Compatibility calls for it

PCI USB IEEE1394 Bluetooth

Software compatibility

Configurable


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All IPs are typically customized to meet specific

SoC specification o tware upgra a ty

Short product cycles

E.g. External memory controller supports memory types (sync. Or async.)

Widths,

Banks,

.


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SoC = (IPs + Platform) Platform, or Semiconductor Infrastructure IP

Interconnect/Inter-block communication

er ormance opt m zat on

Test

Dia nosis

Repair

Power management


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-

PE granularity

(usually imply # of

I/O

Registers Registers Registers

unc ona es

Interconnectionroutability interconnect interconnectinterconnect

PE PE PE PE

neighbor (1-D) / mesh (2-D) crossbar

businterconnect interconnectinterconnect

PE PE PE PEI/O I/O

Initialization mechanism

Configuration overheadPE PE PE PE

global interconnection

I/O


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Smallest unit of the reconfigurable fabric that can be reprogrammed

tradeoffs between flexibility and reconfiguration overhead

x(n)

MUX

MEM MEM

CLBCLBreg0

c n y n reg1

Adder

Buffer

Reconfigurable Dataflow Reconfigurable Datapath Reconfigurable Logic


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,

Requirements

Have to connect many local IPs

Scalable capability

QoS

Types Wire (zero hop)

us s ng e op

Switch, router (multi-hop)

Circuit-switched

Packet-switched

Source: Philips


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Advanced Microcontroller Bus Architecture

(AMBA) AMBA 2.0 specifies

the Advanced High-performance Bus (AHB)

the Advanced System Bus (ASB)

the Advanced Peripheral Bus (APB)

On-Chip

BridgeAHB/ASB APB

EBI/TIC

Master Timer Keypad

A typical AMBA system


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What is VCI

A request-response protocol, contents and coding, for the

Why VCI

Other IP blocks not available wra ed to the on-chi

communications may work with IP wrappers. VSI AllianceVCI is the best choice to start with for an adaptation layer

Thee levels of protocol

Advanced VCI (AVCI),

Basic VCI (BVCI), and

Peripheral VCI (PVCI)

Transaction lan ua e


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A platform is a suite of reusable parts (IP) of many systemdesigns in a limited spectrum of applications

Memory

I/O I/O

Peripheral IP

Peripheral Bus

Peripheral IPProcessor(OS/drivers/program)

Co-Processor

Bridge

Memory

(shared data)

System

IP

System

IPBridge Peripheral Bus

Peripheral IPPeripheral IP

I/O I/O

Source: SOC Design Overview /MOE, R.O.C.


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Wipros ARM-based SoC-RapTor Platform

Hardware Software and


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Hardware, Software and

Does the

e

Untime Algorithm

Integration

,C++, C,

SDL, Matlab

functionallyintegrated

design work?

ExecutableFunctional

Specification

ArchitecturePerformance

Performan CPU, DSP

Bus, Memory,RTOS, HW, SW

performance& partitioning

sufficient?

ExecutablePerformanceSpecification

Refined

IntegratedDesign

Communication Pattern

Does the

refineddesign work?

Communication RefinementAbstra

ctToken

AbstractToke

Clock

ed

Software

I/F

DMAC

Ports

Timers

MPEGAudio Decoder

Register File

uCSoftware

HW Toplevel

estBench

CPU I/Os Drivers

RTOSScheduling

and Services

Tasks

GraphicsEngine

On-Chip RamCo-Verification

CoV-SetupT

ResultComparison

us r vers

Source: Cadence


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DFT is usually implemented using a full scan,

muxed flip-flop of scan insertion. For embedded memories, Built in Self-test (BIST)

and Module Test are best used.


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A platform provides an architecture reference which is proved to

be a applicable architecture. Simple modification is enough to be suitable to similar systems.

Save repetitive design time:

x s ng s or e p a orm can e a op e o acce era e e u

up time. Based on existing platform ease the replace of custom design.

Ease the verification:

The environment provided by a platform helps to verify the custom

.

Early evaluation:

H/S partitioning information.


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Reduce overall system cost

Increase erformance Lower power consumption


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New design consideration

Design methodologyPlatform-based design

Personal reuse

In-house reuse Parameterized and blockwise design

IP reuseArchitecture reuse

IP Compiler/Generator

Reuse without redesign

-

Physical design consideration/constraint


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Th N w m D i n P r i m

CPU

CoreDifferentiation

Software

CPU

Core

DSP

Core

Memory

Application-S ecific

RTOSBlueToothBlueTooth

Driver

IEEE1394IEEE1394

Driver

Block-Based Design

Hardware

Platform-Based Design

of function and architecture,


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Time-to-market pressure

ASIC/ASSP ratio: 80/20 in 2000, but 50/50 now

In-house ASIC design is down, replaced by off-the-shelf,programmable ASSP

-

Problem is that each system is an ad-hoc solution No effective programming model

Poor SW productivity


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S h t


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Sna shot

30mm wafer and Pentium 4TM

Photo courtesy of Intel


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200 mm300 mm

0.35 m technology12-Inch-

150 mmWafer

0.25 m technology6-Inch

0.18 m technology0.13 mWhen compared to the 0.18-micron process, thenew 0.13-micron process results in less than 60 technology

0.09 mtechnology

percent the die size and nearly 70 percentimprovement in performance

The 90-nm process will be manufactured on

0.065 mtechnology

300mm wafers

NEC devises low-k film for second-generation

65-nm process

introduction to soc

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