Introduction to Software RADIO What is the Software RADIO ? Advantage of the Software RADIO Physical Layer of a Radio Modem/Software Defined Radio Modem

Instances of Software RADIO Software Defined RADIO Project Reconfigurable Chip design example Example of Development Tool/Configurable Resource

Methodology of Software RADIO Technical Challenge Multi Mode and Reconfigurable Terminals Components Hardware Reconfiguration SDR Functional Blocks Description

Ideal 한 목표 : 채널 변복조 waveform 을 Software 를 이용 . TX:source encoder, up-conversion of baseband signal to carry freque

ncy RX:carry phase recovery, symbol or PN code timing recovery

개방형 구조 (Open Architecture)

다중 대역 , 다중 모드

대부분의 기능들이 소프트웨어 -programmable, 하드웨어 -재구성가능한 프로세서 엘리먼트에서 소프트웨어에 의해 실현 Configurable-ASIC, DSP 칩 , 마이크로프로세서 칩 , FPGA,

다른 programmable-DSP

개발 및 유지 / 보수해야 하는 제품 플랫폼 수 감소 One platform supports any physical layer, protocol stack Lower System maintenance & upgrade cost

No hardware replacement or frequent upgrade 체계적으로 스케일될 수 있는 제품구조

새로이 진화되어 가고 있는 capacity 수용 Backward Compatibility 미래 안정적 (Future-Proof) 시스템 개발 Time-to-Market 최소화

Run-time configurable ASIC: DS spreading, Chip shaping (FIR filter), Timing recovery, Antijam, transmission security, Correlator(low precision arithmetic to reduce power consumption)

Maximize the number of functions performed by the DSP: Data burst, FEC, Interleaving,

Adaptive S.P. Deinterleaver, Adaptive Decoder SDR 기술에 적용 가능한 분야

Hardware Software-Controlled Hardware Programmable SoftwarePost-Shipping

Programmable Software

Antenna

VCOBaseband B/WOutput Power

Modulator(Switched)Encryption

RF SelectivityIF

Chip-rate processing

ModulationEncryption

Smart AntennaSignal Processing

Source codingIF Selectivity

Power-ManagementSymbol-rate processing

User-interface

BB/IF Real/Complex

Digital/Analog

ANTENNA RFChannelSelector/Combiner

BasebandProcessing

DSP

Call/MessageProcessing &

I/O

CommonSystem

Equipment

I/O

MONITOR/CONTROL

Multimedia/WAP

ROUTING

I/O I/O I/O I/O

BBText Flow

Control bits

BBText Flow

Control BitsRFRF

Voice/PSTN

Data/IP

Flow Control

NSS/Network

AIR

I

C

I

C

I

C

I

C

AUX AUX AUX AUX AUX

Ext. Ref

Clock/StobeRef, Power

Remote Control/Display

Local Control

Typical Signal Processing blocks in software Defined Radio SDR Forum Recommended

ADC sampling rate dynamic range (determine precision of arithm

etic operations) translation of digital IF to baseband modulation/demodulation algorithms error coding/decoding algorithms synchronization algorithms

Technical Approach co-simulation methodology 를 사용하여 설계

re-configurable FPGA devices 를 포함한 platform 를 개발

physical hardware 설계 및 검증 일차적으로 re-configurable ASICs 생성 동일한 logic 를 FPGA 형태로 재생성

SDR Platform 으로 구현될 수 없는 service 를 정의 . Partition and real-time operation, optimization (power, co

mplexity, size, performance) 유사 project : TRUST http://www.ist-trust.org

Radio Architecture, RF 기술에 집중 Re-configurable Radio applications 에 적합한

Zero IF, single IF Radio Front-End re-configuration SOI, BICMOSSi-Ge 과 Micro-Machining 등과

같은 다양한 기술하에서 front-end 구조를 개발 .

function partitioning 의 최적화

low power : low-power DSP and MCU processor in combination with a small, low power programmable logic device (PLD). Functions needed for GSM Phase 2+ or UMTS termi

nal. DSP16000 and ARM7 MCU, Xilinx’s CoolRunner PL

D with extreme low power consumption (<0.5mA)

serve as HW co-processor for MCU, DSP or both.

reconfigurable coprocessor SW part designed in Processor Expert™ Embedded Beans library

Object oriented, component based embedded application CASE development tool code portability, component reusability expert knowledge system assistance. virtual prototyping IP sharing by embedded components exchange.

GSM - UMTS components (Embedded Beans) as building blocks

MCU expert knowledge system calculates overall system timing propagation automatic connection of peripherals Verifies the application timing

Processor Expert™ generates resulting source code (in selected language – typically C, ASM, C++ or VHDL).

BRAMs

BRAMs

VersaRing

VersaRing

Ver

saR

ing

Ver

saR

ing

IOB

’s

IOB

’s

IOB’s

IOB’s

DLL DLL

DLLDLL

Control

LUT

Control

LUT

Configurable storageelement

CLBs

Configurable storageelement

StandardArrary of CLBs

LUT :o look up table for logic functionsowide RAM or ROMo shift registerControl :o Combination of both LUTso Arithmetic supporto Carry controlo Route throughConfigurable Storageelement :o clocking modeo polarity asynchronous reset

Xilinx Virtex FPGA : intelligent configurationmechanism for fast and partial

Increasing density and reducing powerIncluded extra functions to support digital signaloperations such as extra arithmetic support andincreased RAMDynamic reconfiguration is also supported.

Block RAM large resource for storage ofapplication data

I n p u t O u t p u tBlocks (IOBs). configurable interfacing

Algorithm Definition& Specification

Optimization ofHardware Structure

PerformanceEst.

DSP/MCURequirement

ASIC/FPGA

Verification

Complexity ofReconfiguration

processor technology,such as DSPs, FPGAs,

Complexity & Levels ofReconfigurationComplexity

Software Repositoryand Access Methods

Transparent Reconfiguration Reconfiguration Signalling Verifying the Reconfiguration

TransparentReconfiguration

Selective Redefinitionof Module(s)

Micro and Macro levelProcess Management

Software Repositoryand Access Methods

Mode 1

Mode 2

Mode n

RFBB signal

Processing

RFBB signal

Processing

RFBB signal

Processing

RF

RF

RF

Memory forparameter

set

Basebandsignal

processing Pro

gra

mm

able

hig

h p

ow

erB

aseb

an

d s

ign

al p

roce

ssin

g

Fle

xib

le a

nd

ad

apti

ve R

F f

ron

ten

d

Multi-mode terminal with parallel modesMulti-mode terminal with software defined

signal processingFully adaptive software reconfigurable

system

RF BaseBand

수신된 신호를 IF 혹은 Baseband 신호로 변환

변조부, 채널 코덱부, 채널화기, 암호화부,시간/위상 추적부

다중 대역 안테나 선형 광대역 RF 부품 광대역 A/D, D/A 변환기 고성능 DSP/ 재구성 가능한 로직

Antenna RF ADC DSP

Smart 안테나

고 효율 선형 안테나

광대역, 소형화고 효율, 선형 RF 전력 증폭

기다른 신호와 동일 시간에 간

섭과 잡음이 없는 설계단일 모드와 같은 특성을 내

는 고주파 부품

첫번째 IF 단(아날로그 내림 변환)- ADC- 두번째 IF 단(디지털 내림 변

환)Band pass sigma delta

구조

기저대역부를 SW화 할 수있을 만큼의 성능,

TMS320C62X : 최대 성능1600 MIPS, TMS320C64X :

4800 MIPS

Reconfigurable Logic

FPGA,RC(ReconfigurableComputing) ASIC

RFConversion

to IF andA/D

I/Ocontroller

ProcessController

TemporaryStorageBuffer

Output andinterface with

host PC

ProgramMemory

ProgramMemory

Fo

rmat

ion

of

Str

eam

Pa

cket

s/In

terp

reta

tio

n

InterconnectingArray of Processing

Elements

Configurable ASIC FPGA

적절한 수준의 프로그래 밍 능력과 집적도를 제공

할 때 최선의 솔루션 , 낮은 프로그램 능력 집

적도

/ 고속 병렬 선형 신호처리 를 위한 최선의 프로그래머

블 솔루션 , 높은 전력 소비 칩 사이즈

가 큼

DSP

복잡한 분석, 의사 결정을 포함하는 기능에 대한 최선의 프로

그래머블 솔루션ASIC, FPGA에 비해

낮은 성능

Programmability,Level of Integration,

Development/Implementation/Test

Cycle,Performance in required

processing time,Power.

Multiplexing &Burst Construction Encription

ChannelCoding

Interleaving

DataProcessing

CRCinsertionModulation

Sequencer

Spreading

Equalization

Rate matching Channelization

Segmentation

RadioResource

Advantage Drawback

Only simple program-Scheduling,

factorization forcommon function

Restrict re-configurabilitywithin macro,

Data path routing-macro function composedof ASIC or FPGA or both, Routing Device-

Sequence

Advantage Drawback

Low-complexity ofhardware

Slower reconfiguration process, ifreconfiguration is failed, the

system will not operate-necessaryof default mode

Systematic re-programming of wholebaseband module, new standard is

installed on same hardware

FPGA

MPU

Previous Standard is running

FPGA

FPGA

FPGA

FPGA

MPU

Reconfiuration

FPGA

FPGA

FPGA

FPGA

MPU

Present Standard is running

FPGA

FPGA

FPGA

IN

F1FPGA

F6FPGAF4 F5Master

MPU

OUT

F2 F3

ASIC

High Speed

Low Speed

Advantage Drawback

Allowing data pathrouting, reconfiguration

of the BusTime division scheme

High Speed - for wide BW and FPGA re-synthesize

Low Speed - Control & low-rate datatransition

Time Delay

Longest

Longer

Band Width

Narrow

Wider

H/W Complexity

Better

Poor

BUS

Switched Net

Reconfiguration Resource Controller

Service

Interface

RADIO Manager

POLICY

DSP FPGA/ASIC

Real-Time Operating System

Stream I/O Layer

fixed length packercontaining

programminginformation or data to

be process

Interface

A mean to exploit processing powerattainable through deep pipeline, First-represented as data flow graph (smallcomputational primitive), changing the

parameter,Functionality is divided into layer.

Configuration Layer

Maintain address and alist of the modules (ofprocessing layer) and

configuration

Drawback

A set of interconnectedprocessing modules, the

core of SDR.

ProcessingElement 1

Stream Packet Stream Packet Stream PacketProcessingElement 2

InterpretPacket

ConfigurationPipeline

Reconstruct

Packet

ProcessingPipeline

Bypass PipelineProcessing Layer

Application Layer Software

I/O Layer

Configuration Layer

· Status of software modules· module UNIQUE identifierlist· module location in memory· active/inactive flag

ConfigurationMap

ModuleDefinition

For downloading step,identify software pieces andhardware pieces.

ModulesIdentification

MCU : defined as in the SDRCUFPGA : module can befused as binary codeDSP : between both

Operating control

Data In

Data Out

ConfigurationControl

· Function ID - Identifier of thefunction· Device ID - Identifier of targetdevice· Function Parameters - Astructure of function specificparameters· Device Parameters - Astructure describing devicespecific resources· Functional control - Control forstopping, starting etc.

Encapsulation data and methods to be wrapped

Interface Installed and managed using differentcode and support

Object serialization An object to literally be broken up intobytes for serial delivery

Reflection Capabilities of objects to be examined

, OFDM .데이터 효율 및 순 데이터 율에서 유사하지만 은 데이터 율을 가변할 수 있다

OFDM

변조 및 처리 방식

단순 주파수 영역 (기준 신호 사용)

다중 반송파 협대역 시그널링저속 데이터 율 전송주파수 영역 처리

복잡한 시간 영역 등화 (학습 신호 사용)

VSB

단일 반송파을 사용한 광대역 시그널링고속 데이터 율 전송시간 영역 처리

기준 신호

등화

동기 시간(인터리빙)시간/주파수(인터리빙)

파일럿 반송파 및 싱크 신호다이버서티

기능 분석을 통해 , 각 기능 블록 별로 common function 의 최소의 오버헤드로의 개발

DSP 와 FPGA 구현시 데이터 처리율 및 소요 면적 비교

요구되는 데이터율 및 제어를 고려하여 ASIC/DSP/FPGA 간의 분할