inverter sizing - university of waterloomhanis/ece637/lecture8.pdf · inverter sizing. inverter ......
TRANSCRIPT
-
Inverter SizingInverter Sizing
-
Inverter ChainInverter Chain
CL
If CL is given:- How many stages are needed to minimize the delay?- How to size the inverters?
May need some additional constraints.
In Out
-
Inverter DelayInverter Delay
Minimum length devices, L=0.25m Assume that for WP = 2WN =2W
same pull-up and pull-down currents approx. equal resistances RN = RP approx. equal rise tpLH and fall tpHL delays
Analyze as an RC network
WNunit
Nunit
unit
PunitP RRW
WR
WW
RR ==
=
11
tpHL = (ln 2) RNCL tpLH = (ln 2) RPCLDelay (D):
2W
W
unitunit
gin CWW
C 3=Load for the next stage:
-
Inverter with LoadInverter with Load
Load (CL)
Delay
Assumptions: no load -> zero delay
CL
tp = k RWCL
RW
RW
Wunit = 1
k is a constant, equal to 0.69
-
Inverter with LoadInverter with Load
Load
Delay
Cint CL
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)= Delay (Internal) + Delay (Load)
CN = Cunit
CP = 2Cunit2W
W
-
Delay FormulaDelay Formula( )
( ) ( )/1/1
~
0int ftCCCkRt
CCRDelay
pintextWp
extintW
+=+=
+
Cint = Cg with 1R = Runit/W ; Cint =WCunittp0 = 0.69RunitCunit
Inverters delay is a function of the ratio between its external load capacitance and its input capacitance. The ratio is called the effective fan-out f
-
Apply to Inverter ChainApply to Inverter Chain
CL
In Out
1 2 N
tp = tp1 + tp2 + + tpN
+ +
jgin
jginunitunitpj C
CCRt
,
1,1~
LNgin
N
i jgin
jginp
N
jjpp CC C
Cttt =
+== +
=
+
= 1,
1 ,
1,0
1, ,1
-
Optimal Tapering for Given Optimal Tapering for Given NN
Delay equation has N - 1 unknowns, Cgin,2 Cgin,N
Minimize the delay,
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
Size of each stage is the geometric mean of two neighbors
- each stage has the same effective fanout (Cout/Cin)- each stage has the same delay
1,1,, += jginjginjgin CCC
0,
=
jg
p
C
t
-
Optimum Delay and Number of Optimum Delay and Number of StagesStages
1,/ ginLN CCFf ==
When each stage is sized by f and has same effective fanout f:
N Ff =
( )/10 Npp FNtt +=Minimum path delay
Effective fanout of each stage:
-
ExampleExample
CL= 8 C1
In Out
C11 f f2
283 ==f
CL/C1 has to be evenly distributed across N = 3 stages:
-
Optimum Number of StagesOptimum Number of Stages
When N is large, the first component dominates (intrinsic delay). If N is too small, the effective fanout of each stage becomes large, and second component is dominant.
For a given load, CL and given input capacitance CinFind optimal sizing f
( )
+=+=
fffFt
FNtt pNpp lnln
ln1/ 0/10
0ln
1lnln2
0 =
=
fffFt
f
t pp
For = 0, f = e, N = lnF
fF
NCfCFC inN
inL lnln
with ===
( )ff += 1exp
( )/10 Npp FNtt +=
Self-loading is ignored and load caps only consist of fanout
-
Optimum Effective Optimum Effective FanoutFanout ffOptimum f for given process defined by
( )ff += 1expfopt = 3.6for =1
-
Impact of SelfImpact of Self--Loading on Loading on tptp
1.0 3.0 5.0 7.0u
0.0
20.0
40.0
60.0
u/ln
(u)
x=10
x=100
x=1000
x=10,000
No Self-Loading, =0 With Self-Loading =1
-
Normalized delay function of Normalized delay function of FF
( )/10 Npp FNtt +=
-
Buffer DesignBuffer Design
1
1
1
1
8
64
64
64
64
4
2.8 8
16
22.6
N f tp
1 64 65
2 8 18
3 4 15
4 2.8 15.3
-
Power DissipationPower Dissipation
-
Where Does Power Go in CMOS?Where Does Power Go in CMOS?
Dynamic Power Consumption
Short Circuit Currents
Leakage
Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leaking diodes and transistors
-
Dynamic Power DissipationDynamic Power Dissipation
Energy/transition
Power = Energy/transition * f = CL * Vdd2 * f
Need to reduce CL, Vdd, and f to reduce power.
Vin Vout
CL
Vdd
From equation, not a function of transistor sizes! (In reality it is)
Each time the capacitor gets charged through the PMOS transistor, its voltage rises from 0 to VDD, and a certain amount of energy is drawn from the power supply. Part of this energy is dissipated in the PMOS device, while the remainder is stored on the load capacitor. During the high-to-low transition, this capacitor discharged, and the stored energy is dissipated in the NMOS transistor.
==== DDV
DDLoutDDLout
LDDDDDDVDD VCdvVCdtdtdv
CVdtVtiVE0
2
00
)(
f represents the frequency of energy-consuming transitions (0 -> 1)
-
Modification for Circuits with Reduced Swing
CL
Vdd
Vdd
Vdd -Vt
E0 1 CL Vdd Vdd Vt( )=
Can exploit reduced swing to lower power(e.g., reduced bit-line swing in memory)
-
Node Transition Activity and PowerNode Transition Activity and PowerConsider switching a CMOS gate for N clock cycles
EN CL Vdd2 n N( )=
n(N): the number of 0->1 transition in N clock cycles
EN : the energy consumed for N clock cycles
Pavg N lim
ENN
-------- fclk=n N( )
N------------
N lim
CL
Vdd2 fclk=
0 1n N( )
N------------
N lim=
Pavg = 0 1 C LVdd
2 fclk
-
Short Circuit CurrentsShort Circuit Currents
Vin Vout
CL
Vdd
I VD
D (m
A)
0.15
0.10
0.05
Vi n (V)5.04.03.02.01.00.0
-
How to keep ShortHow to keep Short--Circuit Currents Low?Circuit Currents Low?
-
Minimizing ShortMinimizing Short--Circuit PowerCircuit Power
0 1 2 3 4 50
1
2
3
4
5
6
7
8
tsin
/tsout
Pno
rm
Vdd =1.5
Vdd =2.5
Vdd =3.3
-
LeakageLeakage
Vout
Vdd
Sub-ThresholdCurrent
Drain JunctionLeakage
Sub-threshold current one of most compelling issuesin low-energy circuit design!
-
ReverseReverse--Biased Diode LeakageBiased Diode Leakage
Np+ p
+
Reverse Leakage Current
+
-Vdd
GATE
IDL = JS A
JS = 10-100 pA/m2 at 25 deg C for 0.25m CMOSJS doubles for every 9 deg C!
-
SubthresholdSubthreshold Leakage ComponentLeakage Component
-
Static Power ConsumptionStatic Power Consumption
Vin=5V
Vout
CL
Vdd
Istat
Pstat = P(In=1).Vdd . Istat
Wasted energy Should be avoided in almost all cases,but could help reducing energy in others (e.g. sense amps)
-
Principles for Power ReductionPrinciples for Power Reduction
qPrime choice: Reduce voltage! Recent years have seen an acceleration in
supply voltage reduction Design at very low voltages still open
question (0.6 0.9 V by 2010!)
qReduce switching activityqReduce physical capacitance Device Sizing: for F=20
fopt(energy)=3.53, fopt(performance)=4.47