I/O Systems and Connections

Disk, Graphics Display, Printer, Mouse, Keyboard,....

The Interface

(See Chapter 8)

System Architecture

Processor

Cache

I/OController

I/OController

I/OController

Main Memory

Graphicsdisplay

Keyboard

main bus

interrupts

Types of I/O Devices

Behaviour• input, output, storage

Partner• human or machine

Data rate• peak rate at which data can be sent to

main memory or to processor

Examples

Device Behaviour Partner Data Rate KB/seckeyboard input human 0.01Mouse input human 0.02LaserPrinter output human 100Graphics output human 30,000Floppy disc storage machine 50Magnetic disc storage machine 2,000

The system architecture and bus communications system must accommodate an enormous variety of “peripheral” devices, with huge differences in performance.

Magnetic Discs

Rotating platters coated with magnetic surface• 2 to 20 platters• rotation at about 5000 RPM

Divided into (~2000) concentric circles (tracks)

Each divided into sectors (32-128) The sector is like a “block” or “page” - it

is the fundamental unit of a transaction.

Disk Performance

Arms move across rotating platters, reading or writing information.

Seek time• the arm locating the proper track

rotational latency• getting to right sector

– At 5,000rpm, each rotation takes 200 microseconds (s)– In 200s a 500MHz CPU executes 100,000 cycles!

transfer time• time to transfer the sector of information

– A 2KB page might take 1 second (s)– In 1s a 500MHz CPU executes 500,000,000 cycles!

Role of the Operating System

The OS acts as an interface between the hardware and the program requesting I/O

Responsibilities of OS include• equitable sharing of i/o between many

programs using the CPU• handling “interrupts” generated by the i/o

controllers• managing the many detailed concurrent

events that must be processed consistently.

From Processor to Device

Two main methods for the processor to give commands to a device• memory mapped

– involves the processor writing information to reserved segments of memory that the i/o controller examines and interprets as commands

– good example of this is graphics display.

• special i/o instructions– communicating commands directly over the bus

From Device to Processor

Two main methods for the device to communicate requests to processor• polling

– the device places information in special registers that the processor samples at regular intervals to see if anything has changed

• interrupts– The device sends a special signal to the processor,

which can continue to execute the current instruction, and then hand control over to the OS to service the interrupt.

Memory - Device Interface

Transfer of data between memory and device can also use polling or interrupts, relying on CPU to manage this through the OS.• cost can be extremely heavy for transfers of

very large amounts of data (eg, a sector) between disk and main memory.

In practice Direct Memory Access is used.

Direct Memory Access (DMA) Data is transferred between memory and disk

directly without involving the processor.• Interrupt still tells CPU when such a transfer has

started and finished. DMA involves

• CPU tells the DMA controller operation to perform and addresses involved.

• DMA controller then carries out the operation without bothering the CPU - arbitrates for the bus.

• Informs the CPU when complete.

Buses - Connecting all together Bus is a set of wires that forms a shared

communications link between the various subsystems. (Control+data lines).

Three types of buses:• processor-memory

– short, high-speed, specialised for max. memory-processor communications

• I/O bus– long, many different types of device.

• backplane (literally built into chassis)– processor, memory, & devices coexist on a single bus.

Bus Timing

Synchronous• Controlled according to clock cycle counts in

the control lines + a fixed protocol for commands.

• Requires every device on the bus to run at same speed

Asynchronous• Not clocked• control by “handshaking”

Accessing the Bus

Many devices simultaneously competing for the bus - to send or receive data.

Bus arbitration is the means whereby a “bus master” gains control temporarily over the activities on the bus.

Several schemes whereby bus arbitration may be resolved - all based on notions of priority.

Bus Standards

Characteristic VME IPI SCSItype backplane I/O I/Odata width 16-32bits 16 8bus masters multiple single multipleClocking Asynch Asynch Eitherbandwidth 12.9 MB/s 25MB/s 5 or 1.5 MB/smax devices 21 8 7max length 0.5m 50m 25m

IPI = Intelligent Peripheral InterfaceSCSI = Small Computer Systems Interface

THE END

This is the end of the formal material Still to come:

• Recap and revision• Past papers