is 151 lecture 11

IS 151 Digital Circuitry 1

Edge-Triggered Flip Flops

• A flip flop is a synchronous bistable device• Synchronous - the output changes state only at

a specified point on a triggering input clock• An edge-triggered flip-flop changes state either

at the– positive edge (rising edge) or – negative edge (falling edge) of the clock pulse – The flip flop is sensitive to its inputs only at this

transition of the clock


Edge-Triggered Flip Flops

• Three types of flip-flops– S-R– D– J-K


Edge-Triggered S-R Flip Flop

• Synchronous – because data on its inputs are transferred to the flip flop output only on the triggering edge of the clock pulse

• When S = 1 and R = 0, Q = 1 on the triggering edge of the clock pulse – SET

• When S = 0 and R = 1, Q = 0 on the triggering edge of the clock pulse – RESET

• When S = R = 0, the output does not change• When S = R = 1, invalid condition

– Same operation as the gated S-R latch• The flip flop cannot change state except on the

triggering edge of a clock pulse



• Operation of the positive-edge-triggered flip-flop

S = 1, R = 0, flip flop SETS on the positive clock edge

If already SET, it remains SET

S

C

R

Q

Q’t0

1

0



S = 0, R = 1, flip flop RESETS on the positive clock edge

If already RESET, it remains RESET

S

C

R

Q

Q’t0

0

1




S = 0, R = 0, flip flop does not change

If SET, it remains SET; if RESET, it remains RESET

S

C

R

Q

Q’t0

0

0




• Truth table

Inputs Outputs Comments

S R CLK Q Q’

0 0 X Q0 Q’0 No Change

0 1 0 1 RESET

1 0 1 0 SET

1 1 ? ? Invalid

= Clock transition LOW to HIGHX = irrelevantQ0 = output level prior to clock transition



• Example – determine the Q and Q’ output waveforms of an edge-triggered flip flop for the S, R and CLOCK inputs. Assume that the FF is initially RESET

Q

CLK 1 2 3 4 5 6

S

R

Q’



• Determining the Q and Q’ outputs– At clock pulse 1, S = 0, R = 0, Q does not change (Q = 0)– At clock pulse 2, S = 0, R = 1, Q is RESET (Q = 0)– At clock pulse 3, S = 1, R = 0, Q is SET (Q = 1)– At clock pulse 4, S = 0, R = 1, Q = RESET (Q = 0)– At clock pulse 5, S = 1, R = 0, Q = SET (Q = 1)– At clock pulse 6, S = 1, R = 0, Q = SET (Q = 1)


Applications of Sequential Circuits - Counters

• Flip flops can be used to perform counting operations

• 2 categories:– Asynchronous – events that do not have a

fixed time relationship with each other– Events do not occur at the same time– In an asynchronous FF, the first flip flop is

clocked by the external clock pulse and then each successive flip flop is clocked by the output of the preceding flip flop



– In a synchronous – the clock input is connected to all of the flip flops so that they are clocked simultaneously

• e.g. 2-bit asynchronous binary counter requires 2 flip flops; 3-bit counter requires 3 flip flops



• 2-bit Asynchronous Binary Counter

CLK

J0

C

K0

Q0

Q0’

J1

C

K1

Q1

HIGH

FF0 FF1


2-bit Asynchronous Binary Counter Operation

• The clock line (CLK) is connected to the clock input of only the first flip flop, FF0

• The second flip flop, FF1, is triggered by the Q’0 output of FF0

• FF0 changes state at the positive-going edge of each clock pulse

• FF1 changes state only when triggered by a positive-going transition of the Q’0 output of FF0



• Timing diagram–E.g. apply 4 clock pulses to FF0 and

observe the Q output of each flip flop–Both flip flops are connected for toggle

operation (J = K = 1)–Q is initially RESET (0)



• Timing diagram

Q1

CLK 1 2 3 4

Q’0

Q0



• On the positive-going edge of CLK 1 (clock pulse 1), Q0 = HIGH, Q’0 = LOW

• Q’0 being LOW, no effect on FF1 (a positive-going transition must occur to trigger the flip flop)

• On the positive-going edge of CLK 2, Q0 = LOW, Q’0 = HIGH

• Q’0 being HIGH triggers FF1, causing Q1 to go HIGH• On the positive-going edge of CLK 3, Q0 = HIGH, Q’0 =

LOW• Q’0 being LOW, no effect on FF1, Q1 remains HIGH• On the positive-going edge of CLK 4, Q0 = LOW, Q’0 =

HIGH• Q’0 being HIGH triggers FF1, causing Q1 to go LOW



If Q0 represents the Least Significant Bit (LSB) and Q1 represents the Most Significant Bit (MSB), the sequence of counter states is actually a sequence of binary numbers

• Clock Pulse Q1 Q0

• Initially 0 0 binary 0• 1 0 1 binary 1• 2 1 0 binary 2• 3 1 1 binary 3• 4(recycles) 0 0 binary 0• Recycle means transition of a counter from its final state back to its

original state



• Propagation delay– The effect of the input clock pulse is first ‘felt’ by FF0.

This effect cannot get to FF1 immediately because of the propagation delay through FF0

– The same happens to each flip flop until the last one– Total propagation delay = propagation delays in each

flip flop– E.g. if each flip flop in the example given has a

propagation delay of 5ns, the total propagation delay is 5ns x 2 = 10ns

– Maximum clock frequency = 1/total propagation delay = 1/10ns = 10GHz

is 151 lecture 11

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