is dual gate device structure better from a thermal perspective? d. vasileska, k. raleva and s. m....

Is Dual Gate Device Is Dual Gate Device Structure Better From a Structure Better From a Thermal Perspective?Thermal Perspective?D. Vasileska, K. Raleva and D. Vasileska, K. Raleva and

S. M. GoodnickS. M. GoodnickArizona State UniversityArizona State University

Tempe, AZ USATempe, AZ USA

Ira A. Fulton School of Engineering

AINE – Arizona Institute for Nanoelectronics

Technology Trends and Device Technology Trends and Device Miniaturization SolutionsMiniaturization Solutions



Why Heating Effects in Alternative Why Heating Effects in Alternative Device Geometries?Device Geometries?

dS

~ 300nm



Complexity of the Problem: Complexity of the Problem: Treatment of PhononsTreatment of Phonons

10-9

10-8

10-7

10-6

0

0.2

0.4

0.6

0.8

1

Silicon layer thickness (m)

MolecularDynamics

Phonon Boltzmann Transport Equation

Fourier Law

Classical SOI StructuresSuperlattice

Nanotubes

10-9

10-8

10-7

10-6

0

0.2

0.4

0.6

0.8

1

Silicon layer thickness (m)

MolecularDynamics

Phonon Boltzmann Transport Equation

Fourier Law

Classical SOI StructuresSuperlattice

Nanotubes

-Phonon mean free path(=300nm)

-phonon mean freelength (=1-2nm)

High Electric Field

Optical Phonon Emission

Acoustic Phonon Emission

Heat Conduction in Semiconductor

~ 0.1ps ~ 0.1ps

~ 10ps

~ 10ps

Hot Electron Transport



ASU SolutionASU Solution

J. Lai and A. Majumdar, “Concurent thermal and electrical modeling of submicrometer silicon devices”, J. Appl. Phys. , Vol. 79, 7353 (1996).



Thermal EMC Device SimulatorThermal EMC Device Simulator

Initialize

Calculate Scattering Table

Free-flight scatter

Check contacts

Solve Poisson

Current Convergence

Solve PhononEnergy BalanceEquations

Ensemble Monte Carlo Device

Simulator

Phonon Energy Balance Equations

Solver

TA

TLO

nvd

Te

Find electron position in a gr id:(i,j)

Find: TL(i,j)=TA(i,j) and TLO(i,j)

Select the scattering table with “coordinates”: ( TL(i,j)=TLO(i,j))

Generate a random number and choose the scattering mechanism

for a given electron energy

Ensemble Monte Carlo Device

Simulator

Phonon Energy Balance Equations

Solver

TA

TLO

nvd

Te











Exchange of Variables



The Role of Velocity Overshoot:The Role of Velocity Overshoot:Less Current DegradationLess Current Degradation

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7

x 10-8

-0.5

0

0.5

1

1.5

2

2.5x 10

5

x (m)

Vel

oci

ty (

m/s

)

Vds=1.2VVds=1.1VVds=1.0VVds=0.8VVds=0.6VVds=0.4V

channelsource drain

25 nm Channel Length Device

0 0.2 0.4 0.6 0.8 1 1.20

0.5

1

1.5

2

Vds (V)

Ids

(m

A/u

m)

isothermalT=300K

isothermalT=400K

thermalsimulations



Longer Channel Devices Affected MoreLonger Channel Devices Affected More

25 nm FD SOI nMOSFET (Vgs=Vds=1.2V)

10 20 30 40 50 60 70

3

8

1313


20 40 60 80 100 120

3

12

2121


20 40 60 80 100 120 140 160 180

3

15

2727

300

400

500

300

400

500

300

400

500

source contact drain contact

source region drain region


50 100 150 200

3

20

3535


50 100 150 200 250

3

21

3939


50 100 150 200 250 300

3

23

4343

300

400

500

600

300

400

500

300

400

500


10 20 30 40 50 60 70

3

8

1313


20 40 60 80 100 120

3

12

2121


20 40 60 80 100 120 140 160 180

3

15

2727 300

400

500

300

400

500

300

400

500

600

source contact drain contact


50 100 150 200

3

20

3535


50 100 150 200 250

3

21

3939


50 100 150 200 250 300

3

23

4343 300

400

500

600

400

600

300

400

500

600

T=300 K on gate T=400 K on gate

Hot-Spot Moves Towards theChannel for LargerDevices

AcousticPhononTemperature



Can We Further Minimize Lattice Can We Further Minimize Lattice Heating Problems in Nanodevices?Heating Problems in Nanodevices?

OUR ALTERNATIVES:

BOX

Bottom gate

Source (n+) Drain (n+)

Si substrate

Dual Gate Devices

0 25 50 7575

0

2

4

6

8

10

x (nm)

y (

nm

)

300

305

310

315

320

325

330

335

source drain



Double-Gate SOI:Double-Gate SOI:From Electrical PerspectiveFrom Electrical Perspective

+ Enhanced SCE scalability

+ Lower junction capacitance

+ Light doping possible

+ Vt can be set by WF of metal

gate electrode

+ ~2x drive current

- ~2x gate capacitance

- High Rseries,s/d raised S/D

- Complex process

Tsi, Ultra-thin Body, Fully Depleted

S D

Top

Bottom

Double-Gate SOI:

BOX

SUBSTRATE



Double-Gate SOI:Double-Gate SOI:From Thermal PerspectiveFrom Thermal Perspective

0 10 20 30 40 50 60 70380

400

420

440

460

480

500

520

540

560

580

along the channel (nm)

Tem

per

atu

re (

K)

Average acoustic and optical phonon temperature profile in the silicon layer

25nm single-gateFD SOI nMOSFET

25nm dual-gateFD SOI nMOSFET

lattice temperature profile

optical phonon temperature profile

channelsource drain Higher Numberof Carriers

Higher LatticeTemperature

More VelocityDegradation



A Closer Look …A Closer Look …

0 25 50 7575-2

0

2

4

6

8

10

12

14

16

18x 10

4


Vel

oci

ty (

m/s

)

0 25 50 75750

0.1

0.2

0.3

0.4

0.5

0.6

0.7


En

erg

y (e

V)

dual-gatesingle-gate

Average electron velocity and energy for 25nm single-gate and dual-gate FD SOI nMOSFET

10 20 30 40 50 60 70

10

20

30

40

50

60

X= 68Y= 6Level= 560.9467

x (nm)

y (n

m)

Lattice temperature profile for 25nm DG SOI MOSFET

X= 15Y= 9

Level= 416.422

300

350

400

450

500

550

bottom gateregion

set to 300K

10 20 30 40 50 60 70

10

20

30

40

50

60

Lattice temperature profile for undoped, single-gate 25nm FD SOI MOSFET

300

320

340

360

380

400

420

440

460

480

500

Single gate lattice temperature profile

Dual gate lattice temperature profile



Where Does the Where Does the Benefit of the DG Benefit of the DG Structure Comes Structure Comes From?From?

25nm DG SOI nMOSFET(Vgate-top=Vgate-bottom=1.2V; Vdrain=1.2V; Vsource=0V; Vsubstrate=0V)

Type of simulation

Top gate temperature

Bottom gate temperature

Bottom of the BOX

temperature

Current(mA/um)

Current decrease

(%)

isothermal 300K 300K 300K 3.0682 \

thermal 300K 300K 300K 2.7882 9.13

thermal 400K 400K 300K 2.6274 14.37

thermal 600K 600K 300K 2.3153 24.54

Type of simulation

Gate temperatur

e

Bottom of the BOX

temperature

Current(mA/um)

Current decrease

(%)

isothermal 300K 300K 1.9428 \

thermal 300K 300K 1.7644 9.18

thermal 400K 300K 1.6641 14.35

thermal 600K 300K 1.4995 22.82

ND=1019 cm-3; NA= 1018 cm-3

tox=2nm; tsi=10nm; tBOX=50nm

25nm FD SOI nMOSFET

25nm DG SOI nMOSFET

For almost the sameCurrent degradationDG devices offer1.5-1.7 times morecurrent



What Needs to be Done in Terms What Needs to be Done in Terms of Modeling Thermal Effects?of Modeling Thermal Effects?

When the heat conduction is nonlocal, the transport is highly When the heat conduction is nonlocal, the transport is highly nonequilibrium, the temperature used to represent the nonequilibrium, the temperature used to represent the modeling results is at best a measure of the local energy modeling results is at best a measure of the local energy density, rather than their typical thermodynamic meaning. density, rather than their typical thermodynamic meaning. On the other hand, in microelectronics, the device reliability On the other hand, in microelectronics, the device reliability

is often associated with the temperature through the is often associated with the temperature through the Arrehnius law, which is a manifestation of the Boltzmann Arrehnius law, which is a manifestation of the Boltzmann distribution and is a result obtained under the assumption distribution and is a result obtained under the assumption of local equilibrium.of local equilibrium.

The simulations so far are based on either Monte Carlo The simulations so far are based on either Monte Carlo methods or the Boltzmann equation and take the various methods or the Boltzmann equation and take the various relaxation times as input parameters. These parameters are relaxation times as input parameters. These parameters are subject to a wide range of uncertainties. subject to a wide range of uncertainties. There is a clear need for more accurate information on the There is a clear need for more accurate information on the

relaxation times. Molecular dynamics simulation may be relaxation times. Molecular dynamics simulation may be one way to obtain them.one way to obtain them.

Similarly, electron-phonon scattering processes also need Similarly, electron-phonon scattering processes also need further consideration, particularly when electrons have very further consideration, particularly when electrons have very different temperatures from that of phonons.different temperatures from that of phonons.

is dual gate device structure better from a thermal perspective? d. vasileska, k. raleva and s. m....

Documents

gate temperature

current slide

nm slide

nanoelectronics complexity

dual gate devices

nm channel length device

box substrate slide

velocity degradation