Part 3

Bus Systems

The two components discussed so far, microprocessor and memory, are not yet enough to builda complete computer. These components are the heart and brain of the machines but some more* organs» (to continue the biological theme) are still necessary. Their number, tasks and connec-tions are the actual implementation of a computer architecture. For example, drives and thegraphics adapter must be accessed, and the interrupts issued by them should be handled ac-cordingly by the processor-memory system. A major - and for the enormously successful IBM-compatible personal computer, decisive - property is the very flexible bus system with theexpansion bus (or slot). The simple installation of a variety of LAN, graphics and other adaptersis only then possible. For that reason, Part 3 is dedicated to the structure (and architecture) ofthe various «classes» of personal computers and their accompanying bus systems.

You can, of course, combine the chips described earlier, and those described later, and constructa robot or a laser printer controller, for example; one advantage of microprocessors is theirflexibility. You may also meet the chips described in this book in other products, such as inyour washing machine or in an aeroplane. But let us now turn to the actual architecture of thePC/XT.

20 The 8-bit PC/XT Architecture

The PC/XT was the first IBM personal computer. For today's demands it would not be sufficienteven for simple computer games; its 8-bit architecture is far out-dated. Nevertheless, manycomponents have survived from the PC/XT decade up to the i486 and Pentium machines, forexample, the 8237A DMA chips or the PIC 8259A. Their logical structure still determines thebehaviour of the most advanced chip set. I will discuss the PC/XT structure mainly for reasonsof completeness.

20.1 The Components and Their Cooperation

Aigure 20.1 shows a block diagram of a PC/XT. If you have looked in vain for the chip namesindicated in the figure on your motherboard, this doesn't mean that you didn't buy a PC!Instead, the chips will have been provided' by a third-party manufacturer, or the functions ofseveral chips integrated into a single chip. But the functional construction, and therefore thearcriitecture, remains the same. Therefore, I only want to describe the basic configuration.

521

8-bit PC/XT Architecture 523

Figure 20.1: The PC/XT architecture.

The central part is of course the processor. In a PC you will find an 8088 and in an XT the 8086.For a short time, an XT/286 was also on the market with the newer and more powerful 80286,but it did not have any other modification. This XT/286 was soon replaced by the more power-ful and modern AT.

In addition to the 8086/88, a mathematical 8087 coprocessor can be Installed, or at least a socketfor It may be present on the motherboard. An 8284 clock generator generates the system clock,and in the first PC was supplied with a crystal signal of 14 318 180 Hz. The 8284 divides thisfrequency by 3 to generate the effective system clock of 4.77 MHz. In more modern turbo-PC/XTs an oscillator with a higher frequency Is present, which enables a system clock of 8 MHzor even 10 MHz. Further, an NEC CPU called V30 or V20 may be present Instead of the 8086/88. The V30 and V20 are faster and have a slightly extended Instruction set compared to the8086/88, but are entirely downwards compatible with the Intel CPUs. The enhanced instructionset is of no use In a PC, as it can't be used for compatibility reasons.

A further essential component of the computer Is the main memory. The processor is connectedto It via the data, address and control buses. The CPU addresses the memory by means of theaddress bus, controls the data transfer with the control bus, and transfers the data via the databus. The necessary control signals are generated by the 8288 bus controller according to Instruc-tions from the 8086/88. In order to carry out data exchange In as error-free and orderly a wayas possible, the signals are buffered and amplified In various address and data buffer circuits.In the PC/XT four different address buses can be distinguished:

- local address bus: comprises the 20 address signals from the 8086/88. External addressbuffers and address latches separate the local bus from the system address bus.

_ system address bus: this is the main PC/XT address bus and represents the latched versionof the local address bus. The signal for latching the address signals on the local address businto the latches for the system address bus is ALE. In the PC/XT the system address busleads to the bus slots.

- memory address bus: this is only Implemented on the motherboard, and represents themultiplexed version of the system address bus. Via the memory address bus, the row andcolumn addresses are successively applied to the DRAM chips (see Chapter 19).

- X-address bus: this is separated from the system bus by buffers and drivers, and serves toaddress the I/O units and the ROM BIOS on the motherboard. These may, for example, bethe registers of the interrupt controller, the timer or an on-board floppy controller. I/O portsand BIOS extensions on expansion adapters are accessed by the system address bus.

Besides the four address buses there are four different data buses:

- local data bus: comprises the 16 or eight data signals from the 8086/88. Additionally, a buslogic is necessary to distinguish byte and word accesses. External data buffers and datalatches separate the local data bus from the system data bus. In the PC the local data bus iseight bits wide, and in the XT it is 16 bits wide.

- system data bus: Is the latched version of the local data bus in the PC/XT, and has eight bitsin the PC and 16 bits in the XT. One byte of the system data bus leads to the bus slots.

- memory data bus: this is only present on the motherboard, and establishes the connectionbetween main memory and the system data bus. In the PC the memory data bus is eight bitswide, and in the XT it Is 16 bits wide.

- X-data bus: this is separated from the system bus by buffers and drivers and accesses I/Ounits and the ROM BIOS on the motherboard. I/O ports and BIOS extensions on expansionadapters are accessed by the system data bus.

As already mentioned, the difference between the 8086 and the 8088 is the different width oftheir data buses. The 8086 has a 16-bit data bus, but the 8088 only has an 8-bit one. Therefore,in the PC the data bus on the motherboard for an access to main memory Is only eight bits wide,but in an XT it is 16 bits wide. Besides the main memory on the motherboard, the CPU can alsoaccess chips on the adapter cards In the bus slots. A more detailed explanation of the structureand functioning of the bus slots is given below. Here, I only want to mention that all essentialsignals of the system bus lead to the bus slots, for example address, data and certain controlsignals necessary to integrate the adapter cards into the PC system.

In this respect, it is also Important that in an XT the data bus Is guided into the bus slots withonly eight bits. In a 16-bit access via the complete 16-bit data bus of the 8086, an 8/16-convertermust carry out the separation of one 16-bit quantity into two 8-bit quantities, or has to combinetwo 8-bit quantities into one 16-bit quantity. On the XT motherboard this is not necessary. Thememory access is always carried out with the full width of 16 bits. On an XT this has, of course,enormous consequences for accesses to on-board memory on the one hand and to memory onan adapter card which is located in one of the bus slots on the other. Because of the limited 8-bit width for accesses to memory on the adapter card, less data is transferred each time. Thus,

524 Chapter 20 The 8-bit PC/XT Architecture

the data transfer rate is smaller. If 16-bit values are to be transferred then these values must beseparated Into two 8-bit values, or they must be combined from them. This takes some time, andthe access time for accessing the memory expansion adapter card Increases further compared tothe on-board memory. This is especially noticeable on a turbo XT. The ancestor PC only ran at4.77 MHz; with this clock rate the bus slots and inserted adapter cards don't have any problemin following the clock, but with the 10 MHz turbo clock this is not the case. In most cases, theslow bus slots are run at only half the turbo clock speed, that is, 5 MHz. An access to expansionmemory on the adapter card is therefore slower In two ways: the 8/16-bit conversion lasts onebus cycle, and halving the bus frequency decreases the transfer rate further. Therefore, youshould always choose to expand the on-board memory as long as the motherboard can accom-modate additional memory chips. That Is especially true for fast-clocked 1386 and 1486 comput-ers. Even in these PCs, the bus slots run at 8 MHz at most. What a shock for the proud ownersof a 50 MHz computer! Some PCs have a dedicated memory slot besides the normal bus slots.Special memory adapter cards may be Inserted Into these memory slots to run at a higherfrequency than the bus slots.

To decode the processor's addresses In a memory access, the PC/XT includes an address multi-plexer. Together with the memory buffer, It drives the memory chips on the motherboard. Thecheck logic for memory parity Issues an NMI If the data doesn't conform to the additionallyheld parity bit at the time of data reading. The parity check Is carried out on a byte basis, thatIs, each individually addressable byte in main memory is assigned a parity bit. When youextend your storage, therefore, you not only have to Insert the «actual» memory chips, but alsoan additional chip for every eight memory chips. This nineth chip holds the corresponding paritybits. Generally, the memory is divided into banks which must always be completely filled. Howmany chips correspond to a bank depends on the number of data pins that one chip has foroutputting or inputting data.

The older 64 kbit or 256 kbit chips usually have only one data pin. If memory is organized ineight bits, as is case for a PC (that is, If It has an 8-bit data bus), then one bank is usually madeup of eight memory chips plus one chip for parity. The reason Is that In a read or write access,one byte Is always transferred at a time, and therefore eight data connections are necessary.With a 16-bit organization, 18 chips (16 data chips plus two parity chips) are required. If youdon't fill a bank completely then the address multiplexer accesses «nothing» for one or morebits, and the PC unavoidably crashes. However, do not mix these «expansion banks» with thebanks of an interleaved memory organization. Because of the low PC/XT clock rates, an Inter-leaved access to the main memory is unnecessary. Modern DRAMs can handle 10 MHz withoutany problem; the banks need not be interleaved. An expansion bank only determines the small-est unit by which you may expand the memory.

The PC/XT also has a ROM, where code and data for the boot~up process and the PC's BIOSroutines are stored. The 8086/88 accesses the BIOS In ROM in the same way as it does withmain memory. Wait cycles during an access to main memory, ROM or the I/O address spaceare generated by the wait state logic.

For supporting CPU and peripherals an 8259A Programmable Interrupt Controller (PIC) Ispresent In the PC/XT. It manages external hardware Interrupts from peripherals such as thehard disk controller or timer chip. The 8259A has eight input channels connected to a chip, each

NMIIRQOIRQ1IRQ2IRQ3IRQ4IRQ5IRQ6IRQ7

02h08h09hOahObhOchOdhOehOfh

of which may issue an interrupt request. In the PC these channels are called IRQ0-IRQ7. Table201 shows the assignment of Interrupt channel IRQx and the corresponding peripheral orsupport chip. How the 8259A.works and how you may program it Is explained in Chapter 26.

Channel Interrupt Used by

parity, 8087 faultchannel 0 of timer 8253keyboardreservedCOM2COM1hard disk controllerfloppy disk controllerLPT1

Table 20.1: Hardware interrupt channels

Another support chip is also present, the 8253 programmable interval timer (PIT) (or timer •chip). It has three Individually programmable counters in all (see Table 20.2). Counter 0 Is usedin the PC/XT to update the internal system clock periodically. For this purpose, this counter isconnected to IRQO of the PIC The hardware Interrupt issued in this way updates the internalclock. This clock may be read or written using the DOS commands TIME and DATE. Counter1 together with the DMA chip carries out the memory refresh, and counter 2 generates a tonefrequency for the speaker. In Chapter 27, details on the operation modes and programming ofthe PIT 8253 and speaker are given.

Channel Used by

0 internal system clock (IRQO)1 memory refresh2 speaker frequency

Table 20.2: PC/XT timer channel

The keyboard is connected to the PC/XTs system bus by an 8255 programmable peripheralInterface (PPI) (see Section 29.2). With the same chip, the BIOS can check the system configu-ration, which is set by DIP switches. But newer turbo XTs, like the AT, have a real-time clockand a CMOS RAM, which holds all necessary configuration data. Thus, DIP switches are nolonger necessary. However, the PC/XT accesses the keyboard through the 8255. Also connectedto the PPI are the speaker and the cassette logic for driving the cassette drive. Using the 8255,the speaker is either enabled or disconnected (the cassette drive is only of historical importancetoday).The whole PC is powered by a power supply that outputs voltages of -12 V, -5 V, 0 V, +5 V and+12 V. The adapter cards in the bus slots are usually powered by corresponding contacts in thebus slots. Only «current eaters», for example FileCards with integrated hard disk drives, mustbe directly connected to the power supply.

526The 8-bit PC/XT Architecture

527

As hardware comporients/ the support chips mentioned above are accessed via ports in theI/O address space. Thus, the PC/XT uses I/O mapped input/output (I/O). Table 203 shows theport addresses of the most important hardware components in the PC/XT.

OOOh-OOfh020h-021h040h-043h060h-063h080h-083hOaOh-OafhOcOh-OcfhOeOh-Oefh100h-1ffh200h-20fh210h-217h220h-24fh278h-27fh2f0h-2f7h2f8h-2ffh300h-31fh320h-32fh378h-37fh380h-38fh3a0h-3afh3b0h-3bfh3c0h-3cfh3d0h-3dfh3e0h-3e7h3f0h-3f7h3f8h-3ffh

DMA chip 8237APIC 8259APIT 8253PPi 8255DMA page registerNMi mask registerreservedreservedunusedgame adapterextension unitreservedparallel printerreservedCOM2prototype adapterhard disk controllerparallel interfaceSDLC adapterreserved

monochrome adapter/parallel interfaceEGACGAreservedfloppy disk controllerCOM1

The registers of hardware components on adapter cards that are inserted into the bus slots (forexample, the UART on the serial interface adapter or the 6845 on the graphics adapter) are alsoaccessed via port addresses. The PC/XT hands over all accesses to the I/O address space to thebus slots in the same way as for accesses to memory on adapter cards. Note that any address,no matter whether in the memory or I/O address space, may only be assigned a single compon-ent. If you assign the same I/O address to, for example, the UART registers of COM1 andCOM2, the chips disturb each other because they respond to the CPU's instructions (nearly) atthe same time. Thus the interfaces don't work at all, or at least not correctly.

To complete the picture, I will explain in advance the DMA architecture of the PC/XT (the pinsand signals of the 8237A, as well as the terms «page register», etc. are detailed in Chapter 28).

Besides the processor, there is another chip able to carry out memory and I/O accesses: the8237A DMA chip. It enables fast data transfer between main memory and I/O units such as thefloppy controller. Unlike the 8086/88, the 8237A cannot process data but only transfer it (at highspeed). The 8237A has four separately programmable transfer channels, used as indicated inTable 20.4.

Channel Used by

memory refreshSDLC adapterfloppy disk controllerhard disk controller

Table 20.4: PC/XT DMA channels

Channel 0 is reserved for memory refresh, and is activated periodically by the 8253A PIT tocarry out a dummy access to memory. The memory chips are thus refreshed. The remainingthree channels are available for data transfer. If, for example, the hard disk controller has readone sector then it activates channel 3 of the 8237A and hands the data transfer over to it withoutany intervention from the CPU. Besides the.8086/88 CPU, the 8237A Is another, independentchip for carrying out bus cycles; thus it Is a busmaster - but with a limited function. The function,programming and transfer protocol of the DMA chip are described in Chapter 28. The CPU andDMA chip are located on the motherboard. The PC/XT bus doesn't support external busmastersthat may be located on an adapter card in a bus slot. It would be useful, for example, if theprocessor of a network adapter could access the main memory independently and withoutintervention from the motherboard's CPU to deliver data to the network, or to transfer datafrom the network into main memory. But In a PC/XT (and also In an AT), the adapter mustissue a hardware interrupt to indicate the required data transfer to the CPU. Then the CPUcarries out this transfer. With the advent of EISA and the microchannel, though, busmastersmay be located on an external adapter card. They are then able to control the EISA bus or themicrochannel on their own.

20.2.1'.8-bit Channels

From Table 20.4 it is apparent that the 8237A mainly serves for a data transfer between mainmemory and an I/O device in a bus slot. As the PC/XT slots only encompass eight bits, onlyan 8-bit transfer takes place - the PC/XT has only 8-bit DMA channels. .Because of the 8088 processor the PC has only an 8-bit data bus and a 20-bit address bus, thusa DMA page register with a width of only four bits is required In the PC (their I/O addressesare listed in Table 20.5). The eight address bits from the 8237A plus eight address bits from theDMA address latch plus four bits from the page register together form a 20-bit address for thePC/XT address space. As an 8-bit chip, the 8237A Is perfectly designed for the 8088. Becauseof the 8-bit data bus only 8-bit DMA channels are possible. During the course of a read transferthe 8237A provides the memory address and activates the MEMR signal to read a data bytefrom memory onto the 8-bit data bus. Afterwards, it enables the IOW signal so the peripheral

T528

Chapter 20 The 8-bit PC/XT Architecture 529

Port

87h83h81h82h

rage register

channel 0channel 1* )

channel 2channel 3

*) simultaneously channel 0

Table 20.5: I/O addresses of the PC/XT page registers

can accept the data byte. A write transfer proceeds in exactly the opposite direction: the 8237Aoutputs the memory address and activates the IOR signal to read out a data byte from theperipheral's I/O register onto the 8-bit data bus. Afterwards, it enables the MEMW signal sothat the memory can fetch the data byte.

Note that in the PC/XT, channels 0 and 1 are assigned the same physical page register. Youaccess the same physical page register through the two different I/O addresses 87h and 83k Inthe AT, the page register for channel 4 - which serves only for cascading - holds the pageaddress for the memory refresh.

On the XT the situation becomes more ponderous and complex. Because of the 8086 the XT hasa 16-bit data bus internally. As Is the case on the PC, the only DMA chip present Is designedfor 8-bit channels to 8-bit peripherals. Only 8-bit devices can be Installed into the XT bus slotanyway, as the data bus only leads Into them with 8 bits. But because of the 16-bit data bus ofthe 8086, memory Is organized as 16-bit storage. This means that on the low-order data bus byteD0-D7 only data bytes with an even address (and on the high-order data bus byte D8-D15 onlydata bytes with an odd address) appear.

If the 8237A continuously counts up or down the source address during the course of a readtransfer, the Intended data byte appears on memory bus lines D0-D7 If an even address issupplied, and on lines D8-D15 If an odd address is output. Thus, an additional logic is requiredto transfer the data byte with an odd address onto data bus lines DO-D7 so that an 8-bitperipheral with an even I/O address can fetch It. At the same time, the memory only outputsthe data byte with an odd address without driving the lines D0-D7. In the same way as for aperipheral with an odd I/O address, an additional logic Is required to transfer the data bytewith an even address onto lines D8-D15, so that the 8-bit peripheral can actually fetch It. Asimilar problem arises with the 8086 if It attempts to read a data byte with an odd address fromor write a data byte with an odd address to the memory. The 8086 manages this by means ofthe control signal BHE which, together with the least significant address bit A0, disables theupper or lower half of the data bus.

The 8237A, on the other hand, continuously Increments or decrements the target address inmemory during the course of a write transfer, and the data byte from the 8-bit peripheral alwaysappears on the same data bus bits. With an even target address the data byte needs to appearon the low-order part D0-D7 of the memory bus; with an odd address, however, It appears onthe high-order part D8-D15 of the memory bus so that the memory can write the data byteupon activation of the MEMW signal to the memory location Intended.

ZG22 Memory Refresh

Channel 0 Is dedicated to memory refresh. For refresh purposes, counter 1 of the 8253/8254 PIToperates In mode 3 (square-wave generator) with a count value 18 (12h). Only the low-ordercounter byte is loaded (RW1 = 0, RW0 = 1), that is, the PIT generates a square wave with afrequency of 1.193 18 MHz/18 = 66 288 Hz. Counter 1 therefore Issues a DREQ every 15 us for adummy transfer, which refreshes the DRAMs. Channel 0 of the 8237A Is programmed In singletransfer mode with a read transfer for this purpose. During the course of the dummy cycle, theDMA chip reads data from the memory onto the data bus, whereby the address buffers, addressdecoders and sense amplifiers in the memory chips are enabled. This automatically leads to therefresh of one memory cell row. But the data Is not fetched by a peripheral, as no device hasissued a DREQ0 and would be able to respond to DACKG, MEMR and IOW. The data there-fore disappears upon the next bus cycle. Because all these control signals lead Into the bus slotsand are thus also available for the adapter cards, the dummy cycle may also refresh the memoryon expansion adapters (for example, graphics adapters). Only adapters with their own refreshlogic generate refresh cycles on their own.

The PIT defines the refresh time by means of the periodic square-wave signal. The DMA chipis used to generate the refresh address and the control signals for reading the main memory.The startup routine of the BIOS usually loads the count register with a suitable count value, andsets channel 0 to single transfer mode and autoinitialization. Thus every request via channel 1of the PIT Issues exactly one transfer, increments the refresh address, and decrements the countregister. If the count register reaches the value ffffh, then a TC occurs and channel 0 of the DMAcontroller Is automatically initialized. The refresh process starts from the beginning again.

20.2.3 Memory-Memory Transfer

On each of the channels a page register is allocated.- IBM, though, has implemented a commonpage register for channels 0 and 1 in the PC/XT. Therefore, memory-memory transfer Is onlypossible within a single DMA page of 64 kbytes, as only channels 0 and 1 can carry out thistransfer and have to share one register on the PC/XT. Note that channel 0 is further occupiedby the memory refresh. Before you issue a memory-memory transfer within the 64 kbyte pageyou must, therefore, disable the memory refresh. And don't forget to reprogram channel 0 afterthe transfer for the refresh again. Additionally, the refresh may only be interrupted for a shorttime period (less than 1 ms) by the memory-memory transfer, because otherwise the DRAM«forgets» data. Summarized, these are all requirements that make the memory-memory transferthrough the 8237A quite Inconvenient.

203 I/O Channel and Bus Slots

Most of the PC/XT system bus leads Into the bus slots, all of which have the same structure.Theoretically, it doesn't matter Into which slot you Insert your brand-new adapter card, but inpractice some adjoining adapter cards may disturb each other, so you may have to insert oneadapter into another slot. During bus cycles that only refer to components on the motherboard,

530Chapter 20

The 8-bit PC/XT Architecture 531

the slots are usually cut off from the system bus to minimize the load on the driver circuits, andto avoid any noise induced by the slots. Using the bus slot contacts, a PC/XT may be configuredvery flexibly. The inserted adapter cards behave like components that have been integrated ontothe motherboard. Figure 20.2 shows the structure and contact assignment of a bus slot.

GND B p i A1JRESET DRV Hi I

+5V H i I!RQ2 H i I-5V H i j

DRQ2 Hi ' j-12V H i j

res ^ B 9+12V I I I JGND ^PB1° A10(

MEMW H jMEMR

iowiOR

DACK3

m tIDRQ3 ^p i|

DACK1 ^fc •DRQ1 f/f i |

DACKO Hi mCLK ^p B 2 0 A2°i«

IRQ7 H •IRQ6 Hk •IRQ5 Hi •!RQ4 H i MIRQ3 H •

DACK2 j j j j i •TC • •

ALE HE •+5v HE Mosc HE ajGND BlB31 A31B

1• I/O CH CK| D 7

1 D6

1 D5• D4

• D2| D I

1 D0I I/O CH RDY• AEN

i A 1 9I A18

i A 1 71 A16• A151 A141 A13

I A 1 2I A11I A10I A91 A8

1*7IA6I A5I A4I A3IA2I A11A0

Figure 20.2: The PC/XT bus slot is kid out for an external 8-bit data bus, and has 62 contacts.

The following sections discuss the contacts and the meaning of the supplied or accepted signals.

A19-A0 (O)Terminals A12-A31

These contacts form the 20-bit address bus of the PC/XT, and either indicate the state of the8086/88 address signals directly, or are generated by DMA address logic.

AEN (O)Terminal All

If the address enable signal at this contact is active the DMA controller is controlling the bus fora data transfer. The processor and other peripherals are cut off from the bus.

ALE (O)Terminal B28

The address latch enable signal ALE is generated by the 8288 bus controller, and indicates thatvalid address signals are present on the bus. Adapter cards may now decode these signals.

CLK (O)Terminal B20

CLK is the system clock of the PC/XT. In the first PC, OSC was divided by 3 to generate thesystem clock with a frequency of 4.77 MHz.

D7-D0 (I/O)Terminals A2-A9

These signals form an 8-bit data bus for data transfer from or to adapter cards.

DACK3-DACKQ (I)Terminals B15, B17, B19, B26

These four DMA acknowledge contacts are used for acknowledging DMA requests DRQ3 toDRQ1, and for the memory refresh (DACKO). Once a DRQx request has been acknowledged bythe corresponding DACKx, the data transfer via the corresponding DMA channel may takeplace.

DRQ3-DRQ1 (I)Terminals B6, B16, B18

With these DMA request contacts a peripheral on an adapter card indicates to the motherboardsystem that it wants to transfer data via one of the three DMA channels. Channel 0 of the DMAchip is connected on the motherboard with channel 1 of the timer chip to periodically carry outmemory refresh. Therefore, DRQO doesn't lead to the bus slots. Lines DRQ3 to DRQ1 must beheld active until the corresponding DACK signal also becomes active; otherwise the DMArequest is ignored.

I/O CH CK (I)Terminal Al

With this I/O channel check contact the adapter cards flag errors to the motherboard to indicate,for example, a parity error on a memory expansion board, or a general error on an adapter card.An active I/O CH CK signal (that is, a low level signal) issues an NMI corresponding to inter-rupt 2 in the PC/XT.

I/O CH RDY (I)Terminal A10

The I/O channel ready contact receives the ready signal from addressed units on an adaptercard. If I/O CH RDY is low, the processor or DMA chip extends the bus cycle by inserting one

or more wait states.

532Chapter 20

IOR (O)Terminal B14

The I/O read signal at this contact indicates that the processor or the DMA controller wants toread data, and the addressed peripheral should supply data onto the data bus. An active IORcorresponds to an active IORC of the 8288 bus controller, which indicates a read access to theI/O address space.

Terminal B13

The I/O write signal at this contact indicates that the processor or the DMA controller wantsto write data, and that the addressed peripheral should take the data off the data bus. An activeIOW corresponds to the active IOWC of the 8288 bus controller, which indicates a write accessto the I/O address space.

LQ2-IRQ7 CDTerminals B4, B21-B25

These contacts transmit the hardware interrupt requests corresponding to channels IRQ2-IRQ7to the PIC on the motherboard. For example, the hard disk controller activates IRQ5 afterreading data from the disk into an internal buffer. The IRQO and IRQ1 lines are assignedchannel 0 of the timer chip and the keyboard, respectively. Therefore, they do not need to beintegrated into the bus slots.

Terminal B12

By an active memory read signal MEMR (that is, a low level signal), the motherboard tells theadapter cards that the processor or DMA controller wants to read data from main memory. Anactive MEMR corresponds to the active MEDC of the 8288 bus controller, which indicates aread access to memory address space.

TThe 8-bit PC/XT Architecture 533

This contact supplies a reset signal to reset the whole system at power-up or during a hardwarereset.

T/C.(O)Terminal B27

If the counter of a DMA channel has reached its final value, the DMA transfer is complete andthe terminal count terminal T/C supplies a pulse to Indicate the end of the DMA cycle.

Terminal Bll

By an active memory write signal MEMW (that Is, a low level signal), the motherboard tells theadapter cards that the processor or DMA controller wants to write data Into main memory. Anactive MEMW corresponds to the active METC of the 8288 bus controller, which indicates awrite access to memory address space.

OSC (O)Terminal B30

This contact supplies the oscillator's clock signal of 14 318 180 Hz,

RESET DRV (O)Terminal B2

535

There are no major differences between a PC and an AT, except that the PC with itsprocessor only has an 8-bit data bus internally on the motherboard. On the other hand, the XTdata bus internally comprises 16 bits. But in both PCs only 8 bits lead into the bus slots. Also,the internal structure is the same as far as the number and connections of the support chips8237A, 8259A, 8253, etc. are concerned. Compared to the XT, the AT is a significant advance (ATactually means advanced technology), and its architecture is quite different from that of the PC/XT. The following sections briefly present these main differences.

21 o1 Th @Hi a T

Figure 21.1 gives a block diagram of an AT. In most of today's ATs or AT-compatibles, severalchips are integrated into one single chip, but the functional groups remain the same. Therefore,you may not find any of the chips shown in Figure 21.1. If you look at the data sheet of yourmotherboard, though, you will recognize that in chip X the functions of, for example, the twoInterrupt controllers, etc. have been Integrated. It is the aim of Figure 21.1 to represent thefunctional structure of the AT as it was originally realized by individual chips, before thedevelopment of large-scale integration technology.

Here, the central part Is also the processor. In the AT you will find the 80286, with 24 addresslines. Thus, the AT may have 16 Mbytes of memory at most. Further, with the 80286 the AT canoperate In protected mode to run with advanced operating systems like OS/2 or UNIX. The A20address line Is controlled by the 8042 keyboard controller. It can be locked so that the 80286 inreal mode strictly addresses only the lowest 1 Mbyte of memory, and carries out a wrap-aroundlike the 8086/88. Unfortunately, some DOS-internal functions dating from the PC's Stone Agerely on this wrap-around, but compatibility with the Stone Age may be, in my opinion, a matterof taste.

In addition to the 80286, the 80287 mathematical coprocessor can be installed. Normally, thereis at least one socket for it present on the motherboard. The system clock Is supplied by the,82284 clock generator, which Is the successor of the PC/XT's 8284. The first AT ran with aneffective processor clock of 6 MHz, so that the clock generator had to supply twice this fre-quency (12 MHz). The processor clock frequency was Increased up to a giant 8 MHz with theAT03 model. Meanwhile, there are 80286 CPUs on the market (Harris or AMD, for example)which run with an effective processor clock of up to 25 MHz. But the support chips and the ATbus are nowhere near this frequency, so wait states are often required.

A further component of the AT (as In every computer) Is the main memory. The processor isconnected to It by means of data, address and control buses, as is the case In the PC/XT, TheCPU addresses the memory via a 24-bit address bus, controls the data transfer with the controlbus, and transfers the data via a 16-bit data bus. The necessary control signals are generated bythe 82288 bus controller, which Is the successor of the PC/XT's 8288, and which Is dedicated tothe 80286. To carry out the data exchange in as error-free and orderly a manner as possible, thesignals are buffered and amplified In various address and data buffers.

534

536Chapter 21 16-bit AT Architecture 537

In the AT and ail Its successors up to the EISA PC, five different address buses can bedistinguished:

- Local address bus: comprises the 24 address signals from the 80286. External address buffersand address latches separate the local bus from the system address bus.

- System address bus: as Is the case for the PC/XT, this bus Is the main address bus andrepresents the latched version of bits A0 to A19 of the local address bus. Thus the systemaddress bus in the AT is a 20-bit address bus. The signal for latching the address signals onthe local address bus Into the latches for the system address bus is ALE. In the AT, thesystem address bus Is led to the bus slots as A0 to A19.

- Memory address bus: this address bus is only present on the motherboard, and representsthe multiplexed version of the system address bus. Via the memory address bus, the rowand column addresses are sucesslvely applied to the DRAM chips (see Chapter 5).

- X-address bus: this bus is separated from the system bus by buffers and drivers, and servesto address the I/O units and the ROM BIOS on the motherboard. These may, for example,be registers of the interrupt controllers, the timer or an on-board floppy controller. On theother hand, I/O ports and ROM BIOS on extension adapters are accessed by the systemaddress bus,

- L-address bus: this bus comprises the seven hlgh-order (L = large) and non-latched addressbits A17-A23 of the local address bus. It leads Into the AT slots as LA17-LA23.

Besides these, there are four different data buses Implemented in the AT:

- Local data bus: comprises the 16 data signals from the 80286. Additionally, a bus logic Isnecessary to distinguish byte and word accesses. External data buffers and data latchesseparate the local data bus from the system data bus.

- System data bus: this is the latched version of the local data bus in the AT, and it Is 16 bitswide. The system data bus leads into the bus slots.

- Memory data bus: this data bus Is only present on the motherboard, and establishes theconnection between main memory and the system data bus.

- X-data bus: this bus Is separated from the system bus by buffers and drivers, and accessesI/O units and the ROM BIOS on the motherboard. I/O ports and BIOS extensions on exten-sion adapters are accessed by the system data bus.

Besides the main memory on the motherboard the CPU can also access chips on the adaptercards in the bus slots. A more detailed explanation of the construction and function of theAT slots Is given below. Unlike the XT, the data bus leads Into the bus slots with the full widthof 16 bits. The additional control and data signals are located In a new slot section with 38contacts. However, older XT adapters with an 8-bit data bus can also be Inserted Into the ATslots by means of the two newr control signals MEM CS16 and I/O CS16. The bus logic auto-matically recognizes whether a 16-bit AT or an 8-bit PC/XT adapter Is present In the bus slot.

An 8/16-bit converter carries out the necessary division of 16-bit quantities Into two 8-bit quan-tities, and vice versa. Like the PC/XT bus, the AT or ISA bus also supports only the CPU andthe DMA chips on the motherboard as busmasters which can arbitrate directly, without usinga DMA channel. On external adapter cards In the bus slots, no busmaster may operate andcontrol the AT bus. The arbitration Is carried out only indirectly, via a DMA channel, and notdirectly by a master request. It was not until EISA and the microchannel that such busmasterscould also operate from peripheral adapter cards.

The first AT model ran at a processor clock of only 6 MHz. The bus slots and the Insertedextension adapters have no problem In following the clock, but the situation is different witha turbo clock of, for example, 16 MHz. The inert bus slots then usually run with only half theturbo clock, that is, 8 MHz. Problems mainly arise with «half»-turbo clocks of 10 MHz or 12.5MHz. In most cases, the bus slots also run at this frequency, but only very high quality adapterssupport 10 MHz or even 12.5 MHz. The consequence is frequent system crashes, especially If thePC has been running for a long time and the warmer chips of the peripheral adapters can nolonger follow the clock. Meanwhile, the ISA standard (which corresponds to the AT bus In mostrespects) requires a clock frequency for the bus slots of 8.33 MHz at most. Even adapter cardsthat could run more quickly are supplied in ATs which strictly Implement this standard, withonly 8.33 MHz.

Unlike the bus slots, the main memory on the motherboard runs with the full processor clock,even if this is 25 MHz. The main memory controller may advise the CPU at most to insert waitcycles if the RAM chips are too slow. But advanced memory concepts such as paging or inter-leaving (see Chapter 19) shorten the memory access times. Thus, an access to memory expan-sions on adapter cards is much slower than an access to the on-board memory (remember thisif you want to extend your memory). You should always prefer an extension of the on-boardmemory as long as the motherboard can integrate more chips. This applies particularly to veryfast-clocked 1386 and i486 models. Some PCs have a special memory slot besides the normal busslots into which special memory adapter cards may be Inserted, largely running with the fullCPU clock so that no delays occur compared to the on-board memory.

To decode the processor's addresses In a memory access/the AT also has an address multi-plexer. Together with the memory buffer, it drives the memory chips on the motherboard. Thecheck logic for memory parity issues an NMI if the data does not conform with the additionallyheld parity bit at the time of data reading. Also, additional memory on an adapter card mayissue this memory parity error. Other sources for an NMI in an AT may be errors on an adaptercard, indicated by I/OCHCK. In the PC/XT the memory refresh was carried out only viachannel 0 of the DMA chip. This channel is activated periodically by channel 1 of the timer chip.In the AT, the refresh interval Is further defined by channel 1 of the timer chip, but the refreshItself Is usually carried out by a dedicated refresh logic driven by the timer channel 1. Thus,channel 0 would normally be available, but certain manufacturers do use it further for refresh.For this purpose, the lines DACKO and REF lead into the AT slots (see below).

Like the PC/XT, the AT also has a ROM for holding boot, code and data and the AT's BIOSroutines. Unlike the 8086/88, in the PC/XT the ATs 80286 may also be operated In protectedmode. These two operation modes are completely Incompatible, which Is, unfortunately, badnews for the BIOS: BIOS routines in real mode cannot be used by the 80286 In protected mode.

538Chapter 21 16-bit AT Architecture 539

Only the original AT, or other manufacturers' ATs, incorporate an advanced BIOS, which holdsthe corresponding routines for protected mode. The advanced BIOS is located in the addressspace just below 16 Mbytes. If you buy a freely available version of OS/2 then usually the disksnot only hold the operating system, but also the BIOS for protected mode. Thus, during theOS/2 boot process not only the operating system is loaded, but also the BIOS for protectedmode. The BIOS routines present in ROM are only used for booting as long as the 80286 is notswitched to protected mode.

For supporting the CPU and peripherals, the AT also has several support chips. Instead of one8259A programmable interrupt controller (PIC), two are present in an AT: one master PIC andone slave PIC. The 1NTRPT output of the slave is connected to the master's IR2 input, thus thetwo PICs are cascaded. Therefore, 15 instead of eight IRQ levels are available in the AT. Table21.1 shows the assignment of the interrupt channels IRQx to the various peripherals or supportchips. Besides the IRQs, the NMI also is listed as a hardware interrupt, but the NMI directlyinfluences the CPU, and no 8259A PIC is used for this purpose. Chapter 26 describes how the8259A operates and how it may be programmed.

Channel Interrupt

NMIIRQOIRQ1IRQ21RQ3IRQ4IRQSIRQ6IRQ71RQ8IRQ9IRQ10IRQ11IRQ12IRQ13IRQ14IRQ15

02h08h09hOahObhOchOdhOehOfhOfhOfhOfhOfhOfhOfhOfhOfh

Used by

parity, error on extension card, memory refreshchannel 0 of timer 8253keyboardcascade from slave PICCOM2COM1LPT2floppy disk controllerLPT1real time clockredirection to IRQ2reservedreservedreservedcoprocessor 80287hard disk controllerreserved

Table 21.1: AT hardware interrupt channels

Besides the PICs, a 8253/8254 programmable interval timer (PIT), or for short, timer chip, ispresent. The 8254 is the more developed successor to the 8253 but has the same function set. ItIncludes three individually programmable counters (see Table 21.2). Counter 0 is used for pe-riodically updating the internal system clock, as is the case in the PC/XT, and is connected tothe IRQO of the master PIC. The hardware interrupt issued thus updates the internal clock,which can be checked by means of the DOS commands TIME and DATE. Timer 1 periodicallyactivates the memory refresh, which is Indicated by an active signal REF in the AT bus slot.Counter 2 generates the tone frequency for the speaker. In Chapter 27 some details about theoperation modes and the programming of the 8253 PIT and the speaker are given.

Channel Used by

0 internal system clock (IRQO)

1 memory refresh2 speaker frequency

Table 21.2: AT timer channels

Unlike the PC/XT, the more modern and programmable keyboard of the AT is connected bya keyboard controller to the AT system bus. In the PC/XT, an 8255 programmable peripheralinterface (PPI) was included for this purpose. The functions of the AT keyboard and its succes-sor, the MF II keyboard, may be programmed (details are discussed in Section 34.1).

Instead of the DIP switches you will find a CMOS RAM in the AT. The CMOS RAM holds thesystem configuration and supplies it at power-up. EISA microchannel and PCI further extendthis concept: here you may even set up the DMA and IRQ channels used by EISA or microchanneladapters by means of an interactive program. These setups are stored in an extended CMOSRAM, and no jumpers need to be altered (after deinstalling all adapters to expose themotherboard .. .)• Together with the CMOS RAM, a real-time clock is integrated which periodi-cally updates date and time, even if the PC is switched off. The two DOS commands DATE andTIME are no longer necessary at power-up for setting the current date and time. They aremainly used for checking these values.

The whole AT is powered in the same way as the PC/XT, by means of a power supply thatsupplies voltages of -12 V, -5 V, 0 V, +5 V and +12 V. In the AT, too, the adapter cards in thebus slots are usually powered by corresponding contacts in the bus slots. Only «current eaters»like FileCards with Integrated hard disk drives must be directly connected to the power supply.As hardware components, the support chips mentioned are accessed via ports in the I/O ad-dress space. Thus, the AT as well as the PC/XT uses I/O mapped input/output (I/O). Table 213shows the port addresses of the most important hardware components In the AT.

Besides the 80286, ATs often also Include an 1386 or i486 processor, seldom a Pentium. Withthese processors, the on-board data and address buses (the memory address bus, for example)are usually 32 or 64 bits wide, but only 24 address lines and 16 data lines lead Into the bus slots,as is the case for an original AT. The conversion to 32-bit or 64-bit quantities is carried out byspecial swappers and buffers. In principle, the architecture of these 1386, i486 or Pentium ATstherefore doesn't differ from that of a conventional AT. Only the internal address and databuses may be adapted accordingly. The AT or ISA bus (as it is called in its strictly defined form)is very popular as an additional standard expansion bus for VLB and PCI systems. Thus, modernand very powerful graphics and drive host adapters can be Integrated into the system. On theother hand, cheap and readily available ISA adapters (for example, parallel and serial interfaces,games adapters, etc.) can also be used.

212 DIVSA Architecture

As already done for the PC/XT, I will also discuss the AT's DMA subsystem In connection withthe bus architecture. DMA basics are detailed in Chapter 28.

Chapter 21 16-bit AT Architecture 541

OOOh-OOfh 1st DMA chip 8237A02Gh-021h 1st PiC 8259A040h-043h PIT 8253060h-063h keyboard controller 8042070h-071h real-time clock080h-083h DMA page registerOaOh-Oafh 2nd PIC 8259AOcOh-Ocfh 2nd DMA chip 8237AOeOh-Oefh reservedOfOh-Offh reserved for coprocessor 80287100h-1ffh available200h~20fh game adapter210h-217h reserved220h-26fh available278h-27fh 2nd parallel interface2b0h-2dfh EGA2f8h-2ffh COM2300h-31fh prototype adapter320h-32fh available378h-37fh 1st parallel interface380h-38fh SDLC adapter3a0h-3afh reserved3b0h-3bfh monochrome adapter/parallel interface3c0h-3cfh EGA3d0h-3dfh CGA3e0h-3e7h reserved3f0h-3f7h floppy disk controller3f8h-3ffh COM1

Table 213: AT port addresses

21.2.1 8-bit and 16-bit Channels

For memory and I/O accesses without any intervention from the CPU, the AT has two 8237A° „ A ° h l p S W h k h a r e c a s c a d e d so that seven DMA channels are available. For that purpose an8237A is operated as a master, and is connected to the CPU. The HRQ and HLDA terminals ofthe slave DMA are connected to channel 0 of the master DMA so that slave channels 0-3 havea higher priority than the three remaining master DMA channels. Channels 0-3 of the masterare usually called the AT's DMA channels 4-7. The four slave DMA channels serve 8-bit periph-erals, and the other channels 5-7 are implemented for 16-bit devices. The use of the separatelyprogrammable transfer channels is listed in Table 21.4.

Channel 0 is reserved for memory refresh, although in most ATs their own refresh logic ispresent for the refresh process. The remaining three 8-bit channels are available for an 8-bit dataransfer. Usually, the DMA chips run with a much lower clock frequency than the CPU The

frequency is typically about 5 MHz (even in cases where the CPU is clocked with 25 MHz).Some ATs enable a DMA frequency of up to 7 MHz, not very exciting compared to the CPUdock. Thus it is not surprising that most AT hard disk controllers do not transfer data by DMA

Channel

01234567

Used by

reserved (memory refresh)SDLC adapter/tape drivefloppy disk controllerreservedcascade DMA1-»DMA2reservedreservedreserved

Width

8 bits8 bits8 bits8 bits

16 bits16 bits16 bits

Table 21.4: AT DMA channels

but by means of programmed I/O, because the 80286 runs much faster than an 8086/88 and theDMA chips. But the 16-bit hard disk controllers are sometimes served by one of the DMAchannels 5-7. Because of Its 16 Mbyte address space, the AT has an 8-bit page register (PC/XT:4-bit page register) to generate a 24-bit address together with the two 8-bit addresses from the8237A and the DMA address latch.

The functioning of the AT DMA is, in principle, the same as In the PC/XT; however, 24-bitaddresses can be generated, and 16-bit channels are available. During the course of a readtransfer the 8237A provides the memory address and activates the MEMR signal to read a dataword from memory onto the 16-bit data bus. Afterwards, it enables the IOW signal so theperipheral can accept one (8-bit channel) or two (16-bit channel) data bytes. A write transferproceeds In exactly the opposite direction: the 8237A outputs the memory address and activatesthe IOR signal to read out one or two data bytes from the peripheral's I/O register onto the 16-bit data bus. Afterwards, it enables the MEMW signal so that the memory can fetch the databyte(s). For that purpose, the system controller must be able to recognize whether an 8-bit or16-bit DMA channel is used and generate signals according to BHE and A0.

With an 80286 the data from the 8-bit peripheral must be put onto or taken off the low-orderor high-order part of the data bus (depending on the storage address). The situation becomeseven more ponderous with PCs that have an 1386 or I486 chip (or even a Pentium). They usuallyimplement main memory with a 32-bit or 64-bit organization. Here, according to the storageaddress, one of the now four or eight data bus bytes Is responsible for fetching or providing the8-bit data from or to the peripheral. An additional logic that decodes the two or three least-significant address bits from the DMA chip can easily carry out the transfer.

The three free channels of the new second DMA chip in the AT are already designed for serving16-bit peripherals. This can be, for example, a 16-bit controller for hard disk drives. Althoughthe 823 7A is only an 8-bit chip, it can carry out a 16-bit or even a 32-bit transfer betweenperipherals and main memory. How the DMA controller carries out this, at first glance impos-sible, job is described below.

The descriptions up to now have shown that the internal temporary 8-bit register of the 8237Adoesn't play any role in data transfer between peripherals and memory (It is only important formemory-memory transfers). The transfer target receives the data from the source directly viathe data bus. The only problem left Is that the 8237A address register provides byte addressesand no word addresses. But if the coupling of address bits AQ-A15 from the 8237A and the

542Chapter 21 16-bit AT Architecture 543

DMA address latch to the system address bus is shifted by 1, which corresponds to a multi-plication by a factor of 2, and address bit AO of the system bus is always set to 0, then the 8237Awill generate word addresses. This also applies to the 16-bit DMA channels in the AT. AO isalways equal to 0 here. The 8237A and the DMA address latch provide address bits A1-A16,and the DMA page register supplies address bits A17-A23. Therefore, one DMA page of the16-bit channels now has 128 kbytes instead of 64 kbytes and the data transfer is carried out in16-bit sections. Transferring the data bytes onto the low-order or high-order part of the data busaccording to an even or an odd address is unnecessary.

Only on systems with a 32-bit data bus do the words need to be transferred by an additional16/32-bit logic onto the low-order or high-order data bus word, according to whether theiraddresses represent double-word boundaries. This is carried out analogously to the transfer of8-bit quantities on the XT,

For a data transfer between memory and peripherals (the main job of DMA), it is insignificant,therefore, as to whether an 8- or 32-bit chip is present. The shifting of the address bits suppliedby the 8237A by one or two places leads to 16- or even 32-bit addresses. Unfortunately, thetransfer can then only start and end at word or double-word boundaries, and the transferredquantities are limited to multiples of 16 or 32 bits. If a peripheral supplies, for example, 513bytes, this may give rise to some difficulties. EISA therefore implements a 32-bit DMA controllerwhich also runs somewhat faster than 4.77 MHz.

lefresh

Channel 0 is dedicated to memory refresh. In modern ATs and other computers with intelligentDRAM controllers, the memory refresh need not be carried out by a DMA cycle; instead, theDRAM controller or even the DRAM chips themselves do this on receipt of a trigger signal fromthe PIT. The PIT defines the refresh time by means of the periodic square-wave signal. TheDMA chip Is used to generate the refresh address and the control signals for reading the mainmemory (if the memory controller or even the DRAM chips themselves are doing that). Modernmemory controllers handle these processes on their own. Channel 0 of the 8237A is no longerrequired for memory refresh. On such motherboards you would therefore be able to use channel0 together with channel 1 for a memory-memory transfer. However, the AT architecture thwartsyour plans again.

21.23 Memory-Memory Transfers

On each of the channels a page register is allocated, whose addresses are listed in Table 21.5.IBM, though, has Implemented a common page register for channels 0 and 1 in the PC/XT, asalready mentioned. Therefore, memory-memory transfer was only possible within a singleDMA page of 64 kbytes, as only channels 0 and 1 can carry out this transfer, and they have toshare one register on the PC/XT.

On the AT also, no memory-memory transfer is possible for the following reasons: DMA chan-nel 4, corresponding to the master's channel 0, is blocked by cascading from the slave DMA.

Port

87h83h81 h82h8fh8bh89h8ah

Page register

channelchannelchannelchannelchannelchannelchannelchannel

01234 (refi567

Table 215: I/O addresses of the AT page registers

Thus the master DMA chip Is not available for a memory-memory transfer. Only the slaveDMA remains, but here also the problems are nearly Insurmountable. On the AT and compatiblesthe memory refresh is no longer carried out by a DMA cycle, so channel 0 would then be freefor a memory-memory transfer.

But for the memory-memory transfer, the internal temporary register of the 8237A is alsoinvolved - and this Is only eight bits wide. Thus, 16-bit data on the 16-bit data bus cannot betemporarily stored; for this a 16-bit DMA chip would be required. If we restrict all memory-memory transfers to 8-bit transfers, then the data byte can be temporarily stored, but dependingupon an even or odd source address, the byte appears on the low- or high-order part of the databus. After temporary storage the data byte must be output by the 8237A, again depending onart even or odd target address onto the low- or high-order part of the data bus. This is possiblein principle by using a corresponding external logic, but Is quite complicated and expensive.Therefore, the AT and 1386/1486 motherboards generally don't implement •memory-memorytransfer. It could be worse, because the REP MOVS instruction moves data on an 80286 in 16-bit units and on an 1386/i486 even in 32-bit units very quickly. The much higher CPU clock rateadditionally enhances the effect. IBM has probably implemented the second DMA chip onlybecause some peripherals might request a 16-bit DMA channel for data transfer. Note that theXT carries out the transfer of sector data from or to the hard disk (originally a job of the DMA)via a DMA channel but the AT employs PIO for this. Only EISA and PS/2 still use DMA forthis job.

213 I/O Channel and Bus Slots

Similar to the PC/XT, here also a main part of the system bus leads into the bus slots. The ATbus slots incorporate 36 new contacts, compared to the XT bus slot, to Integrate the additionaladdress, data, DMA and IRQ lines. Thus, 98 contacts are present In total The additional ATcontacts are included In a separate section, which is always arranged Immediately behind theslot with the conventional XT contacts. Usually, each AT or AT-compatible has several pure XTand several pure AT slots with corresponding contacts. Also, it is' completely insignificant (intheory) into which slot you insert an adapter card in the AT. You only have to ensure that youreally do insert an AT adapter (discernible by the additional contacts on the bottom) into an ATslot and not into an XT slot. Figure 21.2 shows the structure and assignment of an AT bus slot.

544 Chapter 2116-bit AT Architecture 545

In the following sections only the new contacts and the meaning of the supplied or acceptedsignals are presented. The assignment of the XT part of an AT slot (with the exception of theOWS and REF contacts) is given in Section 203. OWS has been added instead of the reservedXT bus contact B8 to service fast peripherals without wait cycles. Because the AT bus andISA can support busmasters on external adapters up to a certain point, all connections arebidirectional To show the data and signal flow more precisely, I have assumed for the transferdirections indicated that the CPU (or another device on the motherboard) represents the currentbusmaster. Anyway, there are virtually no AT adapters with a busmaster device.

OWS (I; PC/XT slot)Terminal B8

The signal from a peripheral indicates that the unit is running quickly enough to be servicedwithout wait cycles.

DACKO, DACK5-DACK7 (O)Terminals D8, D10, D12, D14

These four DMA acknowledge contacts are used for the acknowledgement of the DMA requestsDRQO and DRQ5-DRQ7. Compared to the XT, DACKO has been replaced by REFR because thememory refresh is carried out via REFR in the AT.

DRQO, DRQ5-DRQ7 (I)Terminals D9, Dll, D13, D15

With these DMA request contacts a peripheral on an adapter card may tell the system on themotherboard that it wants to transfer data via a DMA channel. Channel 0 of the first DMA chipis designed for an 8-bit transfer, the three additional channels 5~7f on the other hand, for 16-bittransfers. Channel 4 is used for cascading the two DMA chips.

I/O CS16 (I)Terminal D2

The signal at this contact has a similar meaning to MEM CS16. I/OCS16 applies to I/O portsand not memory addresses.

IRQ10-IRQ12, IRQ14, IRQ15 CDTerminals D3-D7

These contacts transmit the hardware interrupt requests according to the channels IRQ10-IRQ12and IRQ14, IRQ15 to the slave PIC on the motherboard. IRQ13 in the AT is reserved for the80287 coprocessor, which is located on the motherboard. Therefore, this signal doesn't lead intothe bus slots.

Figure 212: The AT bus slot comprises a separate section with 38 new contacts for the extension up to 16 bits.

(O)Terminals C2-C8

The large address contacts supply the seven high-order bits of the CPU address bus. Comparedto the normal address contacts A0-A19 of the conventional XT bus, the signals at these contacts

546 Chapter 21 16-bit AT Architecture 547

are valid much earlier, and may be decoded half a bus clock cycle in advance of the address bitsA0-A19. Note that LA17-LA19 and A17-A19 overlap in their meaning. This is necessary be-cause the signals on A17-A19 are latched and therefore delayed. But for a return of the signalsMEM CS16 and I/O CS16 in time, it is required that address signals A17-A19 are also availablevery early.

MASTER (I)Terminal D17

The signal at this contact serves for bus arbitration. Thus, busmasters on adapter cards have theopportunity to control the system bus. For this purpose they must activate MASTER (that is,supply a low level signal). In the AT the integration of a busmaster is carried out by an assignedDMA channel. Via this channel the busmaster outputs a DRQx signal. The DMA chip cuts theCPU off the bus using HRQ and HLDA, and activates the DACKx assigned to the busmaster.The busmaster responds with an active MASTER signal and thus takes over control of the bus.

MEM CS16 (I)Terminal Dl

A peripheral adapter card must return a valid MEM CS16 signal in time if it wants to be ser-viced with a data bus width of 16 bits. Using MEMCS16, therefore, 8-bit and 16-bit adaptersmay be inserted into an AT slot without any problem. The AT bus logic recognizes whether theadapter must be accessed with 8- or 16-bits.

Terminal C9

An active memory read signal MEMR (that is, a low level) signal indicates that the processoror DMA controller wants to read data from memory with an address between OM and 16M. Onthe other hand, the SMEMR signal in the XT slot only applies to the address space between OMand 1M. With an address below 1M, MEMR is inactive (that is, high).

MEMW (O)Terminal CIO

An active memory write signal MEMW (that is, a low level signal) indicates that the processoror DMA controller wants to write data into memory with an address between OM and 16M. Onthe other hand, the SMEMW signal in the XT slot only applies to the address space between OMand 1M. With an address below 1M, MEMW is inactive (that is, high).

REF (O; PC/XT slot)Terminal B19

The refresh signal at this contact indicates that the memory refresh on the motherboard is inprogress. Thus, peripherals may also carry out a memory refresh simultaneously with themotherboard.

SBHE(O)Terminal Cl

If data is output onto or read from the high-byte SD8-SD15 of the data bus by the CPU oranother chip, then the system bus high enable signal SBHE is active and has a low level

SD8-SD15 (I/O)Terminal C11-C18

These eight system data contacts form the high-order byte of the 16-bit address bus in the AT.

SMEMR (O; PC/XT slot)Terminal B12

An active S-mernory read signal SMEMR (that is, low level) signal indicates that the processoror DMA controller wants to read data from memory with an address between OM and 1M. Onthe other hand, the MEMR signal in the AT extension applies to the address space between OMand 16M. With an address above 1M, SMEMR is inactive (that is, high).

SMEMW CO; PC/XT slot)Terminal Bll

An active memory write signal MEMW (that is, a low level signal) indicates that the processoror DMA controller wants to write data into memory with an address between OM and 1M. Onthe other hand, the MEMW signal in the AT extension only applies to the address space be-tween OM and 1M. With an address above 1M, SMEMW is inactive (that is, high),

214 AT Bus Frequencies and the ISA Bys

The concept and architecture of the AT have been very successful during the past few years.This makes it worse that no strictly defined standard for the bus system has actually existed.That became especially clear as the clock frequencies were increased more and more, and there-fore problems with the signal timing became heavier. IBM never specified the AT bus in a clearand unambiguous way. All standards in this field are therefore rather woolly. For IBM that wasnot very serious, because Big Blue went over to the PS/2 series before its AT products exceededthe 8 MHz barrier. It was only after this barrier was broken that users of AT compatibles hadto deal with bus problems. I have already mentioned that the bus slots run at 8.33 MHz at most,even in a 25 MHz AT. Before the AT manufacturers agreed to this strict definition, every manu-facturer chose their own standard - not very pleasant for AT users. The consequence was thatin many older turbo-ATs the bus as well as the CPU ran at 10 MHz or even 12.5 MHz. Suchfrequencies are only handled by a very few adapter cards. They cannot follow the clock, espe-cially if the chips get warm after a certain time. A warmer chip usually has a lower operatingspeed, even if only by a few nanoseconds. This is enough, though, and the computer crashes.Things get even more confusing if we remember that the 8237A DMA chips and the 8259A PICsr^n at 5 MHz at most. Even the faster types only reach 8 MHz. Moreover, the timer chip isoperated at 1.193 180 MHz, namely lk of the PC/XT base clock of 4.77 MHz, even in a 50 MHz

548 Chapter 21

i486 PC. That some misalignments and therefore unnecessary wait cycles occur with a CPUclock of 25 MHz, a bus frequency of 10 MHz, a DMA frequency of 5 MHz and a timer frequencyof 1.19 MHz seems to be obvious.

Seven years after presenting the AT the computer industry has become reconciled to a clearer,but unfortunately not very strict, standard for the AT bus. The result now is the ISA bus whichis about 99% compatible with the AT bus in the original IBM AT. ISA is the abbreviation forIndustrial Standard Architecture. Thus, ISA will really define an obligatory bus standard for all ATmanufacturers.

This standard specifies that the bus slots should run at 8.33 MHz at most. If a 33 MHz 1386wants to access the video RAM, it must insert a lot of wait states. A reading bus cycle, forexample, needs two bus cycles, but one bus clock cycle lasts four CPU clock cycles so that eightCPU clock cycles are necessary. If the memory on the graphics adapter has an (optimistic) accesstime of 60 ns, about four wait cycles are additionally necessary (the cycle time of a 60 ns DRAMlasts for about 120 ns, and the cycle time of the CPU clock is 30 ns; this leads to four wait cycles).If the two CPU cycles are subtracted, which a memory access always needs, then even with theoptimum cooperation of a graphics adapter and a bus, nine (!) wait states are necessary. Drivers,buffers etc. connected in between and misalignments may readily increase this value up to 15wait cycles. The transfer rate with an ISA bus width of 16 bits is decreased to 4 Mbytes/scompared to a memory transfer rate of 66 Mbytes/s. A Windows window of 640 * 512 pixelswith 256 colours is filled within 100 ms; a time period which is clearly recognized by the eye.No wonder that even 33 MHz i486 ATs do not always operate brilliantly with Windows. The- enormous number of wait cycles during reads and writes from and to video RAM slows downthe high-performance microprocessor. Whether the CPU needs some additional cycles for cal-culating a straight line is thus of secondary Importance. Only special motherboards and graph-ics adapters where the video memory Is (more or less) directly connected to the memory busor a fast local bus, and not accessed Indirectly via the ISA bus, may solve this problem.

The bus frequency Is generated by dividing the CPU clock, thus the ISA bus largely runssynchronously to the CPU. This Is different, for example, from the microchannel, which uses itsown clock generator for the bus so that the microchannel runs asynchronously to the CPU. TheISA bus also operates asynchronous cycles, for example if a DMA chip that runs at 5 MHzInitiates a bus cycle. The big disadvantage of synchronous ISA cycles Is that a whole clock cycleIs lost as soon as an adapter becomes too slow even for only a few nanoseconds. Therefore, EISAenables the stretching of such cycles to avoid unnecessary wait states. Actually, a bus is muchmore than a slot on a motherboard.

Besides the layout of the bus slots and the signal levels, the ISA standard also defines the timeperiod for the rise and fall of the address, data and control signals. But these properties are onlyImportant for developers of motherboards and adapter cards, therefore a vast number of signaldiagrams and exact definitions are not given here. Signal freaks should consult the original ISAspecification.

The introduction of the 1386 and I486 32-bit microprocessors with full 32-bit data bus and 32-bit address bus also required an extension of the ISA bus. This bus was Implemented for the80286, with its 16-bit address bus and 16 Mbyte address space only. Not only is the small widthof the bus system outdated today, but so are the antiquated 8-bit 8237A DMA chips, with theirlimitation to 64 kbyte blocks, and the rather user-unfriendly adapter configuration • (usingjumpers and DIP switches). Another serious contradiction between the very powerful 32-bitprocessors and the «tired» 8-bit AT concept is the lack of supporting busmasters on externaladapter cards.

Two completely different solutions for these problems are established today: IBM's microchannelfor PS/2, and EISA, which has been developed by a group of leading manufactures of IBM-compatible PCs. IBM has gone down a completely different road with Its micr©channel, notonly because of the new geometric layout of the bus slots, but also with the architectureimplemented. Moreover, IBM has denied the microchannel to other manufacturers by meansof patents and other protective rights. This is a consequence of the fact that these other clonemanufacturers had previously got a large part of the PC market. As IBM is rather miserly withissuing licences, the microchannel is no longer the completely open architecture that users andmanufacturers haveifbeen accustomed to with the PC/XT/AT. Together with the significantlylarger functionality of the microchannel, one may speak of a radical reorganization or Indeedview of the microchannel as a revolutionary step towards real 32-bit systems.EISA, on the other hand, tries to take a route that might be called «evolutionary». The maximof EISA is the possibility of Integrating ISA components Into the EISA system without anyproblems. This requires an Identical geometry for the adapter cards and, therefore, unfortun-ately also the integration of obsolete concepts for the EISA's ISA part. With this concept, 16-bitISA components can be integrated In an EISA system with no problems, but you don't then haveany advantage. Under these conditions the EISA bus operates more or less Identically to theconventional ISA bus. Only 16- and 32-bit EISA components really take advantage of the EISAbus system, using, for example, burst cycles or 32-bit DMA. The EISA bus is capable of a datatransfer rate of.up to 33 Mbytes/s, compared to 8.33 Mbytes/s with an ISA bus.

In view of the technical structure, EISA is more complicated than the microchannel because itnot only needs to carry out EISA bus cycles, but for compatibility reasons also ISA cycles. Thisapplies, for example, to DMA, where the EISA system must decide whether an 8237A-compatlble DMA cycle (with its known disadvantages) or a full 32-bit EISA DMA cycle has tobe executed. The hardware must be able to carry out both, and thus is, of course, rathercomplicated. In this aspect, the microchannel has an easier life; it frees itself from the outdatedPC/XT/AT concepts, and starts from a new beginning. This restriction to a new beginningmakes the microchannel less complicated. However, stronger competition In the field of EISAhas surely led to cheaper EISA chips, even though their technology is more complex. Additionally,as the user you have the advantage that older ISA components may also be used initially. Lateryou can integrate more powerful EISA peripherals. In view of the speedy development, though,who Is going to use Ms old hard disk controller or 8-bit.graphics adapter with 128kbytes ofmemory when buying a computer of the latest generation?

549