Iteration Technique toward SOC

EDA Lab, Department of Computer Science and Technology, Tsinghua University

2005.8

Outline

Part One Simulation vs. Iteration Problem Size in the Future Future Trend of Simulation

Part Two P/G Simulation More Accurate Model Numerical Character Accelerate Convergency Speed Universal Formulation

Simulation vs. Iteration

Linear System Large Scale Differential Equations Topology of Differential Variable Numerical method need Iteration

Non-Linear System Successful Commercial Simulator

Spice/HSpice/PSpice ADS （ Agilent Design System）

Problem Size in the Future

More Than Two Billion Transistors More Metal Layers Complicated Interconnect Techniques Local Simulation Size is equal to today’s

Global Simulation Size

Future Trend of Simulation

More Accurate Simulation Model More Efficient Local Simulator

Utilize the Geometry Similarity Accelearte Iteration Convergency Speed Reuse of Iteration Result Model Reduction in Analytical Form

Parallel Global Simulation SMP Cluster

P/G Simulation

Different Topology Physical Factors to be Considered Static and Dynamic Simulation Technique Design and Optimization Technique

More Accurate Model

Consider Package

One Bump on Power Rail

One Bumpon Gnd Rail

Power Pin on Package

Gnd Pin on Package

topL topR

botL viaL viaRbotR

botL viaL viaRbotR

topL topR

pkgCcpkgR

cpkgL

More Accurate Model

Consider Vias

Horizontal Layer

Vertical Layer

Neglect Via

Horizontal Layer

Vertical Layer

1.1 1.2 1.3 1.4 1.5

2.x 2.y 2.z

layer 1 nodes in the same metal wires

layer 2 nodes in different metal wires

Numerical Character

Matrix Stamp Order

node a g g g

g g

node b

row a

row b

col a col b

Numerical Character

Matrix Shape

Side Block

Diag Block

Power Grid

Gnd Grid

One Layer

Numerical Character

Poorer Eigenvalue

Numerical Character

Iteration Times Comparision

ILU Iteration Times ICD Iteration Times

residual Matrix I Matrix II residual Matrix I Matrix II

1e-3 165 5 1e-3 166 5

1e-6 258 8 1e-6 258 8

1e-10 377 11 1e-10 375 11

Accelerate Convergency Speed

Balance Technique

Side Block

Diag Block

Power Grid

Gnd Grid

One Layer

Accelerate Convergency Speed

Result

Node

Num

Avg

Iter

times

CPU

time

(sec.)

Mem

Usage

(MB)

Speed

Up

Ratio

Node

Num

Avg

Iter

times

CPU

time

(sec.)

Mem

usage

(MB)

5.5K 15 0.53 65 3.18 5.5K 208 1.69 59

23K 19 1.13 78 9.20 22K 293 10.4 70

130K 30 5.37 148 13.01 100K 456 70.2 136

450K 40 21.2 366 19.79 450K 710 419.6 349

Universal Formulation

Famouse NA Formulation in P/G Simulation Universal MNA Formualtion in General

Simulation Gap Here is Numerical Problem Improve Preconditioner to Break the Gap

Universal Formulation

Simple Preconditioner Fit MNA

More Efficient One

'

0

T TA B A BG G

B B kI

11

21 22

0lL

l l

11 21

220

T T

T

l lU

l

21 11Tl B l

21 21 22 22T Tl l l l

Conclusion

Pay more attention to topolgy and geometry Trying to find out analytical result instead of

using iteration When considering an algorithm, think about

whether it is easy to be implement in parallel form

Construct as many reusable data as possible

That’s All

Thank you！