What is an Interrupt?

• It means interrupting the normal execution of the microprocessor.

Steps whenever there is an interrupt?

current

PC PC contents are stored in stack

100

101

102

103

104

103

103

STACK

SP

4

Interrupts in 8085

Main routine

Interrupt

Save program counter

Disable interrupts

Send out interupt acknowledge

Service routine

Go to service routine

Get original program counter

Go back

EI

RET

HARDWARE INTERRUPT

• It is a special signal from an I/O device to the computer.

SOFTWARE INTERRUPT

• It is generated by a program interrupt instructions in the CPU.

TYPES OF INTERRUPTS

• MASKABLE & NON- MASKABLE INTERRUPTS

• VECTORED & NON-VECTORED INTERRUPTS

• EDGE TRIGGERED & LEVEL TRIGGERED INTERRUPTS

• PRIORITY BASED INTERRUPTS

MASKABLE INTERRUPTS

EXAMPLE:

• RST 7.5

• RST 6.5

• RST 5.5

• INTR

• ONLY TRAP IS A NON MASKABLE INTERRUPT

VECTORED INTERRUPTS

EXAMPLE:

• RST 7.5

• RST 6.5

• RST 5.5

• TRAP

8085 Interrupts

8085

TRAP

RST7.5

RST6.5

RST 5.5

INTR

INTA

The addresses to which program control goes:

NAME VECTOR

ADDRESSES

RST 7.5 003CH(7.5 X 0008H)

RST 6.5 0034H(6.5 X 0008H)

RST 5.5 002CH(5.5 X 0008H)

TRAP 0024H(4.5 X 0008H)

Absolute address is calculated by multiplying the RST value with 0008H.

NON – VECTORED INTERRUPT

EXAMPLE:

• INTR is a non vectored interrupt.

The 8085 Interrupts

Interrupt name

Maskable Vectored

INTR Yes No

RST 5.5 Yes Yes

RST 6.5 Yes Yes

RST 7.5 Yes Yes

TRAP No Yes

EDGE TRIGGERED INTERRUPTSEXAMPLE:

• RST 7.5

Edge triggering

Rising edge

Falling edge

LEVEL TRIGGERED INTERRUPTEXAMPLE:

• RST 6.5

• RST 5.5

• INTR

• TRAP is EDGE & LEVEL triggered interrupt.

Level triggering

Low level

High level

PRIORITY BASED INTERRUPTS

INTERRUPT PRIORITY

TRAP 1

RST 7.5 2

RST 6.5 3

RST 5.5 4

INTR 5

Five hardware interrupts are:• TRAP

• RST 7.5

• RST 6.5

• RST 5.5

• INTR

TRAP (PIN-6)

• Non- maskable

• Has highest priority

• Can not disable.

• Edge & level triggered

• Used for power failure & emergency shut off.

RST 7.5

• Maskable interrupt.

• Has 2nd highest priority.

• +ve edge triggered only.

RST 6.5

• Maskable interrupt.

• 3rd highest priority.

• Level triggered only.

RST 5.5

• Maskable interrupt.

• 4th highest priority.

• Level triggered only.

INTR

• Maskable interrupt.

• Lowest priority.

• Level triggered.

INTA’

• Stands for Interrupt acknowledge.

• Outgoing signal.

• Active low signal.