ITRSITRSYield EnhancementYield Enhancement

By By

Sai N. LwinSai N. Lwin

What is [Process] Yield?What is [Process] Yield?

The fraction (or percentage) of acceptable The fraction (or percentage) of acceptable parts among all parts that are fabricated.parts among all parts that are fabricated.

For example, the average number of good chips For example, the average number of good chips produced per wafer is called produced per wafer is called wafer yieldwafer yield..

Y = (1 + Ad/Y = (1 + Ad/αα))--αα

A = area of the chipA = area of the chipd = defect densityd = defect densityαα = clustering parameter= clustering parameter

Improving the Process YieldImproving the Process Yield

Diagnosis and RepairDiagnosis and RepairFirst allow the process to make errors First allow the process to make errors Then diagnose the cause of errors and repairThen diagnose the cause of errors and repairYield is improved but cost is also increasedYield is improved but cost is also increased

Process Diagnosis and CorrectionProcess Diagnosis and CorrectionTrace the specific causes (defective material, faulty Trace the specific causes (defective material, faulty machines, incorrect human procedures, etc) of the machines, incorrect human procedures, etc) of the failed parts failed parts Eliminate the causeEliminate the causeThis method is preferredThis method is preferred

What is Yield Enhancement (YE)?What is Yield Enhancement (YE)?

““The process of improving the baseline yield of The process of improving the baseline yield of a given technology node from R&D (Research a given technology node from R&D (Research and Development) yield level to mature yield.and Development) yield level to mature yield.””Four focus topics:Four focus topics:

1)1) Yield Model and Defect BudgetYield Model and Defect Budget2)2) Defect Detection and CharacterizationDefect Detection and Characterization3)3) Yield LearningYield Learning4)4) Wafer Environment(s) Contamination ControlWafer Environment(s) Contamination Control

1) Yield Model and Defect Budget1) Yield Model and Defect Budget

Y = YY = YSS * Y* YRR = Y= YSS * (1+A* (1+ADD00//αα))--αα , where, whereYYSS = systematic (gross) limited yield = systematic (gross) limited yield YYTT = random= random--defect limited yielddefect limited yieldA = area of the deviceA = area of the deviceDD00 = fault density (the average number of = fault density (the average number of faults per unit area)faults per unit area)αα == clustering parameterclustering parameter

Yield Model and Defect Budget Yield Model and Defect Budget ContinuedContinued……

Defect Target CalculatorDefect Target CalculatorAllow users to enter key technology Allow users to enter key technology parameters and estimate a defect target for a parameters and estimate a defect target for a specific chipspecific chip

2) Defect Detection and Characterization2) Defect Detection and Characterization

Primary Requirement Primary Requirement –– ability to detect ability to detect inlineinline--yield limiting defects on specific yield limiting defects on specific process layersprocess layers

Unpatterned wafer inspectionUnpatterned wafer inspectionPatterned wafer inspectionPatterned wafer inspectionHigh Aspect Ratio Inspection (HARI)High Aspect Ratio Inspection (HARI)

Needs high resolution microscopesNeeds high resolution microscopesScanning Electron Microscopy (SEM)Scanning Electron Microscopy (SEM)

3) Yield Learning3) Yield Learning

The collection and application of process and wafer knowledge to improve device yield through the identification and resolution of systematic and random manufacturing events.Ytotal_i = (Yline) * (Ybatch_i)Ybatch_i = (Ysys_i) * (Yrandom_i)

4)4) Wafer Environment(s) Wafer Environment(s) Contamination ControlContamination Control

Wafer environment controlAirborne Molecular ContaminationProcess critical materialsUltrapure WaterGases and Liquid ChemicalsNovel materialsDesign-to-process interactionsProcess-to-process interactions

Difficult ChallengesDifficult Challenges>= 45 >= 45 nmnm/Through 2010/Through 2010

Need for highNeed for high--speed and costspeed and cost--effective effective high aspect ratio inspection toolshigh aspect ratio inspection toolsAchieve testable and diagnosable designs Achieve testable and diagnosable designs for Integrated Circuits (IC)for Integrated Circuits (IC)Data management and test structures for Data management and test structures for rapid yield learningrapid yield learningDetection of everDetection of ever--shrinking yield critical shrinking yield critical defectsdefects

Difficult ChallengesDifficult Challenges< 45 < 45 nmnm/Beyond 2010/Beyond 2010

Correlation of Impurity level to yieldCorrelation of Impurity level to yieldDevelopment of parametric sensitive yield Development of parametric sensitive yield models including new materials and considering models including new materials and considering the high complexity of integrationthe high complexity of integrationNeed for fast and short yield learning cycles at Need for fast and short yield learning cycles at simultaneously increasing process complexitysimultaneously increasing process complexityDetection and simultaneous differentiation of Detection and simultaneous differentiation of multiple killer defect types is necessary at high multiple killer defect types is necessary at high capture rates and throughputcapture rates and throughput

CreditsCredits

International Technology Roadmap for International Technology Roadmap for Semiconductors (ITRS)Semiconductors (ITRS)Bushnell, Michael L. & Agrawal, Vishwani Bushnell, Michael L. & Agrawal, Vishwani D., D., ““Test Economics and Product Quality,Test Economics and Product Quality,””Essential of Electronic Testing,Essential of Electronic Testing, pp. 44pp. 44--50, 50, 2004.2004.