iv. diodes - advanced energy technology...

IV. Diodes

We start our study of nonlinear circuit elements. These elements (diodes and transistors) are

made of semiconductors. A brief description of how semiconductor devices work is first given

to understand their i − v characteristics. You will see a rigorous analysis of semiconductors

in the breadth courses.

4.1 Energy Bands in Solids

In every atom, the nucleus (positively charged) is surrounded by a cloud of electrons. Initially

scientists envisioned the atomic structure to be similar to the solar system: the nucleus in

the center (similar to the sun), electrons revolving on orbits around the nucleus (similar to

planets), and the electric attraction force between the nucleus and electrons being similar

to the gravitational force between the sun and planets. However, according to Maxwell’s

equations, electrons that revolve around a nucleus should emit electromagnetic radiation. As

such, the electrons should lose energy gradually and their orbit should decay (in a fraction

of a second!). This means that there is a mechanism that would not allow the electrons to

lose energy gradually and is one of main reasons that the quantum theory was developed.

According to quantum theory, electrons revolving around an atom can have only discrete

levels of energy as is shown below. Electrons are not allowed to gradually lose or gain

energy. They can only “jump” from one level to another (by absorbing or emitting a quanta

of energy, usually a photon). Furthermore, there are only a finite number of electrons that

are allowed in each state (Pauli’s Principle). Therefore, both the energy levels for electrons

and the number of electrons at each energy level are specified. Because any system would

tend to be in a minimum energy state, electrons in an atom start by “filing” the lowest

energy level. Once all allowable slots is filled, electrons start filling the next energy level and

so on. Therefore, the electronic structure include “filled” energy levels (all slots are taken

by electrons), “empty” energy levels (positions are available but no electron is present), and

“partially filled” levels (there are some electrons but there is also room for more electrons).

Isolated Atoms A Solid

ECE65 Lecture Notes (F. Najmabadi), Spring 2006 76

When atoms are arranged in a solid, the inter-spacing between atoms can become comparable

to the size of electron orbitals of each atom (electrons at each energy level are confined to a

region in space called the orbital and the higher energy levels have larger orbital sizes). In

this case, the outer orbitals merged into energy bands. Electrons in these bands are not tied

to an atom, rather they are free to move around the solid (if space is available per Pauli’s

Principle). In addition, instead of discrete energy levels, these “shared” electrons can have

continuous values of energy within a “band” of energy. As before, there are range of energies

that no electron can occupy. These range of energies are called “Forbidden Gaps.” (see the

figure above).

The electric properties of metals, semiconductors, and insulators are can be understood with

this picture. As these properties are tied to energy bands and forbidden gaps, we only focus

on these regions as are shown in the figure below.

Forbidden Gap

Partially Filled Band

Forbidden Gap

Empty Energy Band

Filled Energy Band

Metals

Forbidden Gap

Empty Energy Band

Filled Energy Band

Semiconductors

In metals, one of the energy bands is only partially filled. Obvi-

ously, all energy bands below (i.e., with lower energies) are com-

pletely filled and all energy bands above are completely empty.

Electrons in the partially filled band can easily move around the

solid with smallest amount of energy as there are lots of spaces

available. As such, metals can conduct electricity (and heat)

very well.

In a semiconductor, no partially filled band exists. In the filled

energy band, there are a lot of electrons, but there are no avail-

able slot to move into. In the empty band, there are a lot of slots

but no electrons. One would expect that semiconductors to be

perfect insulators (for both electricity and heat). However, the

size of the forbidden gap in a semiconductor is small. At room

temperature, the thermal energy in the material is sufficient to

provide sufficient energy to a select number of electrons to move

from the filled energy band into the empty energy band.

These electrons that are promoted to the empty energy band now can carry electricity and

heat because there are a lot of slots available in this band. In addition, these electrons leave

spaces (or “holes”) in the originally filled energy band. As such, electrons in the originally

filled energy band can also move around the solid by moving from one hole to another hole

and participate in the conduction of electricity. Obviously it is easier to keep track of the

small number of holes in the filled energy band as opposed to the large number of electrons

in that band (it is much easier to find the attendance in a almost full class room by counting

the number of empty seats rather the number of students!). In this picture, when electrons

move for example to the left to fill a hole, it would look like the hole is moving to the

right direction. So, in describing semiconductors we usually keep track of negatively charged


electrons (those that are promoted to the empty energy band) and positively charged holes

(spaces left behind).

Since at room temperature the number of electrons that are promoted into the energy band

(∼ 1016 to 1019) is much smaller than number of electrons in the partially filled band of a

metal (∼ 1028 to 1029), semiconductor conduct electricity but have a much lower conductivity

(thus, the name semiconductor). Overall, the properties of semiconductors are very sensitive

to temperature as the number of electrons than can “jump” over the Forbidden gap increases

exponentially. This is an important effect and should be taken into account in the design of

electronic circuits.

Lastly, insulator have a similar energy band structure as semiconductors (no partially filled

band) with one exception. The size of the forbidden gap in an insulator is several time larger

than that of a semiconductor. As such, the number of electrons that can be promoted to the

energy band is very small (∼ 107 at room temperature). So, these material are very poor

conductors.

4.2 Semiconductor Devices

Semiconductor material are mainly made of elements from group IVB of the periodic table

like C (diamond), Si, Ge, SiC. These material have 4 electrons in their outer most electronic

shell. Each atom can form a “covalent” bond with four of its neighbors sharing one electron

with that atom. In this manner, each atom “sees” eight electrons in its outer most electronic

shell (4 of its own, and one from each neighbor), completely filling that shell. It is also

possible to form this type of covalent bond by combining elements from group IIIB (sharing

three electrons) with element from group VB (sharing five electrons). Examples of these

semiconductors are GaAs or AlGaAs and are usually called “3-5” semiconductors. We focus

mostly on Si semiconductors in this class. Figure below shows this covalent bond structure

for Si. A pair of electrons and holes are slow shown. Note that Si form a tetrahedron

structure and an atom in the center of the tetrahedron share electrons with atoms on the

each vertex. Figure below is a two-dimensional representation of such a structure. The left

figure is for a pure Si semiconductor and an electron-hole pair is depicted. Both electrons

and holes are called “mobile” carriers as they are responsible for carrying electric current.

If we add a small amount of an element from group VB, such as P, to the semiconductor, we

create a n-type semiconductor and the impurity dopant is called a n-type dopant. Each of

these new atoms also form a covalent bond with four of its neighbors. However, as a n-type

dopant has 5 valance electron, the extra electron will be located in the “empty” energy band.

As can be seen, there is no hole associated with this electron. In addition to electrons from

the n-type dopant, there are electron-hair pair in the solid from the base semiconductor (Si in


the above figure) which are generated due to temperature effects. In a n-type semiconductor,

the number of free electrons from the dopant is much larger than the number of electrons from

electron-hole pairs. As such, a n-type semiconductor is considerably more conductive than

the base semiconductor (in this respect, a n-type semiconductor is more like a “resistive”

metal than a semiconductor).

SiSi

Si

SiSi

Si

Si

Si

Si

ElectronHole

SiSi

SiSi

Si

Si

Si

Si

P

Electron

SiSi

SiSi

Si

Si

Si

Si

B

Hole

Pure Semiconductor n-type semiconductor p-type semiconductor

In summary, in a n-type semiconductor there are two charge carriers: “holes” from the base

semiconductor (called the “minority” carriers) and electrons from both the n-type dopant

and electron-hole pairs (called the “majority” carrier).

Similarly, we can create a p-type semiconductor by adding an element from group IIIB, such

as B, to the semiconductor. In this case, the p-type dopant generate holes. We will have two

charge carriers: majority carriers are “holes” from the p-type dopant and electron-hole pairs

and minority carriers are electrons from the base semiconductor (from electron-hole pairs).

The charge carriers (electrons and holes) move in a semiconductor through two mechanisms:

First, charge carriers would move from regions of higher concentration to lower concentration

in order to achieve a uniform distribution throughout the semiconductor. This process

is called “diffusion” and is characterized by the diffusion coefficient, D. Second, charge

carriers move under the influence of an electric field. This motion is called the drift and is

characterized by the mobility, µ. The ratio of D and µ is independent of the dopant or the

base semiconductor material and is given by Einstein’s Equation

D

µ=

kT

q'

T

11, 600≈ VT

where k is the Boltzmann’s constant, T is temperature in Kelvin, and q is the electron

charge. Parameter VT is called the “volt-equivalent of temperature” and appears in most

semiconductor formulas. At room temperature, VT ≈ 0.026 V.


4.3 The Junction Diode −+v

iD

D

The simplest semiconductor device is a pn-

junction diode as is shown in the figure with p-

type material on the left and n-type material on

the right and metal contacts are attached to both

sides. Circuit symbol for the device is also shown

with the “inward” arrow depicting the p-type ma-

terial side. The convention for the direction of the

diode current and the voltage across the diode are

also shown.

We see that in the n-type material side, there is

a large concentration of free electrons. As such,

these electrons would like to diffuse to the p-side

where there are few electrons. Similarly there is a

large concentration of holes in the p-type material

and they would like to diffuse to the n-type ma-

terial side. When these electrons and holes meet

in the vicinity of the junction, they combine and

are neutralized. Since this region is “depleted”

of mobile carriers, it is called the “depletion” re-

gion (also referred to as the “transition” or “space-

charge” region). The width of this region is small,

typically ∼ 0.5µm.

Since the n-type material has lost electrons, it becomes positively charged. Similarly the p-

type material becomes negatively charged. As a result, an electric potential and an electric

field appears across the depletion region. This electric field (or the voltage barrier) impedes

the flow of electrons from the n-type material and flow of holes from the p-type material.

The height of this voltage barriers is related to the forbidden gap of the base semiconductor

material (and not the amount of dopant).

i − v Characteristics

Let us attach a voltage source to this junction diode such that the positive terminal of the

voltage source is attached to the n-type material. This configuration is called reverse bias.

In this case, some of the free electrons from the n-type material will travel to the voltage

sources making the n-type material side more positively charged. Similarly, some of the

holes from the p-type material would go the voltage source, making the p-type material

more negatively charged. As a result, the depletion region becomes wider and the height of

the potential barrier increases and no majority carriers can cross the depletion region.


−+v

iD

D− +

Reverse Bias

−+v

iD

D

−+

Forward Bias

A small current however, flows in the circuit because of the minority

carriers. On the n-type material side, electron-hole pair are created

due to thermal energy. Electrons move to the voltage source and holes

move to the depletion region. Similarly, on the p-type material side,

electron-hole pairs are created, holes are neutralized by electrons from

the voltage source and electrons move to the depletion region. These

electrons from the p-type material and holes from the n-type material

(minority carriers) combine in the depletion region leading to the flow

of a net current which is called the reverse saturation current, IS. In

the circuit above, iD = −IS. IS is very small: at room temperature it is

about several nA (10−9A) for Si semiconductors. Value of IS strongly

depends on the temperature (as it is related to the electron-hole pro-

duction rate) – IS doubles for every increase of ∼ 7C in temperature.

Now, let us attach the voltage source to the diode such that the positive

terminal is attached to the p-type material. This configuration is called

forward bias.

Electrons are injected into the p-type material making that region less positively charged

while electrons are taken from the n-type material making it less negatively charged. As a

result, the depletion region become thiner and the height of the potential barrier decreases.

In this case the diffusion process can gradually overcome the force of the electric field and

some of majority carriers can cross the junction and a positive current flows through the

diode. As the voltage source voltage is increased, the potential barrier height become smaller

leading to larger and larger currents (diode current increases exponentially with the applied

voltage).

The i − v characteristics of a junction diode is given by:

iD = Is

(

evD/ηVT − 1)

where the constant η is called the “emission coefficient” (η = 2 for Si and ηVT = 0.052 V).

Figure below (left) shows the plot of iD versus vD for a typical Si diode. Note that be-

cause IS is very small (nA range), vD should become large enough such that large value

of exp(vD/0.052) compensate for the small value of IS. As can be seen, the diode current

sharply rises when vD is in the range of 0.6 to 0.7 V. If we zoom near the origin and expand

the current scale to nA range (figure to the right), we can see the behavior of the diode in

the reverse-bias region.


-1

0

1

2

3

4

5

6

7

8

-1 -0.5 0 0.5 1

VD (V)

ID (mA)

-20

-10

0

10

20

30

40

50

60

70

-0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15

VD (V)

ID (nA)

Diode Limitations: In the forward bias region, the power P = iDvD is dissipated in the

diode in the form of heat. The diode packaging provides for the conduction of this heat to

the outside and diode is cooled by the air. If we increase vD (or iD) diode is heated more.

At some point, the generated heat is more than capability of the diode package to conduct it

away and diode temperature rises dramatically and diode burns out. As vD changes slowly,

this point is usually characterized by the current iD,max, maximum forward current, and is

specified by the manufacturer.

Heat generation is not a problem in the revers bias as iD ' 0 (and, thus, P ' 0). However,

if we increase the reverse bias voltage, at some voltage, a large current can flow through the

diode. This voltage is called the reverse breakdown voltage or the Zener voltage.

This large reverse current is produced through two processes. First, in the reverse bias,

minority carriers enter the depletion region. These minority carriers are accelerated by the

voltage across the depletion region. If the reverse bias voltage is high enough, these minority

carrier can accelerate to a sufficiently high energy, impact an atom, and disrupt a covalent

band, thereby generating new electron-hole pairs. The new electron-hole pairs can accelerate,

impact other atoms and generate new electron-hair pairs. In this manner, the number of

minority carriers increases exponentially (an avalanches process), leading to a large reverse

current. This is called the avalanche breakdown. Second, when the strength of the electric

field across the junction becomes too large, electrons can be pulled out of the covalent bonds

directly, generating a large number of electron-hole pairs and a large reverse current. This

is known as the Zener effect or Zener breakdown.

Regular diodes are usually destroyed when operated in the Zener or reverse breakdown

region. These diode should be operated such that vD > −vZ . A special type of diodes,

Zener diodes, are manufactured specifically to operate in the Zener region. We will discuss

these diodes later. In Zener diodes, heat generation sets a maximum for the allowable diode

current in the Zener region.


4.4 Solving Diode Circuits

iD vDRest ofCircuit

−+

iD vD

−+

−+V

R

T

T

With diode i−v characteristic in hand, we now attempt to solve

diode circuits. Consider any linear circuit with a diode. The box

labeled “the rest of the circuit” in the figure can be replaced by

its Thevenin equivalent, giving the simple diode circuit below.

Because the three elements are in series, current iD flows through

all elements. Writing KVL around the loop we have:

VT = iDRT + vD

This is an equation with two unknowns (iD and vD) as VT and RT

are known. The second needed equation (to get two equations

in the two unknown) is the diode characteristic equation:

iD = Is

(

evD/ηVT − 1)

The above two equations in two unknown cannot be solved analytically as the diode i − v

equation is non-linear. PSpice solves these equations numerically. As analytical solutions

can provide insight in the circuit behavior and may be also needed for circuit design, we

develop two methods to solve diode circuits without numerical analysis.

Load Line

The i − v characteristic of the diode is plotted in the figure. The iD and vD values of any

point on the curve satisfies the diode equation above. Also plotted is the line representing

VT = iDRT + vD. This line is called the “load line.” The iD and vD values of any point on

the load line satisfies the first equation above. Since the solution to the above two equations

in two unknowns is a pair of iD and vD that satisfies both equations, such a point should

be both on the iv plot of the diode and on the load line, i.e., at the intersection of the two.

This point is called the Q-point or the Quiescent point (or the operating point) of the diode.

The load line technique is not accu-

rate in finding numerical values of

iD and vD. However, it is a power-

ful tool to get qualitative measures

of the circuit behavior e.g., ensur-

ing that the diode operating point

is safety away from the maximum

forward current.-1

0

1

2

3

4

5

6

7

8

-0.5 0 0.5 1 1.5 2 2.5

VD

ID

Q

Load Line

VQ

IQ

VT

VT/RT


Piecewise Linear Model

-1

0

1

2

3

4

5

6

7

8

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1

VD

ID

V

The problem in arriving at an analytical

solution to the diode circuit is that the

diode i − v equation is nonlinear. An ap-

proach would be to try to “approximate”

the diode i − v equation by a linear equa-

tion (i.e., the diode i − v characteristics

curve with a line).

As can be seen from the figure, it is NOT possible to approximate the i − v characteristics

curve with ONE line. However, it is possible to do so with TWO (or more) lines. This type

of approximation is called a piecewise linear model, i.e., pieces of the curve are replaced by

lines. One such model for diodes is shown in the figure with equations:

Diode ON: vD = vγ , and iD > 0

Diode OFF: iD = 0 and vD < vγ ,

Parameter vγ is called the “cut-in” voltage and it is related to the forbidden gap of the base

semiconductor (not what dopant is used and how much). For Si, vγ ≈ 0.6 − 0.7 V. For

GaAs, vγ ≈ 1.7 − 1.9 V. Note that the above equations are valid only for a certain range of

parameters, (or range of validity) e.g., “Diode ON” equation is valid only if iD > 0.

An issue that arises in solving circuits with diodes is that we do not know a priori the state

of the diode (ON or OFF) and so we do not which equation to use. The following “recipe”

can be used to solve diode equations:

Recipe for solving diode circuits:

1. Write down all circuit equation with iD and vD as parameters and simplify as much as

possible.

2. Assume diode is in one state (either ON or OFF). Use the diode equation for that state

to solve the circuit equations and find iD and vD.

3. Check the range of validity inequality with the values of iD and vD that was found. If

iD and vD values satisfy the range of validity, the assumption was correct. Otherwise,

the assumed diode state is incorrect. Go to step 2 above and assume that the diode is

in the other state.


iD vD

−+

−+V

RS

S

Let’s use this method for the Si diode circuit shown with

vs = 5 V and Rs = 1 kΩ.

Step 1: KCL tells that current iD flow in all elements and

by KVL:

vs = iDRs + vD → 5 = 103iD + vD

Step 2: Assume diode is OFF:

Diode OFF: iD = 0 and vD < vγ

Substituting for iD = 0 in the circuit equation, we get:

5 = 103× 0 + vD → vD = 5 V

Step 3: Since vD = 5 > 0.7 = vγ, diode vD does NOT satisfy range of validity and the

assumed diode state is incorrect.

Step 2: Assume diode is ON:

Diode ON: vD = vγ and iD > 0

Substituting for vD = vγ = 0.7 V in the circuit equation, we get:

5 = 103× iD + 0.7 → iD = 4.3 mA

Step 3: Although we know that since diode was not OFF, it should be ON, it is a good

practice to check the range of validity again in case we might have made a math mistake.

For this case, iD > 0 and satisfies range of validity. So diode is ON and vD = 0.7 V and

iD = 4.3 mA.

Parametric solution of diode circuits

It is very useful if we can derive the circuit solution parametrically, i.e., with values of

various circuit elements as parameters. This approach would allows us to solve the circuit

ONCE. For example, for inverting amplifier, we solved the circuit parametrically and found

the gain to be A = −R2/R1. So, if we encounter a circuit with R1 = 1 kΩ and R2 = 10 kΩ,

we can calculate the gain, A = −R2/R1 = −10 without solving any circuit equations.

An example would the diode circuit above in which we would like to find iD and vD in terms

of vs and Rs. The problem is that diode can be either of its two states which in principle

would depend on the values of circuit parameters (vs and Rs in the example above). As a

result, since the diode has two states, we will find TWO solutions to the circuit, each being

valid over a range of parameters as described in the recipe below:


Recipe for solving diode circuits parametrically:

1. Write down all circuit equation with iD and vD and simplify as much as possible.

2. Assume diode is in one state. Use the diode equation for that state to solve the circuit

equations and find iD and vD. Use the range of validity of that state to find a range

of validity for the circuit parameters.

3. Repeat step 2 for all possible states.

For example, consider the circuit above with vs and Rs as parameters. Following our recipe

we get:

KCL tells that current iD flow in all elements and by KVL:

vs = iDRs + vD

Case 1: Diode is OFF:

iD = 0 → vD = vs

vD < vγ → vs < vγ

Case 2: Diode is ON:

vD = vγ → iD =vs − vγ

Rs

iD > 0 →vs − vγ

Rs

> 0 → vs > vγ

Therefore, the parametric solution of the circuit can be summarized as:

vs > vγ → Diode in ON → vD = vγ and iD =vs − vγ

Rs

vs < vγ → Diode in OFF → vD = vs and iD = 0

Note that if we had solved the circuit parametrically first, we can get the answer for the

case vs = 5 V and Rs = 1 kΩ immediately: vs = 5 V > vγ = 0.7 V, therefore, diode is ON,

vD = vγ = 0.7 V and iD = (5 − 0.7)/103 = 4.3 mA.

We will use the above two methods to explore some diode circuits.


4.5 Diode Logic Gates

You have seen binary mathematics and logic gates in ECE25. We will explore some electronic

logic gates in this course. Binary mathematics is built upon two states: 0, and 1. We

need to relate the binary states to currents or voltages as these are the parameters that

we can manipulate in electronic circuits. Similar to our discussion of analog circuits, it is

advantageous (from power point of view) to relate these the binary states to voltages. As

such, we “choose” two voltages to represent the binary states: VL for state 0 or Low state

and VH for state 1 or High state (for example, 0 V to represent state 0 and 5 V to represent

state 1). These voltages are quite arbitrary and can be chosen to have any value. We will

add subscript O and I to these voltages to denote input and output voltages to the gate,

e.g., V OL is the output voltage of the gate at the low state.

V

V

V

H

VL VH

I

VO

L

V

V

V

V V

I

VO

OH

IL

OL OHV VIL IH

Similar to analog circuits, we can plot the voltage transfer

characteristics of a gate. For example, the voltage transfer

characteristics of an “ideal” inverter is shown in the figure,

when the input is low, the output is high and the when the

input is high, the output is low. We can see a difficulty

right away. In a practical circuit, there would be an output

voltage for any input voltage, so the output voltage makes a

“smooth” transition for the high voltage to the low voltage

as the input voltage is varied. We have to be careful as it is

extremely difficult, if not impossible, to design an electronic

circuit to give exactly a voltage like 5 V (what if the input

voltage was 4.99 V?). So, we need to define a range of volt-

ages (instead of one value) to represent high and low states.

We will try very hard to make sure that the output of our

gates to be as close as possible to VOH and VOL. But, we

will design our gates such that they respond to a range of

voltages, i.e., the gate would think that the input is low if

the input voltage is smaller than VIL and would think that

the input is high if the input voltage is larger than VIH .

With this definitions, the voltage transfer characteristics of a practical inverter is shown.

The range of voltages, VOL to VIL and VIH to VOH are called the noise margins. The range

of voltages between VIL to VIH is the forbidden region as in this range, the output of the

gate does not correspond to any binary state. The maximum speed that a logic gate can

operate is set by the time it takes to traverse this region as the input voltage is varied from

one state to another state.


Logic circuits are typically constructed from “basic” logic gates like NOR or NAND. You have

seen in ECE25 that all higher level logic gates, e.g., flip-flops, can be made by a combination

of NOR gates or NAND gates. So, for each logic gate that we will work on, we have to

remember that the output of the logic gate is attached to the input of another logic gate.

o

R

CC

A

11

A

22

1

2

D

i

D

i

i

v

V

v

v

Diode AND Gate: Let us now to proceed to a simple logic

gate, a diode AND gate as is shown. To study the behavior of

the gate we will consider the state of the circuit for different

values of v1 and v2 (either 0 or 5 V corresponding to low and

high states). To aid the analysis, let’s assume VCC = 5 V and

RA = 1 kΩ. We note that by KCL, iA = i1 + i2 (assuming

that there is no current drawn from the circuit).

Case 1, v1 = v2 = 0: Since the 5-V supply will tend to forward bias both D1 and D2,

let’s assume that both diodes are forward biased. Thus, vD1 = vD2 = vγ = 0.7 V and i1 > 0,

i2 > 0. In this case:

vo = v1 + vD1 = v2 + vD2 = 0.7 V

iA =VCC − vo

RA

=5 − 0.7

1, 000= 4.3 mA

Current iA will be divided between two diodes by KCL, each carrying one half of iA (because

of symmetry). Thus, i1 = i2 = 2.1 mA. Since diode currents are positive, our assumption of

both diode being forward biased is justified and, therefore, vo = 0.7 V.

So, when v1 and v2 are low, D1 and D2 are ON and vo is low.

Case 2, v1 = 0, v2 = 5 V: Again, we note that the 5-V supply will tend to forward bias

D1. Assume D1 is ON: vD1 = vγ = 0.7 V and i1 > 0. Then:

vo = v1 + vD1 = 0.7 V

vo = v2 + vD2 → vD2 = −4.3 V < vγ

and D2 will be OFF (i2 = 0). Then:

iA =VCC − vo

RA=

5 − 0.7

1, 000= 4.3 mA

i1 = iA − i2 = 4.3 − 0 = 4.3 mA

Since i1 > 0, our assumption of D1 being forward biased is justified and, therefore, vo = 0.7 V.


So, when v1 is low and v2 is high, D1 is ON and D2 is OFF and vo is low.

Case 3, v1 = 5 V, v2 = 0 V: Because of the symmetry in the circuit, this is exactly the

same as case 2 with roles of D1 and D2 reversed.

So, when v1 is high and v2 is low, D1 is OFF and D2 is ON and vo is low.

Case 4, v1 = v2 = 5 V: Examining the circuit, it appears that the 5-V supply will NOT

be able to forward bias D1 and D2. Assume D1 and D2 are OFF: i1 = i2 = 0, vD1 < vγ and

vD2 < vγ. Then:

iA = i1 + i2 = 0

vo = VCC − i1RA = 5 − 0 = 5 V

vD1 = vo − v1 = 5 − 5 = 0 < vγ and vD2 = vo − v2 = 5 − 5 = 0 < vγ

Thus, our assumption of both diodes being OFF are justified.

So, when v1 and v2 are high, D1 and D2 are OFF and vo is high.

Overall, the output of this circuit is high only if both inputs are high (Case 4) and the output

is low in all other cases (Cases 1 to 3). Thus, this is an AND gate. This analysis can be

easily extended to cases with three or more diode inputs.

This is actually not a good gate as for input we used low states of 0 V and the output low

state was 0.7 V. We need to make sure that the input low state voltage is similar to the

output low state voltage so that we can put these gates back to back. (You can easily show

that if we had assumed low states of 0.7 V for input, the output low state would have been

1.4 V.) This gate is not usually used by itself but as part of diode-transistor logic gates that

we will discuss in the BJT section.

Diode OR Gate: Show that this circuit is an OR gate.

e

RA

o

11

22

D

Dv

v

v


4.6 Rectifier Circuits

iD

vD

vL

iL

−+VS

−+

RL

−

+This circuit is similar to the circuit we have solved in

page 86. There, we found:

vs < vγ → Diode in OFF: iD = iL = 0 and vL = 0

vs > vγ → Diode in ON: iD = iL =vs − vγ

RL

and vL = vs − vγ

Consider a case in which vs is a sinusoidal

waveform, vs = Vs cos(ωt). In the positive

half of the input period with vs > vγ, diode

is ON and vL = vs − vγ and in the rest of

the input period, vs < vγ , diode if OFF

and vL = 0 as is shown.

Exercise: Explain why the output voltage

is NOT exactly vL = vs−vγ at every point.

The above circuit is a simple method to convert AC input voltages to a “DC” output voltage

and is used in AC to DC converter part of power supplies. Such circuits are called “rectifier”

circuits. Because the output of the circuit is only one half of the input waveform, the above

circuit is called a “half-wave” rectifier circuit.

A better circuit would be a “full-wave” rectifier in which both portion of the AC input

waveform is turned into a DC output (so that we do not “throw” away half of the input).

An example of such a full-wave rectifier is the bridge rectifier shown below with four diodes.

We can see that in the portion of the input period in which vs > 2vγ , diodes D1 and D3 are

ON and a positive voltage appear across RL. Diodes D2 and D4 are OFF. In the portion

of the waveform in which vs < −2vγ , Diode D2 and D4 are ON and diodes D1 and D3 are

OFF and again a positive voltage appears on RL. The resulting voltage across RL is shown

below.


4.7 Peak Detector

Another popular diode circuit is the peak detector which is similar to the half-wave rectifier

circuit with the addition of a capacitor. Following the same procedure, we find:

vD = vs − vC > vγ → vs > vC + vγ → Diode in ON

vD = vs − vC < vγ → vs < vC + vγ → Diode in OFF

vDiL

−+VS

−+

−

+RL

C VLV

−

+C

V − VS γiL

−+

−

+VC+

LLRVC−

iL

−+

−

+VVS

V RL L+

C−

C

Diode is ON Diode is OFF

So, when vs > vC + vγ and diode is ON, we have a parallel RC circuit and capacitor will be

charged up (middle circuit). When vs < vC +vγ , we have an RC circuit (circuit to the right)

and the capacitor discharges in the resistor with a time constant τ = RC.

The output voltage wave form is shown if the

value of the capacitor is chosen such that τ =

RC T (T is the period of the input AC

voltage). To understand the shape of output

waveform, let’s assume that voltage across the

capacitor was zero at t = 0.

As the input voltage increases in the first quarter wave period (vγ < vs < Vs), the capacitor

charges up as vs > vC + vγ and diode is ON. In the second quarter of the wave period, the


input voltage vs is decreasing. In this case, diode is OFF and the capacitor slowly discharges

in RL. This continues until the next period when vs becomes again larger than vC + vγ and

capacitor charges for a short period of time.

Exercise: What would have if τ = RC T where T is the period of the input AC voltage?

This circuit has two applications. First, by adding a large capacitor (10s to 100s of µF) to

our rectifier circuit, we get a relatively smooth DC output. Similarly such a capacitor can be

added to a full-wave rectifier circuit. (All AC to DC converters have such a large capacitor).

Second, the above circuit can be used as a “peak-detector” circuit. For example, consider

the signal transmitted from an AM station. Such a signal includes a carrier wave (radio

station frequency). The amplitude of the carrier is modulated according the sound signal.

An example of such a signal is shown below (assuming that the sound signal is a triangular

wave). If we apply this modulated voltage to our “peak-detector” circuit above and choose

the value of capacitor such that τ = RC Trf where Trf is the period of radio-frequency

carrier wave but τ = RC Tso where Tso is the period of the sound wave, the output of

the circuit would be an approximation of the the initial sound wave as is shown below. The

circuit is called the peak-detector because the output voltage is the envelope of the peak

amplitudes of the input signal.

4.8 Zener Diodes

Zener diodes are specially manufactured to operate in the Zener region. These diode are

made by means of heavily doped regions near the metal contacts to the semiconductor.

The high density of charge carriers provides the means for a substantial reverse breakdown

current to be sustained. These diodes are useful in applications where one would like to hold

some load voltage constant, for example, in voltage regulators.

The circuit symbol, the i − v characteristics of Zener diodes and a piece-wise linear model

are shown below:


iD

vvD

γ

−vZ

+

_v

iD

D

The piece-wise linear characteristics equations are:

Diode ON: vD = vγ , and iD > 0

Diode OFF: vD < vγ , and iD = 0

Diode in Zener Region: vD = −vZ , and iD < 0

Circuit solution techniques developed in this sections for diodes can be applied directly to

Zener diodes. The only change is that Zener diodes can have three states (instead of two for

regular diodes).

A simple Power Supply

vS vD vLiD

iL

+_

+i

R

+

_

_

RL

An independent voltage source is a circuit in

which the output voltage is constant regardless

of the current drawn from the circuit. This

circuit (with vs > 0) is such an independent

voltage source, i.e., the output voltage, vL is

constant for a range of iL’s. It is a simple power

supply circuit if we replace the voltage source

vs with the rectifier (and capacitor) circuit that

we developed before.

We will use the parametric method to analyze this circuit. First, we write down the circuit

equations:

KCL: i = −iD + iL

KVL: vs = Ri − vD

KVL: vL = −vD


Case 1: Diode is in the Zener region. In this case, vD = −vZ and iD < 0. Substituting

for vD = −vZ in the third equation above, we find vL = vZ and is independent of iL. So,

if the diode is in the Zener region, this circuit would behave like an independent voltage

source. To find the range of iL for which the diode is in the Zener region, we calculate iDfrom equations above:

i =vs + vD

R=

vs − vZ

R

iD = iL − i < 0 → iL < i =vs − vZ

R

Therefore, as long as iL is smaller than the value iL,max = (vs − vZ)/R, the diode would

remain in the Zener region and the circuit would act as an independent voltage source.

Case 2: Diode is in the reverse bias region. In this case, iD = 0 and −vZ < vD < vγ .

Substituting for iD = 0 in the above circuit equations, we get:

KCL: i = −iD + iL = iL

KVL: vs = Ri − vD → −vD = vs − RiL

KVL: vL = −vD = vs − RiL

Thus, in this region the output voltage does not remain constant, rather it decreases with iL.

The diode is in the the reverse bias region as long as vD > −vZ or iL > iL,max = (vs−vZ)/R.

Case 3: Diode is in the forward bias region. Since vs > 0, the diode CANNOT be in the

forward bias region.

The i − v characteristics of this circuit is shown in the figure

vL

L,maxi v /RS

Diode inZener Region

Diode inReverse Bias

vZ

Li


4.9 Wave-form shaping Circuits

A wide-variety of waveform shaping circuits are used in electronics. These circuits are used

to transform one waveform into another. Two examples of such circuits made with diodes

are below.

Clipper Circuit

Diodes can be used to “clip” off a portion of the input signal. Consider the circuit below:

vi = RiD + vD + vDC

vo = vD + vDC = vi − RiD

Diode ON: vD = vγ and iD > 0

vo = vγ + vDC and iD =vi − vγ − vDC

R> 0 → vi > vγ + vDC

Diode OFF: iD = 0 and vD < vγ

vo = vi − 0 × R = vi and vD = vi − RiD − vDC < vγ → vi < vγ + vDC

So, when vi < vγ + vDC, the diode is OFF and vo = vi: the output signal is exactly the same

as the input signal. However, when vi exceeds this value of vγ + vDC , the diode is ON and

vo = vγ + vDC . As a result, the input signal is “clipped” when it exceeds vγ + vDC . The

shape of the output signal for a sinusoidal input signal is shown below.

vi

vov + vDC

Vo−+

DCV

V

R +

−

i

−

+

Similarly, the circuit below will clip the input at −vγ − vDC

vi

vo- v - vDC

Vo−+

SDC

VV

R +

−

−

+


And the two circuits can be combined to clip both the positive and negative values.

vi

vov + vDC

- v - vDC

VDC1 VDC2

Vo−+

SV

R +

−−

+ −

+

It is usually more convenient to use zener diodes instead of vDC voltage sources. The three

circuits below clip the input, respectively from left to right, at vγ + vZ1, at −vγ − vZ2, and

at both +vZ1 and −vZ2.

Vo−+

SV

+

−

D2

R

Vo−+

SV

+

−

D2

R

Vo−+

SV

+

−

D2

D1R

Exercise: Prove that circuits above clip the input voltage at the values given.

Clamp Circuit

Another popular diode circuit is the diode clamp which is similar to the peak-detector circuit

with the location of diode and capacitor switched as is shown below.

−+VS

−

+

L VR L

C

SV − Vγ

−+

+ −

C

CV

−+

S

−

+

+ −

CV

V

L VLR

C

Diode is ON Diode is OFF

From the circuit we have, vD = vs − vC .

Diode is ON if vs > vC + vγ . In this case, the circuit simplifies to the circuit in the middle

and capacitor charges up (because the diode is ON and it has a “zero” resistance, the current

in RL would be zero and RL does not appear in the circuit).

Diode is OFF when vs < vC + vγ. In this case, the circuit simplifies to the circuit to the left

with diode being open circuit.


When input is a sinusoidal wave, during the

positive half cycle when vs > vC + vγ diode is

ON and the capacitor charges up (see circuits

above). During the negative half cycle when

diode is OFF, the capacitor discharges little if

τ = RC T (similar to the peak detector

circuit). Eventually capacitor will become fully

charged such that vC = Vs −vγ where VS is the

amplitude of the input signal, vs = Vs cos(ωt).

From then on, diode remains in the OFF position during both negative and positive half

cycle . Since vL = vs − vC , the effect of the constant DC voltage across the capacitor

(vC = Vs − vγ) is to produce an output signal which is similar to the input signal with an

addition of a DC voltage (negative in this case) as is shown above.

The clamp circuit above produces an output signal which is shifted downward by the value of

Vs − vγ . Different values of downward shift can be produced by the addition of a DC voltage

circuit in series with the diode. Alternatively, an upward shift can be produced by switching

the polarity of the diode as is shown in circuits below (Note that VDC can be negative).

−+

S

−

+V

DC

RL

C

VV

L

−

+ LR−+

S

−

+V

C

V L−+V

−

+

DC

RL VL

C

VS −

+

down-shift by Vs − vγ − VDC up-shift by Vs − vγ up-shift by Vs − vγ − VDC

Similar to the clipper circuit, the voltage sources in the clamp circuits can be replaced by

zener diodes as is shown below.

−+

S

−

+VR

L

C

V L−+V

−

+RL VL

C

S

down-shift by Vs − vγ − vz up-shift by Vs − vγ − vz


4.10 Exercise Problems

In circuit design, use commercial resistor values (1, 1.1, 1.2, 1.3, 1.5, 1.6, 1.8, 2, 2.2, 2.4, 2.7,

3., 3.3, 3.6, 3.9, 4.3, 4.7, 5.1, 5.6, 6.2, 6.8, 7.5, 8.2, 9.1) and commercial capacitor values (1,

1.5, 1.8, 2. or 2.2, 3.3, 4.7, and 6.8) values. You can also use zener diodes with any Zener

voltage.

Problems 1 to 9. In circuits below with Si diodes and vZ = 5 V for Zener diodes, A) Find

v and/or i for vs = 10 V, B) Find v and/or ifor vs ranging from −20 to +20 V.

−+VS

+ _ iV

5ki

V−

+

−+VS

5k

5k S−+

−+V

i

5V

5k

Problem 1 Problem 2 Problem 3

SV−+

2k

1k V−

+

iSV

−+

2k

1k V−

+

i

VS+ _V

i

5k10k

10k5k


VS+ _V

i

5k10k

10k

5k

S

−

+1k1k vv +

−

S

1k1kv

v

+

−

+−



Problems 10 to 12. Find vo for vs = Vs sin(ωt). (Si diodes and vZ = 5 V for Zener diodes)

Vo−+

SV

+

−

R

R

Vo−+

SV

+

−

R

R

Vo−+

SV

R +

−


Problem 13. Design a clipper circuit that clips voltages above 5 V using a) DC power

supplies only, b) Zener diodes only.

Problem 14. Design a clipper circuit that clips voltages above 5 V and below −3 V using

a) DC power supplies only, b) Zener diodes only.

Problem 15. Design a clipper circuit that clips voltages above 5 V and below +3 V using


Problem 16. Consider a sinusoidal source with vi = 15 sin(ωt) V. Design a clamp circuit

that adds a DC offset of +5 to the input voltage using a) DC power supplies only, b) Zener

diodes only.

Problem 17. Consider a sinusoidal source with vi = 15 sin(ωt) V. Design a clamp circuit

that adds a DC offset of −5 to the input voltage using a) DC power supplies only, b) Zener

diodes only.

Problem 18. Circuit below is a “voltage doubler.” Show that if vs = Vs sin(ωt), vo = 2Vi

(Assume that capacitor C is large such that it discharge very little per cycle and Vs vγ .)

Problem 19. Circuit below is a simplified version of an electronic flash for cameras. Switch

S2 is controlled by the shutter and is closed to operate the flash bulb. Normally switch S2

is open. The circuit to the left of switch S2 charges the capacitor to about 100 V using a

1.5 V battery. Switch S1 is an electronic switch that is opened and closed at about 10 kHz.

As a result, the capacitor is charged to about 100 V using a 1.5 V battery. Explain how the

charge-up circuit works.

C 1

C 2

2D

1D−+VS

−

+

L VR L

A

S1

S2

R

C1.5 V−

+

Problem 18 Problem 19


4.11 Solution to Selected Exercise Problems

Problem 2. In circuit below with Si diodes, A) Find v and/or i for vs = 10 V, B) Find v

and/or i for vs ranging from −20 to +20 V.

i

SV−+

5k

5k V−

+iSCircuit equations:

KCL: is = iD + i

KVL: vs = 5 × 103is + vD

KVL: v = vD = 5 × 103i

Part A: vs = 10 V.

Assume diode is ON: vD = vγ = 0.7 V, iD > 0. Substituting in the above equations we get:

vs = 5 × 103is + vD → 10 = 5 × 103is + 0.7 → is = 1.86 mA

v = vD = 0.7 V

v = vD = 5 × 103i → 0.7 = 5 × 103i → i = 0.14 mA

is = iD + i → 1.86 × 10−3 = iD + 0.14 × 10−3→ iD = 1.72 mA

Since iD = 1.72 mA > 0, our assumption of diode being ON is correct and i = 0.14 mA and

v = 0.7 V.

Part B: Parametric Solution:

For diode being ON: vD = vγ = 0.7 V, iD > 0. Substituting in the circuit equations we get:

vs = 5 × 103is + vD → vs = 5 × 103is + 0.7 → is = 2 × 10−4(vs − 0.7) A

v = vD = 0.7 V

v = vD = 5 × 103i → 0.7 = 5 × 103i → i = 0.14 mA

is = iD + i → iD = is − 0.14 × 10−3 = 2 × 10−4(vs − 0.7) − 1.4 × 10−4

iD > 0 → 2 × 10−4(vs − 0.7) − 1.4 × 10−4 > 0 → vs > 1.4 V

For diode being OFF: iD = 0 and vD < vγ = 0.7 V. From circuit equations, we get:

is = iD + i → is = i


vs = 5 × 103is + vD = 5 × 103is + 5 × 103i = 1 × 104i → i = 10−4vs

v = vD = 5 × 103i → v = vD = 0.5vs

vD < vγ = 0.7 → 0.5vs < 0.7 → vs < 1.4 V

Therefore, for vs < 1.4 V, diode is OFF v = 0.5vs and i = 10−4vs.

For vs > 1.4 V, diode is ON, v = 0.7 V, and i = 0.14 mA.



SV 1D

2D

−+

2k

1k V−

+

i

Circuit equations:

KVL: vs = vD1 + 2 × 103iD1

KVL: vs = 103iD2 + vD2

v = 103iD1 and i = iD1

Part A: vs = 10 V.

Assume both diodes are ON: vD1 = vD2 = vγ = 0.7 V, iD1 > 0, and iD2 > 0. Substituting in

the above equations we get:

KVL: vs = vD1 + 2 × 103iD1 → 10 = 0.7 + 2 × 103iD1 → iD1 = 4.65 × 10−3 = 4.65 mA

KVL: vs = 103iD2 + vD2 → 10 = 0.7 + 103iD2 → iD2 = 9.3 × 10−3 = 9.3 mA

v = 103iD1 → v = 4.65 V

Since both iD1 and iD1 are positive, our assumption of both diodes being ON is correct and

v = 4.65 V and i = iD1 = 4.65 mA.

Part B: Parametric Solution: Here, we have to consider four cases.

Case 1: D1 and D2 are both ON: vD1 = vD2 = vγ = 0.7 V, iD1 > 0, and iD2 > 0.

KVL: vs = vD1 + 2 × 103iD1 → vs = 0.7 + 2 × 103iD1 → iD1 = 5 × 10−4(vs − 0.7)

KVL: vs = 103iD2 + vD2 → vs = 0.7 + 103iD2 → iD2 = 10−3(vs − 0.7)

v = 103iD1 → v = 0.5(vs − 0.7)

iD1 > 0 → 5 × 10−4(vs − 0.7) > 0 → vs > 0.7 V

iD2 > 0 → 10−3(vs − 0.7) > 0 → vs > 0.7 V


So, for vs > 0.7 V, both diodes will be ON with v = 0.5(vs − 0.7) V and i = iD1 =

5 × 10−4(vs − 0.7) = 0.5(vs − 0.7) mA.

Case 2: D1 and D2 are both OFF: iD1 = iD2 = 0, vD1 < vγ = 0.7 V, and vD2 < vγ = 0.7 V.

KVL: vs = vD1 + 2 × 103iD1 → vD1 = vs

KVL: vs = 103iD2 + vD2 → vD2 = vs

v = 103iD1 → v = 0

vD1 < vγ = 0.7 → vs < 0.7 V

vD2 < vγ = 0.7 → vs < 0.7 V

So, for vs < 0.7 V, both diodes will be OFF with v = 0 and i = iD1 = 0

Note that since for vs > 0.7 V, both diodes will be ON and for vs < 0.7 V, both diodes will

be OFF, one would expect that it would not be possible for one diode to be ON and one to

be OFF. We will demonstrate this below.

Case 3: D1 is ON: vD1 = vγ = 0.7 V, and iD1 > 0 while D2 is OFF: iD2 = 0 and vD2 < vγ =

0.7 V.

KVL: vs = vD1 + 2 × 103iD1 → vs = 0.7 + 2 × 103iD1 → iD1 = 5 × 10−4(vs − 0.7)

KVL: vs = 103iD2 + vD2 → vD2 = vs

v = 103iD1 → v = 0.5(vs − 0.7)

iD1 > 0 → 5 × 10−4(vs − 0.7) > 0 → vs > 0.7 V

vD2 < vγ = 0.7 → vs < 0.7 V

We see that for D1 to be ON (iD1 > 0), we need vs > 0.7 V and for D2 to be OFF (vD2 < vγ)

we need vs < 0.7 V. These cases are mutually exclusive so we cannot have simultaneously

D1 ON and D2 OFF.

Similarly, we can find D1 is OFF and D2 ON case is not possible.




VS

1D2D

+ _V

i

5k10k

10k5k

Part A: vs = 10 V.

With the exception of simple circuits, it is usually more useful

to redraw the circuit based on the state of the diodes as this

can simplify the circuit considerably. Note that when a diode is

ON, vD = vγ for iD > 0 and the diode resembles an ideal voltage

source with the strength of vγ. When the diode is OFF, iD = 0

and the diode resembles an open circuit. This can be seen in

circuits below:

VS

V1 V2

V3iD2

iD1

+ _V

i

5k10k

5k10k

0.7 V −

+

−+

VS

V1 V2

V3iD2

iD1

+ _V

i

5k10k

5k10k

0.7 V

−+

VS

V1 V2

V3iD2

iD1

+ _V

i

5k10k

5k10k

0.7 V −

+

VS

V1 V2

V3

iD2

iD1

+ _V

i

5k10k

5k10k

D1 ON D1 ON D1 OFF D1 OFF

D2 ON D2 OFF D2 ON D2 OFF

Case 1: Assume D1 is ON and D2 is ON. The above circuit can be solved by node voltage

method. This circuit has four nodes, v1, v2, v3, and vs = 10 V. All nodes are supernodes as

they are attached to a voltage source. So we have only we KCL containing nodes v1, v2, and

v3:

Supernode: v1 − v2 = 0.7


KCL at v1, v2, v3:v1 − vs

10 × 103+

v3 − vs

5 × 103+

v1 − 0

5 × 103+

v2 − 0

10 × 103= 0

v1 − vs + 2(v3 − vs) + 2v1 + v2 = 0

3v1 + v2 + 2v3 = 3vs = 30 V

We substitute for v1 and v3 from the first two equations in the last equation to get:

3(v2 + 0.7) + v2 + 2(v2 + 0.7) = 30 → v2 = 4.42 V and v1 = v3 = 5.12 V


To check the validity of our assumption of D1 and D2 ON, we need to compute iD1 and iD2.

iD2 is the same as the current in the 5 k resistor on the top of the circuit and iD2 can be

found by KCL at node v1:

iD1 =vs − v1

10 × 103+

0 − v1

5 × 103=

10 − 5.12

10 × 103+

−5.12

5 × 103= −0.54 mA < 0

iD2 =vs − v3

5 × 103=

10 − 5.12

5 × 103= 0.98 mA > 0

Since iD1 < 0, our assumption is incorrect and we should consider other cases.

Case 2: Assume D1 is ON and D2 is OFF. The above circuit can be solved by node voltage

method. This circuit has three nodes, v1, v2, and vs = 10 V (v3 = vs = 10 V as iD2 = 0).

All nodes are supernodes as they are attached to a voltage source. So:


KCL at v1, v2:v1 − vs

10 × 103+

v1 − 0

5 × 103+

v2 − 0

10 × 103= 0

v1 − vs + 2v1 + v2 = 0 → 3v1 + v2 = vs = 10 V

We substitute for v1 from the first equation in the second equation to get:

3(v2 + 0.7) + v2 = 10 → v2 = 1.98 V and v1 = 2.68 V

To check the validity of our assumption of D1 ON and D2 OFF, we need to compute iD1

(KCL at node v1) and vD2.

iD1 =vs − v1

10 × 103+

0 − v1

5 × 103=

10 − 1.98

10 × 103−

1.98

5 × 103= 4.06 mA > 0

vD2 = v3 − v2 = 10 − 1.98 = 8.02 > 0.7 V

Since vD2 > 0.7, our assumption is incorrect and we should consider other cases.

Case 3: Assume D1 is OFF and D2 is ON. The above circuit can be solved by node voltage

method. This circuit has four nodes, v1, v2, v3, and vs = 10 V. All nodes except v1 are

supernodes as they are attached to a voltage source. So:


KCL at v2, v3:v3 − vs

5 × 103+

v2 − 0

10 × 103= 0 → 2v3 − 20 + v2 = 0

KCL at v1:v1 − vs

10 × 103+

v1 − 0

5 × 103= 0 → v1 − 10 + 2v1 = 0 → v1 = 3.33 V


The first two equations can be solved to find v2 and v3:

2(v2 + 0.7) + v2 = 20 → v2 = 6.2 V → v3 = 6.9 V

To check the validity of our assumption of D1 OFF and D2 ON, we need to compute vD1

and iD2.

vD1 = v1 − v2 = 3.33 − 6.2 = −2.87 < 0.7 V

iD2 =vs − v3

5 × 103=

10 − 6.9

5 × 103= 0.62 mA > 0

Since vD1 < 0.7 and iD2 > 0, our assumption is correct. So D1 is OFF, D2 is ON and

i = iD2 = 0.62mA and v = vs − v3 = 10 − 6.9 = 3.1 V.

This case could have been solved more simply by noting that when D1 is OFF, the two

branches of the circuit become independent (we have two separate circuits) and v1 and v2

can be directly calculated:

v1 =5 × 103

10 × 103 + 5 × 103× 10 = 3.33 V

i = iD2 =vs − 0.7

10 × 103 + 5 × 103= 0.62 mA

and proceed to compute vD1 < 0.7 to show that our assumption was valid.

Case 4: Assume D1 is OFF and D2 is OFF.

While we proved that D1 is OFF and D2 is ON, let’s proceed to solve this case. Again, we

see that two branches of the circuit are independent. In addition, since i = 0, v2 = 0 and

v3 = vs = 10 V. From voltage divider, we have v1 = 3.33 V (similar to case 3).

To check our assumption, we note vD1 = v1 − v2 = 3.33− 0 = 3.33 > 0.7 V so D1 cannot be

OFF and assumption was incorrect.

As can be seen, the simplest circuit is when diodes are OFF as the circuit usually divides

into several simpler circuits. As such, if one cannot make an educated guess regarding the

state of the diodes, it is usually best to start the analysis with diodes being OFF.


Part B: Parametric Solution: Here, we have to consider four cases. As discussed above, we

will start with simplest cases (diodes OFF).

Case 1: D1 and D2 are both OFF: we see that two branches of the circuit are independent.

In addition, since i = 0, v2 = 0 and v3 = vs. From voltage divider, we have v1 = vs/3.

To find the range of validity of this solution,

vD1 = vs/3 < vγ → vs < 2.1 V

vD2 = v3 − v2 < vγ → vs < 0.7 V

For both diodes to be OFF, we need vs < 0.7 V (the most restrictive of both conditions).

So, for vs < 0.7 V, both diodes will be OFF, i = 0 and v = 0

Case 2: D1 OFF and D2 ON: we see that two branches of the circuit are independent. From

voltage divider, we have v1 = vs/3 V.

i = iD2 =vs − 0.7

10 × 103 + 5 × 103= 6.67 × 10−5(vs − 0.7)

v = 5 × 103i = 0.33(vs − 0.7)

To find the range of validity of this solution,

iD2 = 6.67 × 10−5(vs − 0.7) > 0 → vs > 0.7 V

vD1 = v1 − v2 < vγ →vs

3− 10 × 103i < 0.7

0.33vs − 0.67(vs − 0.7) < 0.7 → vs > −0.7 V

For D1 OFF and D2 ON, we need vs > 0.7 V (the most restrictive of both conditions).

So, for vs > 0.7 V, D1 OFF and D2 ON, i = 6.67 × 10−5(vs − 0.7) and v = 0.033(vs − 0.7).

Since for vs < 0.7 V, both diodes will be OFF and for vs > 0.7 V, D1 is OFF and D2 is ON,

there is no range of values for vs when other cases (D1 ON and D2 OFF or both ON) are

possible.

Exercise: Solve circuit equations directly to show that D1 ON and D2 OFF Case or both

diodes ON Cases are not physically possible.




iD

i1

s

i

1 kΩ1 kΩv v

−

++−

Part A: vs = 10 V.

Assume diode is OFF: iD = 0 and vD < vγ = 0.7 V. Then

i1 = i = vs/(103 + 103) = 5 mA and v = 103i = 5 V.

To check the our assumption, we note vD = 103i1 = 5 >

0.7 V, so the assumption is incorrect.

Assume diode is ON: vD = vγ = 0.7 V and iD > 0 Then

by KVL: v = vs − vD = 9.3 V and i = v/103 = 9.3 mA.

To check the our assumption, we note i1 = vD/103 = 0.7 mA and by KCL iD = i − i1 =

8.6 mA. Since iD > 0, our assumption is correct.

Therefore, diode is ON and i = 9.3 mA and v = 9.3 V.

Part B: Parametric Solution:

Case 1: Assume diode is ON: vD = vγ = 0.7 V and iD > 0.

KVL: v = vs − vD = vs − 0.7

To check the region of validity of our assumption we need to calculate iD:

i1 =vD

103= 0.7 × 10−3 A = 0.7 mA and i =

v

103= 10−3

× (vi − 0.7)

iD = i − i1 > 0 → 10−3× (vs − 0.7) − 0.7 × 10−3 > 0 → vs > 1.4 V

So, if vs > 1.4 V, the diode will be ON and v = vs − 0.7 V.

Case 2: Assume diode is OFF: iD = 0 and vD < vγ = 0.7 V.

KCL: i = i1 + iD = i1

KVL: vs = 103i1 + 103i = 2 × 103i → i = i1 = 0.5 × 10−3vs

v = 103i = 0.5vs

To check the region of validity of our assumption we need to calculate vD:

vD = vs − v = vs − 0.5vs = 0.5vs

vD < vγ → 0.5vs < 0.7 → vs < 1.4 V

So, if vs < 1.4 V, the diode will be OFF and v = 0.5vs.


Problem 10. Find vo for vi = Vi sin(ωt).

Vo2D

1D

−+

SV

+

−

R

R

The regular diode can have two states (ON and OFF) and

the Zener diode has three states (ON, OFF, and Zener).

So, it appears that we need to consider 2×3 = 6 possible

cases. However, an examination of the circuit shows that

only two of these six combinations are possible by nothing

iD1 = −iD2.

If D1 is ON, iD1 > 0. This means that iD2 < 0 and D2 diode has to be in Zener state.

If D2 is OFF, iD1 = 0. This means that iD2 = 0 and D2 diode has to be OFF.

Case 1: D1 is ON (vD1 = vγ = 0.7 V, iD1 > 0) and D2 is in Zener state (vD2 = −vZ = −5 V

and iD2 < 0). By KVL:

vs = RiD1 + vD1 − vD2 + RiD1 → iD1 =vs − vD1 + vD2

2R

vo = vs − RiD1 = vs − 0.5(vs − vD1 + vD2) = 0.5(vs + vD1 − vD2) = 0.5(vs + 5.7)

The range of validity of this solution can be found by setting iD1 > 0 (iD2 < 0 will be

automatically satisfied).

iD1 =vs − vD1 + vD2

2R> 0 → vs > vD1 − vD2 = 0.7 + 5.0 = 5.7 V

Case 2: D1 and D2 are OFF (iD1 = iD2 = 0, vD1 < vγ = 0.7 V, −vZ < vD2 < vγ = 0.7 V).

In this case, vo = vs − RiD1 = vs.

The range of validity of this solution can be found by noting:

vD1 − vD2 = vo = vs

vD1 < vγ and − vγ < −vD2 < vZ

vD1 − vD2 < vγ + vZ → vs < vγ + vZ = 5.7 V

In sum, when vs < 5.7 V, vo = vs and vs > 5.7 V, vo = 0.5(vs + 5.7).


Problem 12. Find vo for vs = Vs sin(ωt).

Vo3D

4D

5D

1D

2D−+

SV

R +

−

Diodes D3, D4, and D5 all have the same state

(all are ON or all OFF). So, they act like ONE

diode with a cut-in voltage of 3vγ = 2.1 V. There-

fore, examination of the circuit shows that this

is a clipper circuit. It clips the input voltage

above vγ +vZ = 5.7 V and clips the voltage below

−3vγ = −2.1 V

Problem 14. Design a clipper circuit that clips voltages above 5 V and below −3 V using


VDC1 VDC2

Vo−+

SV

R +

−−

+ −

+

Part A: Set vγ + VDC1 = 5 or VDC1 = 4.3 V

Set −vγ − VDC2 = −3 or VDC2 = 2.3 V

Vo−+

SV

+

−

D2

D1R

Part B: Set vγ + vZ1 = 5 or vZ1 = 4.3 V

Set −vγ − vZ2 = −3 or vZ2 = 2.3 V

Problem 16. Consider a sinusoidal source with vs = 15 sin(ωt) V. Design a clamp circuit

that adds a DC offset of +5 to the input voltage using a) DC power supplies only, b) Zener

diodes only.

−+V

−

+

DC

RL VL

C

VS −

+

Part A: Set Vs − VDC = 5 or VDC = 15 − 5 = 10 V.

−+V

−

+RL VL

C

S

Part B: Set Vs − vZ = 5 or vZ = 15 − 5 = 10 V


Problem 18. Circuit below is a “voltage doubler.” Show that if vs = Vs sin(ωt), vo = 2Vs

(Assume that capacitor C is large such that it discharge very little per cycle and Vs vγ .)

C 1

C 2

2D

1D−+VS

−

+

L VR L

A

Capacitor C1 and diode D1 form a clamp circuit. As a result the voltage at point A is a

sinusoidal voltage with a DC offset of Vs (ignoring vγ). Diode D2 and capacitor C2 form

a peak-detector circuit. They will generate a DC signal with a value which is equal to the

peak of AC signal or 2Vs

Problem 19. Circuit below is a simplified version of an electronic flash for cameras. Switch

S2 is controlled by the shutter and is closed to operate the flash bulb. Normally switch S2

is open. The circuit to the left of switch S2 charges the capacitor to about 100 V using a

1.5 V battery. Switch S1 is an electronic switch that is opened and closed at about 10 kHz.

As a result, the capacitor is charged to about 100 V using a 1.5 V battery. Explain how the

charge-up circuit works.

S1

S2

R

C1.5 V−

+

When the electronic switch is closed, the battery increases the inductor current, i.e., inductor

charges up as its magnetic stored energy increases. When the electronic switch opens, the

inductor current cannot change suddenly. The inductor current has to flow through the

diode and the capacitor which charges up the capacitor and increases its voltage (Note

iL = iC = Cdvc/dt > 0 leads to an increase in vC). So each time, the electronic switch closes

and opens, the capacitor voltage is increased. When the capacitor reaches its desired voltage,

the elctronic switch stays at open position. Diode D1 prevents the capacitor to discharge

back into the power supply and resistor R.

Note that The inductor can charge the capacitor voltage to a high value without violating

KVL as during the capacitor charge up cycle, a negative voltage appears across the inductor

vL = Ldi/dt which means that capacitor voltage would become much larger than the battery

voltage.


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