ivan peric, clic workshop 2014 1 hvcmos for clicpix v2

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van Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

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Page 1: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 20141

HVCMOS for CLICPix V2

Page 2: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 2014

HVCMOS CCPD

2

• ….

LV

NMOS PMOS

Page 3: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 2014

Plans

• AMS H18 on high resistive substrate run ~November 2015• Substrate resistivities 20 Ohm – 1k Ω cm• Depleted zone thicknesses: 15/30um (20/80Ω cm), 50um (200Ω cm), 100um (1kΩ cm) • Improvements – added source follower for better timing and less power constumption• Segmented pixels (16.6 um)• Run shared within ATLAS, Mu3e and CLIC• CLIC area ~ 5cm x 5cm• Cost ~ 160k for two substrate types• Intended power CLIC power per pixel ~1-2uW – peaking time 20ns (capacitance 20fF) 160-320mW• Pixel size 25 um x 25 um• Probably possible 16 um• Present scheme ~10uA for 200fF (50 x 250) – peaking time 20ns

3

Page 4: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 20144

CLIC Pixel

A

BL

BLR

OutBLOutAmp

To CLICPIX

• CLIC Pixel

• Size: 25um x 25um

• Analog signal is transferred to CLICPIX readout chip, no discriminator in pixel

• Simple and small pixels, small capacitance, smaller noise

• Spatial resolution can be improved and time-walk can be corrected by measuring of signal amplitudes

• Second stage amplifier added to increase output amplitude

2nd Stage

Page 5: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 20145

Improvement

A

BL

BLRes

OutBLOutAmp

• …

2nd Stage

VNClic, VNLoad

VNFB

RED: Bias Voltages generated internally

BLUE: External Voltages

VNFoll

Page 6: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 20146

Segmented pixel

A

BL

BLRes

OutBLOutAmp

• …

2nd Stage

VNClic, VNLoad

VNFB

RED: Bias Voltages generated internally

BLUE: External Voltages

VNFoll

InR/L=En

Variable voltage

Saturated signal

Page 7: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 20147

ATLAS pixel

A

BL

BLRes

OutBLOutAmp

To FEI4

• Analog pixel• Size: 25um x 250um• Analog signal is transferred to the readout chip, no discriminator in pixel• Second stage amplifier added to increase the output amplitude• Simulated noise ~30e

2nd Stage

VNClic, VNLoad

VNFB

RED: Bias Voltages generated internally

BLUE: External Voltages

VNFoll

InR/L=En

Middle pixels send two signal copies to two pads

Variable voltage

Page 8: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 2014

ATLAS Analog pixel: layout

8

Page 9: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 2014

ATLAS pixel

9

L0 R0 L1 R1 L2 R2 Str Ld(0:2) dc ao

Col(0:2) Col(3:5)

ampout

ao0 ao1

ampout

InL

0

SerOut

En

RIn

R(3

:0)

En

LIn

L(3

:0)

En

(5:0

)

InL/R(0:3)

row

0(R

),row

1(L

)ro

w2

(R),ro

w3

(L)

En(11:6)

En

(5:0

)

InL

1

InL

2

InL

3

InR

0

InR

1

InR

2

InR

3+ + + +

Page 10: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 2014

CCPDv4

Amplitude coding

10

Page 11: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 201411

CLIC Pixel

• Chip Layout

1.6

mm

Page 12: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 201412

CLIC Pixel

• Simulation: Response to 1500 e input signal (MIP)

• Signal amplitude: 370mV

37

0m

V

Page 13: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 201413

TSV

Page 14: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 201414

Assembly Possibilities

Readout chip

Detector as it is done now:Diode based pixel sensor bump-bonded to readout ASICs

Present development:CMOS pixel sensor capacitively coupled to readout ASICs

With TSVsCMOS pixel sensor with backside contactscapacitively coupled to readout ASICs

PCB

Pixel sensor(diode based)(e.g. 8 x 2cm)

CMOS pixel sensorseveral reticles(e.g. 4 x 2 cm)

Readout chip

Pixel sensor

Readout chips

Wire bond for sensor bias

Wire bonds for RO chips Wire bonds for RO chips

Wire bonds for sensor chip

Readout chips

CMOS pixel sensor

Capacitive signal transmission

CMOS pixel sensorseveral reticles(e.g. 4 x 2 cm)

Readout chip

Wire bonds for sensor chip

Wire bonds for RO chips

CMOS pixel sensor with backside contacts

TSVs

Backside contact

PCB PCB PCB

Capacitive signal transmission

Page 15: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 201415

Thank you!

Page 16: Ivan Peric, CLIC Workshop 2014 1 HVCMOS for CLICPix V2

Ivan Peric, CLIC Workshop 2014

Chip-Top

• CLIC pixels, size 25 x 25um

• ATLAS Type A sub pixel size 33um x 125um

• ATLAS Type B sub pixel size 25um x 125um

16

A N

2x3-col

mon

AO

Mon-AmplifierAnalog-multiplexer

Bia

s B

lock

CLIC

2x4-col 64 x 25um col

Diode for laser testsSeparated guard bias

4 special columns (CLIC)