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convenient to organi3e them into multiple $iles' A common convention is to write one moderate

si3ed module per $ile 4or group related tiny modules into a single $ile5 then combine the $iles o$ the

design together during compilation' (or e%ample& the counter model in counter'v0

module ounter(out, l!, reset);

parameter W#H &;

output 'W#H- *+ out; input l!, reset;

reg 'W#H- *+ out; ire l!, reset;

alays (posedge l!) out out / ;

alays reset if (reset) assign out *;

else deassign out;

endmodule 00 ounter

and the test bench in counter6tb'v0

module test;

01 2a!e a reset that pulses one. 10 reg reset *; initial begin 3 4 reset ; 3 reset *; 3 56 reset ; 3 reset *; 3 ** $stop; end

01 2a!e a regular pulsing lo!. 10 reg l! *; alays 37 l! 8l!;

ire '4*+ value; ounter (value, l!, reset);

initial $monitor("9t time %t, value %h (%*d)", $time, value, value);endmodule 00 test

are written into di$$erent $iles'

!he ,iverilog, command supports multi1$ile designs by two methods' !he simplest is to list the $iles

on the command line0

% iverilog -o my:design ounter:tb.v ounter.v% vvp my:design

!his command compiles the design& which is spread across two input $iles& and generates the

compiled result into the ,my6design, $ile' !his works $or small to medium si3ed designs& but gets


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cumbersome when there are lots o$ $iles'

Another techni)ue is to use a command$ile& which lists the input $iles in a te%t $ile' (or e%ample&

create a te%t $ile called ,$ile6list't%t, with the $iles listed one per line0

ounter.vounter:tb.v

!hen compile and e%ecute the design with a command like so0

% iverilog -o my:design - file:list.tt% vvp my:design

!he command $ile techni)ue clearly supports much larger designs simply by saving you the trouble

o$ listing all the source $iles on the command line' Name the $iles that are part o$ the design in the

command $ile and use the ,1c, $lag to tell iverilog to read the command $ile as a list o$ Verilog input

$iles'

As designs get more complicated& they almost certainly contain many Verilog modules thatrepresent the hierarchy o$ your design' !ypically& there is one module that instantiates other

modules but is not instantiated by any other modules' !his is called a rootmodule' .carus Verilog

chooses as roots 4!here can be more than one root5 all the modules that are not instantiated by other

modules' .$ there are no such modules& the compiler will not be able to choose any root& and the

designer must use the ,1sroot, switch to identi$y the root module& like this0

% iverilog -s main -o hello hello.v

.$ there are multiple candidate roots& all o$ them will be elaborated' !he compiler will do this even i$

there are many root modules that you do not intend to simulate& or that have no e$$ect on thesimulation' !his can happen& $or e%ample& i$ you include a source $ile that has multiple modules& but

are only really interested in some o$ them' !he ,1s, $lag identi$ies a speci$ic root module and also

turns o$$ the automatic search $or other root modules' 7ou can use this $eature to prevent

instantiation o$ unwanted roots'

As designs get even larger& they become spread across many do3ens or even hundreds o$ $iles'

When designs are that comple%& more advanced source code management techni)ues become

necessary' !hese are described in later chapters& along with other advanced design management

techni)ues supported by .carus Verilog'

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