jan axelson's lakeview research

8/12/2019 Jan Axelson's Lakeview Research

1/12

search this site only

Home Site Map Buy Books About Lakeview Research

USB Serial Ports Mass Storage Ethernet Parallel Port PR!S "orum

More

LVR.COM has moved toJANAXELSON.COM

Please update your bookmarks and links.

A#ter $une %& '(%)& this site will be available *L+ at

janaxelson.coman, links to content at lvr-com will

no longer work-

Home. Articles. RS/)01 2ircuits #or All ccasions

Designing RS!"# Ci$c%its

$an A3elson

!his article was originally publishe, in 2ircuit 2ellar-

4hen a network nee,s to trans#er small blocks o# in#ormation

over long ,istances& RS/)01 is o#ten the inter#ace o# choice-

!he network no,es can be P2s& microcontrollers& or any

,evices capable o# asynchronous serial communications-

2ompare, to Ethernet an, other network inter#aces& RS/)015s

har,ware an, protocol re6uirements are simpler an, cheaper-

!he RS/)01 stan,ar, is #le3ible enough to allow a choice o#,rivers& receivers& an, other components ,epen,ing on the

cable length& ,ata rate& number o# no,es& an, the nee, to

conserve power- Several ven,ors o##er RS/)01 transceivers

with various combinations o# #eatures- 7n a,,ition& there are

options #or metho,s o# terminating an, biasing the line an,

controlling the ,river/enable inputs-

7n this article& 7 show several circuits #or RS/)01 networks-

Even i# you use prebuilt car,s or converters& un,erstan,ing theoptions will help you choose the right pro,uct an, con#igure it

to get the best results #or your application-

&a$tne$ Lin's

(ools) D$ive$s)

*i$m+a$e

!he broa,est

range o# pro,ucts

an, services #or

the USB,eveloper-

mcci-com

,igh -%alit

Em/edded 0S1

Most 8evice9Host

controllers

supporte,- Broa,

range o# class

,rivers-

www-H22/

Embe,,e,-com

Net+o$'ing

Ove$ 0S1

R*87S&

282/E2M9EEM

9*2M9A2M-

Pre/con#igure,pro:ects available-

www-H22/

Embe,,e,-com

Em/edded

&$og$amming

E3perts in

embe,,e,

so#tware,evelopment-

Microchip 2erti#ie,

2onsults-

Axelson's Lakeview Research http://janaxelson.com/rs-485_circuits.ht

12 6/1/2014 10:13 PM


2/12

RS!"# in 1$ie2

But #irst& a 6uick look at RS/)01- !he inter#ace popularly known

as RS/)01 is an electrical speci#ication #or multipoint systems

that use balance, lines- RS/)01 is similar to RS/)''& but

RS/)'' allows :ust one ,river with multiple receivers& whileRS/)01 supports multiple ,rivers an, receivers-

!he speci#ication ,ocument& !7A/)01/A& ,e#ines the electrical

characteristics o# the line an, its ,rivers an, receivers- !here

are brie# suggestions relating to terminations an, wiring& but

unlike RS/';'& there5s no ,iscussion o# connector pinouts or

so#tware protocols-

An RS/)01 network can have as many as ;' unit loa,s& with

one unit loa, e6uivalent to an input impe,ance o# %'k- By usinghigh/impe,ance receivers& you can have as many as '1 at %Mbps& it ,rops

to )(( #t& an, at %(Mbps& to 1( #t- "or more no,es or very long

,istances& you can use repeaters that regenerate the signals

an, begin a new RS/)01 line-

Although the RS/)01 stan,ar, says nothing about protocols&

most RS/)01 links use the #amiliar asynchronous protocols

supporte, by the UAR!s in P2s an, other computers- A

transmitte, wor, consists o# a Start bit #ollowe, by ,ata bits&

an optional parity bit& an, a Stop bit-

!wo ways to a,, RS/)01 to a P2 are on an e3pansion car, an,

by attaching an RS/)01 converter to an e3isting port-

2onverters #or RS/';' an, USB are available- nmicrocontrollers& you can connect an RS/)01 transceiver to

any asynchronous serial port-

Many network circuits also re6uire a port bit to control each

transceiver5s ,river/enable input- Ports ,esigne, #or RS/';'

communications can use the R!S output- 7# that5s not available&

any spare output bit will ,o-

Most serial/communications tools& inclu,ing ?isual Basic5s

MS2omm& support RS/)01 communications with R!S

controlle, in so#tware- 42S25s 2MM/8R?serial/port ,rivers

have automatic R!S control built/in-

absolute/

so#tware-co-uk

0S1 &$otocol

Anal3e$s

ELL7S+S protocol

analy@ers&

generators&

automate,

compliance

solutions-

www-ellisys-com

0S1($ace 0S1

Anal3e$

So#tware/base,

USB ProtocolAnaly@er-

Easy/to/use an,

a##or,able-

www-sysnucleus-co

&o+e$2%l 0S1

Anal3e$

Real/time USB '-(

,isplay class,eco,ing- See a

vi,eo ,emo now-

www-totalphase-co

0S1 to Ethe$net

Connecto$

Share access

USB ,evices over

local network or

even 7nternet

www-eltima-com

CCC

!o #in, out about

a,vertising on this

site& please

contact :an Dat

:ana3elson-com-


12 6/1/2014 10:13 PM


3/12

!he main reason why RS/)01 links can e3ten, so #ar is their

use o# balance,& or ,i##erential& signals- !wo wires& usually a

twiste, pair& carry the signal voltage an, its inverse- !he

receiver ,etects the ,i##erence between the two- Because most

noise that couples into the wires is common to both wires& it

cancels out-

7n contrast& inter#aces like RS/';' use unbalance,& or single/

en,e,& signals- !he receiver ,etects the voltage ,i##erence

between a signal voltage an, a common groun,- !he groun,

wire ten,s to be noisy because it carries the return currents #or

all o# the signals in the inter#ace& along with whatever other

noise has entere, the wire #rom other sources- An, noise on

the groun, wire can cause the receiver to misrea, transmitte,

logic levels-

!he chips5 ,ata sheets label the non/inverte, RS/)01 line as

line A& an, the inverte, line as line B- An RS/)01 receiver must

see a voltage ,i##erence o# :ust '((m? between A an, B- 7# A is

at least '((m? greater than B& the receiver5s output is a logic

high- 7# B is at least '((m? greater than A& the output is a logic

low- "or ,i##erences less than '((m?& the output is un,e#ine,-

At the ,river& the voltage ,i##erence must be at least %-1?& so

the inter#ace tolerates a #air amount o# non/common/mo,e

noise an, attenuation-

?en,ors o# RS/)01 transceivers inclu,e Linear !echnology&

Ma3im& *ational Semicon,uctor& an, !e3as 7nstruments- !hese

companies are also e3cellent sources #or application notes

containing circuit e3amples an, e3planations o# the theory

behin, them-

RS/)01 is ,esigne, to be wire, in a ,aisy/chain& or bus&

topology- Any stubs that connect a no,e to the line shoul, beas short as possible- Most links use twiste, pairs because o#

their ability to cancel magnetically an, electromagnetically

couple, noise-

A 4ene$al5%$5ose Net+o$'

Here is a no,e #or a general/purpose RS/)01 networkF


12 6/1/2014 10:13 PM


4/12

Each no,e has a !e3as 7nstruments S*G1%G


5/12

!he initial current is a #unction o# the line5s characteristic

impe,ance& which is the input impe,ance o# an in#inite& open

line- !he value varies with the wires5 ,iameters& the spacing

between them& an, type o# insulation-

"or ,igital signals& which mainly consist o# #re6uencies greater

than %(( kH@& the characteristic impe,ance is mostly resistive>the in,uctive an, capacitive components are small- A typical

value #or A4I J') twiste, pair is %'( ohms-

!he #inal current is a #unction o# the line termination& the

receivers5 input impe,ance& an, the line5s series impe,ance- 7n

a typical RS/)01 line without a termination& the initial current is

greater than the #inal current because the characteristic

impe,ance is less than the receivers5 combine, input

impe,ance-

n a line without a termination& the #irst re#lection occurs when

the initial current reaches the receiver- !he receiver5s input can

absorb only a #raction o# the current- !he rest re#lects back to

the ,river- As the current reverses ,irection& its magnetic #iel,

collapses an, in,uces a voltage on the line- As a result& the

receiver initially sees a greater voltage than what was

transmitte,-

4hen the re#lecte, voltage reaches the ,river& which has alower impe,ance than the line& the ,river absorbs some o# the

re#lection an, bounces the rest back to the receiver- !his

re#lection is o# opposite polarity to the #irst re#lection& an,

causes the receiver to see a re,uce, voltage- !he re#lections

bounce back an, #orth like this #or a #ew roun,s be#ore they ,ie

out an, the line settles to its #inal current-

7# the line terminates with a resistor e6ual to the line5s

characteristic impe,ance& there are no re#lections- 4hen theinitial current reaches the termination& it sees e3actly what it

was e3pectingF a loa, e6ual to the line5s characteristic

impe,ance- !he entire transmitte, voltage ,rops across the

loa,- 7n a network with two parallel terminations& the ,rivers

actually ,rive two lines& each en,ing at a termination-

!he biasing resistors hol, the line in a known state when no

,rivers are enable,- Most RS/)01 transceivers have internal

biasing circuits& but a,,ing a termination ,e#eats their ability to

bias the line- A typical internal circuit is a %((k pullup #rom line

A to ?K& an, a %((k pull,own #rom line B to groun,-

4ith no termination& when no ,rivers are enable,& the biasing


12 6/1/2014 10:13 PM


6/12

resistors hol, line A more positive than line B- 4hen you a,,

two %'(/ohm terminations& the ,i##erence between A an, B

shrinks to a #ew millivolts& much less than the re6uire, '((m?-

!he solution is to a,, smaller resistors in parallel with the

internal biasing& so that a greater proportion o# the series

voltage ,rops across the termination-

!he si@e o# the biasing resistors is a tra,eo##- "or a greater

voltage ,i##erence an, higher noise immunity on an i,le line&

use smaller values- "or lower power consumption an, a greater

,i##erential voltage on a ,riven line& use larger values-

4hen the receiver is ,isable,& the receiver5s output is high

impe,ance- 7# the output ,oesn5t connect to a input with an

internal pullup& a,,ing a pullup here will ensure that the no,e

,oesn5t see #alse Start bits when its receiver is ,isable,-

!o comply with the speci#ication& all o# the no,es must share a

common groun, connection- !his groun, may be isolate, #rom

earth groun,-

!he groun, wire provi,es a path #or the current that results

#rom small imbalances in the balance, line- 7# the A an, B

outputs balance e3actly& with e6ual& opposite currents& the two

currents in the groun, wire cancel each other out an, the wire

carries no current at all- 7n real li#e& components ,on5t balance

per#ectly> one ,river will be a little stronger& an, one receiver

will have a slightly larger input impe,ance-

4ithout a common groun,& the circuit may work& but the

energy ,ue to the imbalance has to go somewhere& an, may

,issipate as electromagnetic ra,iation-

!he RS/)01 speci#ication recommen,s connecting a %((/ohm

resistor o# at least %9' 4att in series between each no,e5s

signal groun, an, the network5s groun, wire& as the circuitabove shows- !his way& i# the groun, potentials o# two no,es

vary& the resistors will limit the current in the groun, wire-

Sim5li2ied Lo+5o+e$ Lin'

A,,ing terminations increases a link5s power consumption-

4ith two parallel %'(/ohm terminations an, a ,i##erential

output o# %-1?& the current through the combine, terminations

is '1 mA D,isregar,ing the e##ects o# biasing& attenuation& etc--

4ithout terminations& the loa, is the parallel combination o# the

receivers5 input impe,ances& an, varies with the number o#

receivers- !he ma3imum ;' unit loa,s have a combine, parallel

impe,ance o# ;G1 ohms to groun, or ?K-


12 6/1/2014 10:13 PM


7/12

"or some shorter an, slower links& you can save power an,

components by not using terminating an, biasing components-

!his is #easible i# the line is electrically short& which means that

it behaves as a lumpe,& rather than ,istribute,& system- n a

short line& the re#lections ,ie out long be#ore the receiver is

rea,y to rea, the signal-

A general gui,eline is that a line is short i# the rise time o# its

signals is greater than #our times the signals5 one/way ,elay-

!he one/way ,elay is the amount o# time nee,e, #or a signal to

travel #rom the ,river to the receiver- 7t5s a #unction o# the line5s

physical length an, the spee, o# signals in the line- 7n copper

wire& a typical spee, is '9; the spee, o# light& which works out

to 0 inches9nsec- 2able manu#acturers o#ten speci#y a value #or

pro,ucts likely to be use, in network wiring-

!he rise time is speci#ie, in the ,river5s ,ata sheet- !he slowest

chip 75ve #oun, is Ma3im5s MA;(0(& with a minimum rise time

o#


8/12

7nstea, o# a single pair o# biasing resistors #or the entire line&

the circuit has #our biasing resistors at each no,e-

!he circuit uses !e3as 7nstruments5 G1ALS%0(B transceivers&

which have #ull/,uple3 RS/)01 inputs an, outputs- !he

separate transmit an, receive pairs enable the receiver to haveits own series biasing resistors- !he two RS/)01 lines connect

:ust beyon, the biasing circuits-


12 6/1/2014 10:13 PM


9/12

7n this circuit& i# the signal lines short together& the %-0k series

resistors in combination with the ;


10/12

the network circuits are ,amage, by high voltage-

2omplete isolation re6uires isolating the power supplies an,

the network5s signals- !he power supplies typically use

trans#ormer isolation& while the signals use optoisolatorsF

A one/chip way to achieve isolation is to use Ma3im5s

MA%)0(& which contains its own trans#ormer/isolate, supply

an, optoisolate, signal path-

A%tos+itching Lin'

ne o# challenges in ,esigning an RS/)01 link is controlling the

,river/enable lines- Because all o# the no,es share a ,ata path&

only one ,river can be enable, at a time- Be#ore transmitting& a,river must be sure that the previous ,river has been ,isable,-

Many RS/)01 networks use a comman,9response protocol&

where one no,e sen,s comman,s& an, the no,e being

a,,resse, returns a response-

!he UAR! in the no,e being a,,resse, ,etects the #inal Stop

bit in the mi,,le o# the bit wi,th& or slightly sooner or later i#

the sen,er5s clock ,oesn5t match e3actly- A very #ast no,e may

be rea,y to sen, a reply within a #ew microsecon,s a#ter

,etecting the Stop bit- !o prevent the nee, #or a ,elay be#ore

respon,ing& the sen,ing no,e5s ,river shoul, be ,isable, as

soon as possible a#ter the lea,ing e,ge o# its #inal Stop bit-

7n most systems& the transmitting ,river is enable, on the

lea,ing e,ge o# the Start bit an, remains enable, #or the entire

transmission& then is ,isable, as soon as possible a#ter the #inal

Stop bit- 7n the ,elays between transmissions& biasing hol,s

the line in an i,le state-

!here are various ways that the transmitting no,e can

,etermine when a transmission has #inishe, an, it5s sa#e to


f 12 6/1/2014 10:13 PM


11/12

,isable the ,river- !he no,e may rea, back what it sent& or it

may use a har,ware or so#tware timer to estimate the time

nee,e, to transmit-

!his circuit shows a completely automatic way to control the

enable line so that the ,river is ,isable, as 6uickly as possible&

soon a#ter the lea,ing e,ge o# the Stop bitF

4ith this circuit& the program co,e ,oesn5t have to toggle a

signal to enable an, ,isable the ,river& an, a transmitting

,river ,oesn5t nee, to allow e3tra time to be sure that the

previous ,river has been ,isable,-

Unlike other metho,s o# automatic control& there are no

:umpers to set #or a particular bit rate- 7 #irst learne, o# this

metho, when 7 saw it in R-E- Smith5s 7RS"2') 7solate, RS/)01

boar,-

7nstea, o# keeping the transmitter enable, #or the entiretransmission& the circuit above enables the ,river on the

lea,ing e,ge o# the Start bit or any logic low at the ,river5s

input& an, it ,isables the ,river about )( microsecon,s a#ter


f 12 6/1/2014 10:13 PM


12/12

the lea,ing e,ge o# the Stop bit or any logic high at the ,river5s

input- 4hen the ,river is ,isable,& biasing resistors ensure that

the receiver5s output is a logic high-

!he ,elay is generate, by a 111 timer con#igure, as a

monostable Done/shot- !he enable inputs o# the ,river an,

receiver are tie, together& so the receiver is ,isable, when the

,river transmits-

!he timer5s output controls the transceiver5s enable inputs- A

#alling e,ge at 8ata ut in,icates a Start bit an, triggers the

timer- !he timer5s output goes high& enabling the ,river an,

bringing line B more positive than line A- 8io,e #ee,back to the

!rig input hol,s the timer5s output high #or as long as !rig

remains low-

4hen 8ata ut goes high& the RS/)01 line switches& bringingline A more positive than line B- !he same logic high also

causes the timer to begin timing out- About )( microsecon,s

a#ter the rising e,ge& the timer5s output goes low& ,isabling the

,river- !he ,elay ensures that the ,river5s RS/)01 output

switches without ,elay& while the ,river is enable,- 4hen the

,river is ,isable,& the biasing components continue to hol, A

more positive than B-

7n a similar way& any #alling e,ges in the transmitte, ,ata

enable the ,river& an, any rising e,ges ,isable the ,river a#ter

the ,elay- n the #inal Stop bit& the ,river is ,isable, no later

than )( microsecon,s a#ter the Stop bit5s lea,ing e,ge-

At rates o# =

jan axelson's lakeview research

Documents