jeff shelton 23 march 2015 1 - purdue university
TRANSCRIPT
Jeff Shelton – 23 March 2015 1
Jeff Shelton – 23 March 2015
Dat
a B
us
Module II
Register A Module I
Register B
2
Jeff Shelton – 23 March 2015 3
Pull-up Resistor
Vcc
Vout + – Button
R1
Jeff Shelton – 23 March 2015 4
Pull-up Resistor
Vcc
Vout + – Button
R1
1. R1 determines how much current flows through the button when it is pressed closed. (Don't want too low, as power loss is i2R; start at around 10 kΩ.)
2. R1 determines, in conjunction with input impedance of op-amp, how much current flows into op-amp when circuit is open. (Don't want too high; normally choose order of magnitude less than input impedance of next stage.)
Jeff Shelton – 23 March 2015 5
Two-state output
Tri-state output
Open circuit allows next stage to sink a small amount of current (< 2 mA for TTL) to ground through resistor; results in low voltage (< 0.8 V) at output.
In third state, no current flows through resistor; output neither high nor low. No influence on other circuitry.
Pull-down Resistor
Jeff Shelton – 23 March 2015 6
EN A OUT
0 0 Z
0 1 Z
1 0 1
1 1 0
Jeff Shelton – 23 March 2015
D0
D1
D2
Inputs Outputs
Output Enable
Load Clock
7
Jeff Shelton – 23 March 2015
D0
D1
D2
Inputs Outputs
Output Enable
Load Clock
8
Jeff Shelton – 23 March 2015
(Clock)
(Output Enable)
9
Jeff Shelton – 23 March 2015 10
(Output Enable 1)
(Output Enable 2)
Jeff Shelton – 23 March 2015
Master Clock
OE (reg. A)
LOAD (reg. B)
Data (bus)
11
Dat
a B
us
Module II
Register A Module I
Register B
Jeff Shelton – 23 March 2015 12 Image: http://en.wikipedia.org/wiki/Computer_bus
Jeff Shelton – 23 March 2015
13
Jeff Shelton – 23 March 2015
Dat
a B
us
Output Register Output Enable
Latch Input
Input Register Output Enable
Latch Input
Processor Output Enable
Latch Input
General Register
Output Enable
Latch Input
I/O Register
Output Enable
Latch Input
Memory Output Enable
Latch Input
14
Jeff Shelton – 23 March 2015
15
Jeff Shelton – 23 March 2015
16
Jeff Shelton – 23 March 2015
17
Jeff Shelton – 23 March 2015
•
•
•
•
•
•
18
Jeff Shelton – 23 March 2015
Jeff Shelton – 23 March 2015
20
Jeff Shelton – 23 March 2015
21 Image: https://secure.flickr.com/photos/twylo/2592395272/
Jeff Shelton – 23 March 2015
Start
Stop
D0 (LSB)
D1 D2 D7 or Parity
D6
LOGIC ONE
LOGIC ZERO
22
Jeff Shelton – 23 March 2015
23
Jeff Shelton – 23 March 2015
24
Jeff Shelton – 23 March 2015
G
W
B R
Outer Shield > 65% Interwoven
Tinned Copper Braid
Polyvinyl Chloride (PVC) Jacket
Inner Shield Aluminum
Metallized Polyester 28 AWG Tinned Copper Drain Wire
Non Twisted Power Pair: Red: V BUS
Black: GND
Twisted Signal Pair:
White: Data -
Green: Data +
25 Additional lines present in USB 3!
Jeff Shelton – 23 March 2015 26
Jeff Shelton – 23 March 2015 27
Vcc I2C supply voltage, typically ranging from 1.2 V to 5.5 V
GND Common ground
SDA Serial data (I2C data line)
SCL Serial clock (I2C clock line)
Rp Pull-up resistance (a.k.a. I2C termination)
Rs Serial resistance
Cp Wire capacitance
Cc Cross channel capacitance
Image: http://www.i2c-bus.org/typical-i2c-bus-setup/
Jeff Shelton – 23 March 2015
28
Jeff Shelton – 23 March 2015 29
SPI Master
SCLK MOSI MISO
SS1 SS2 SS3
SPI Slave
SCLK MOSI MISO SS
SPI Slave
SCLK MOSI MISO SS
SPI Slave
SCLK MOSI MISO SS
Jeff Shelton – 23 March 2015
30
Jeff Shelton – 23 March 2015
31
RJ-45
Jeff Shelton – 23 March 2015
Image: https://www.adafruit.com/products/201 32
Jeff Shelton – 23 March 2015
33
Jeff Shelton – 23 March 2015
Image: https://www.sparkfun.com/products/11287 34
Jeff Shelton – 23 March 2015
Image: https://www.spark.io/ 35
Unit price is $39
Jeff Shelton – 23 March 2015
36
Jeff Shelton – 23 March 2015
Image: http://www.makershed.com/Bluetooth_Low_Energy_BLE_Shield_for_Arduino_2_0_p/mkrbl1.htm
37
JY-MCU Bluetooth Module
Jeff Shelton – 23 March 2015 38
Jeff Shelton – 23 March 2015 Image: https://www.sparkfun.com/products/10414 39
Jeff Shelton – 23 March 2015
Table: http://www.zigbee.org/About/FAQ.aspx
40
Jeff Shelton – 23 March 2015 41
Jeff Shelton – 23 March 2015
Image: https://www.adafruit.com/products/789
42
Jeff Shelton – 23 March 2015
43