joal 2005 ht:1 em3 custom designed integrated circuits 1 lecture 7 and 8

joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

1

Lecture 7 and 8


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Extended FSM models (RT-level)

• FSMs have normally only Boolean inputs as conditions and Boolean outputs

• Sequential logic has both control path and data path. How to describe?

• How can we include arithmetic in a FSM?• One answer is to use a FSMD (FSM with Data

path)


3

Extended FSM Models

X<Y X>Y

Y=Y-X X=X-Y Data path(ALU etc)

Control path(FSM)

FSMD

Control signals

Status signals


4

Extended FSM Models

=?

Data Path

Control signals

Condition signals

s1

s2

s3

s4

Control Path


5

Extended FSM Models (FSMD)

State name

State box

Conditional variable

assignment

Unconditional variable and output assignments

ConditionDecision box

Condition box

0 1


6

Extended FSM Models (FSMD)

Blocks1

s0

s2

Blocks1

s0

Cond assign

Moore type Mealy type


7

Extended FSM, UART Project

• We want to model the UART. Alternatives:– Sequential language model (just VHDL)– State machine model (FSM) for control and data path.

Control and condition signals between control path and data path.

– Extended FSM (FSMD with data path)

• Model can be manually synthesized to VHDL code which is automatically synthesized to logic


8

Extended FSM, UART Project

Buss interface

Receiver Transmitter

Bit rate generator

FSM

RX Reg TX Reg

FSM

Bit rate * 16


9

Extended FSM, UART ProjectSynchronous clock and bit clock

Do not gate the clock but use a condition!

processbegin if reset=‘1’ then ......... elsif clk’event and clk=‘1’ then if bit_clk=‘1’ then -- bit clock= one clk period ......... end if; end if;end process;


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FSMD for UART Receiver

Cnt16=0BitCnt=0

RX=0

Cnt16=Cnt16+1

Cnt16=7

0

R=Par & R(9:1)0

s1

BitCnt=BitCnt+1

BitCnt=9

R=RX & R(9:1)

0

s0

RXRDY=1

s2

RXRDY-set: Strobe one system clock!


11

Design Productivity Gap

Moore’s L

aw

Progress in Design Automation

Design ProductivityGap

Moore’s Law: The capacity of integrated chips doubles every 18-20 months.

Time65 75 80 85 90 95 2000

108

1

106


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History of Automation in System Design

Levels of Design Representation

System Functional Specification

Behavioral Specification (VHDL)

RTL Design, “C-Code”

Logic Level Design, “Machine Code”

Physical Design

Implementation

70’s

80s

85

90s

2000 Partially


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Y-Chart

Behavioral DomainStructural Domain

Physical Domain

Boards, MCM

Transistor Layout

Cells, Modules

Chips, ASICs

Flowcharts, Algorithms

Register TransfersBoolean Expressions Transistor Functions

Processors, Mem, Buses Registers, ALUs, MuXs, . Gates, Flip-Flops - Transistors


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Y-Chart-AXES

• Behavioral Axis– Represents functionality: what the system is

supposed to do.

• Structural Axis– Represents the logical interconnections of

components to build the system: how the system is built by interconnecting sub-systems(components).

• Physical Axis– Represents the physical implementation of the

system.


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Design Representation in Y-Chart


Physical Domain

Boards, MCM

Transistor Layout

Cells, Modules

Chip, ASIC




Functional Design

Physical Design of a chip As we move towards the

center, we add more details


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Representation of Design Processes


Physical Domain

Boards, MCM

Transistor Layout

Cells, Modules

Chips, ASICs




Synthesis

Implementation


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High level design / Simulation

The efficiency of the designer will increase if she/he designs at a higher abstraction level.

It’s possible to design and simulate VHDL on a Behavioural level. The data types etc can be more freely chosen. Special synthesis tools are required to synthesize on behavioural level!

Note the difference between behavioural level and behavioural synthesis!

We will come to Behavioural synthesis later in this lecture


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Synthesis

Synthesis involves the transformation of system description from behavioral domain to structural domain.

Behavioral Synthesis

Algorithmic description => RTL-design

RTL-design: Design using Registers, adders, muxes etc.

Logic Synthesis

Boolean functions, Finite State Machines => Logic Design

Logic design: Design using gates and flip-flops.


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Synthesizable/Executable Spec.

Executable Specification

It is possible to simulate the specification to determine system behaviour. Some languages give clock accurate simulation (e.g. SystemC).

Synthesizable Specification

It is possible to build hardware with equivalent timing and functional behaviour to the specification.

(A subset of VHDL is synthesizable)


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Synthesizable VHDL: Examples

Architecture XYZ of PQR is

Signal S1, S2, S3

Begin

• • • • •

• • • • •

S2 <= X and Y;

S3 <= S2 or Y after 3 ns;

• • • • • •

End;

&X Y

1

S2

S3

It is not possible to ensure the delay to be exact 3 ns.

Y

S2

S3

Simulation


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Behavioral and RTL Synthesis

HDL DescriptionZ=a(i)*b(i)-c*d(k)+f

x x - +

x- +

x- +

4 cycles*15 ns

x3 cycles*15 ns

x2 cycles*20 ns

Multiple Architectures

x

x- +

Behavioral Synthesis

RTL Synthesis

Vary clock period

Vary # of clock periods

Vary clock period

1 clock cycle

1 cycle*55 ns

Single Architectures


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Behavioral Synthesis: Illustration

ENTITY gcd IS

PORT (x_in,y_in: IN bit8; z_out: OUT bit8; clock, start: IN BIT; ready: OUT BIT);

END gcd;

ARCHITECTURE beh_gcd IS

BEGIN

PROCESS

Variable x,y,z: bit8;

BEGIN

WAIT UNTIL start = ’1’;

X= x_in; Y = y_in;

WHILE NOT( X=Y) LOOP

IF X > Y THEN X= X- Y ELSE Y = Y-X;

WAIT UNTIL clock’event;

END LOOP;

Z_out = X; ready = ’1’;

END Process

X-Reg Y-Reg

Comparator -

MUX MUX

MUX MUX

Z-Reg

Controller

Control Signals


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Behavioral Synthesis/High Level Synthesis

Behavioral synthesis translates the behavioral HDL (VHDL) description to RTL-design (Register Transfer Level). Reuse of resources! Control of resource usage done by Control Unit ( comapare to RTL-level)

Behavioral Synthesis Steps Scheduling

To decide time for each operationConstrains on resources or time

AllocationResources: Registers, Memories, ALUs, buses etc.To decide the type and number of resources required.

BindingDeciding a specific ALU for each operationDeciding a specific register for each varible.


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Data path: A number of interconnected components on RTL-level

Control Unit: FSM that generates control signals for Data path

SchedulingTo decide time for each operation. Determine in which clock cycle a resource shall be executed. Different function can use the same resource but not at the same time. The scheduler is implemented as a State machine (control unit).

AllocationAllocate resources to operators. Decide the type and number of resources required.

BindingBind a special resource to a special operation

Latency: Number of clock cycles required to execute a function.

Throughput: How often new data can be clocked into the system.


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+

*

*

+

*

The resources shall be scheduled so the resource with the

longest path to end shall be scheduled first.

(one method)

4

1

22

3

* 3


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Handshaking / Process synchronization

• VHDL code can be correctly simulated on behavioural level. It’s clock accurate.

• After Behavioural synthesis the cycle-to-cycle behaviour is changed (due to scheduling and resource allocation).

• The processes must be synchronized by handshake signals

data

ready


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Behavioural synthesisFor special purposes a HW,

designed by Behavioural Synthesis, can replace a micro

controller and SW (SPP=Single Purpose

Processor).

Less over headFaster

Example:

Scheduler in a Real time kernel in HW. RealFast in Västerås


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Technology Mapping

Technology mapping process converts a technology independent design into a netlist of components from a particular technology

Technology independent design (generic)Gates with any number of inputs or outputs.Register of any size and with any number of control signals.

Technology dependent componentsA gate with 2 inputs and a specified fan-out.A gate optimized for speed.A gate optimized for area.Etc.


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System ModellingC has been used for system modelling and then refined with VHDL.

Newer methods:

SDL, Specification and Description Language (graphical)SystemC (Class library to C++ for HW modelling)

EFSM = Extended Finite State Machine (data path and control path). Control path generated by tool.

state A

state B

wait for signal

signals

channel

process X

process Y

state A

send signal


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System ModellingHW and SW co-design and co-simulation.

Tools to partion HW and SW

New tools or extended “old” tools: Examples

Superlog (extended Verilog)

SystemC (C++ with class libraries for hardware and communication

modelling)

C / VHDL1)

2)

3)


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IP, Intellectual Property

Virtual components / Cores

The design efficiency can be increased if tested components are reused. Such virtual components are called IP (Intellectual Property).

Hard IP: Technology mapped for a special process or FPGA.Soft IP: Synthesible HDL description (VHDL, Verilog, SystemC etc).

Examples of IP blocks :

Cores: Micro controllers, DSP, DES encryption modules etc.

IO-block: DRAM-controller, UART, USB, Firewire etc


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SoC System On Chip

CPU

RAM

USER LOGIC

Commu-nication

Co Processor

IO


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SoC / SOPCSystem On Programmable Chip

Q: Who can afford this?A: Big companies with very high volumes.Q: Why do we then study System Level Design? In Sweden only Ericsson designs such circuits.A: FPGAs with built in, hard or soft cores, also require system level design methods.

New technology (small scale) has high NRE (Nonrecurring Engineering Cost). (1.2 => 0.6 => 0.35 => 0.25 => 0.15 => 0.13 =>0,09 ( ?? m)

Today (2003): NRE (0.13 m) $500k-1000k(Write off for a fab is $2Bn+ over 3 years)


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NOC Network on Chip (ING Research)

switch

resourcee.g. CPU

network (packet swiched)

0110

0110


35

Seems interesting?

If System level design seems interesting

If Logic synthesis seems interesting

If Advanced HW design seems interesting

Apply for the Master program in Embedded Systems!


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ASIC


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FPLD = Field Programmable Logic Device.

FPGA = Field Programmable Gate Array. >1 milj gates!

PLD = Programmable Logic DeviceCPLD = Complex PLD. <10k gatesSoPC = System on Programmable Chip

ASIC = Application Specific Integrated CircuitGate Array = Prefabricated wafer with logic+added

interconnections (metal layers). Vol > 10kStandard Cell = Library with components (e.g. gates,

multiplexors, flip-flops). Precompiled on transistor level. Vol >100k

Full Custom = Transistor level design. Used for analog circuits.

SoC = System on Chip. Processors and logic on chip.

Customer Integrated Circuits

ASIC

Gate Array

Std Cell

Full Custom

(F)PLD

FPGA PAL

CPLD PLDSoC SoPC


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ASIC Design Phases

Design

Fabrication

Testing

Packaging

• From idea to synthesizable model

• From synthesizable model masks Wafer fabrication

• To check the fabricated chip

• Slicing of wafer into separate chips wire bonding packaging


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ASIC Design Phase

Design

Fabrication

Testing

Packaging Mask set(Photo masks)

Place & RouteSimulations

Validation

Synthesis and Optimization

Netlist

GDS-II tape


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ASIC Fabrication Phase

Design

Fabrication

Testing

PackagingMetal layers

interconnections

Semiconductors fabrication

Silocon wafers

Dia= 4”, 6”, 8”.. etcThickness = 0.5 mm

Only custom stage in Gate

Array

Standard cell & Full custom


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Design

Fabrication

Testing

Packaging

Wafer tests(Probing of pads)

Test vectors

Test equipment

Wafer

Connection pads

Chip


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Design

Fabrication

Testing

Packagingand test

Scribing(Cutting wafers

to chips)

Bonding e.g. wire bonding to lead frame

Plastic moulding or

ceramic packaging

chip

Test of circuits Test vectors


43

n-MOS transistor basics

p+

n+ n+

Gate

Gate oxide

Channel (minority carriers=e-)

Source Drain

Positive voltage on the gate will result in a channel of electrons below the gate oxide (inversion => majority carriers will be replaced with minority carriers).

- - - - - - - - - - - - - - - - - - - - - - - -


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p+

p_MOS transistor basics

Gate

Gate oxide

Source Drain

Negative voltage (relative source) on the gate will result in a channel of holes below the gate oxide (inversion => majority carriers will be replaced with minority carriers).

p+

p+

n-well n+

p+ p++ + + + + + + + + + + + + + + + + + +


45

ASIC Fabrication Phases

Lithography

Photo resist:Organic polymer.

Positive photo resist:soluble after exposure with

UV-light (shorter and shorter wavelengths required)

Si - substrate

Si - substrate

Si - substrate

Si - substrate Si - substrateetching

Si-oxide

photo resist

UV -light

Glass photo mask


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n-channel MOSFET

Si-substrate

SiO2

Si-substrate

SiO2

Thin oxide

SiO2

Si-substrate

Poly silicon

Si-substrate

SiO2

Etching

Si-substrate

SiO2

Si-substraten+ n+

Si-substraten+ n+

Doping(diffusion / Ion implantation)

metal connectors


47

CMOS inverter

p+ p+ n+ n+

VSS

n+

p+

VDDout

in

n-well

in


48

Vout

Vin

CMOS inverter


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CMOS inverter


50

CMOS circuits

&a

bz

a

b

z

NAND gate

P

P

N

N


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VLSI words

• 0.25 micron process, 0.13 micron process, 0.09 micron process:smallest dimension in a transistor is 0.25 micro meter etc

• Cu- layers. Copper is used for the metal layers => lower resistance in the signal wires. 9 metal layers is not unusual!

• 6 inch wafer, 8 inch wafer: Diameter is 6 inches, 8 inches (newest).

• NRE (Non Recurring Engineering costs. Includes e.g. mask set costs. NRE increases with new (smaller) technology


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NRE cost evaluation

• Typical cost for an ASIC in 0.18 m is $5 millions, in 0.13 m $10 millions. Future 0.45 m will cost more than $15 millions.

• Only Asic’s in very high volumes possible (>100k, >1000k)

• Possible solutions to ASIC cost problem:

• “Structured ASIC”: Modern Gate Array (GA) with more complex building blocks than traditionally GA’s.

•Converted FPGA to “Hardwired FPGA” => faster, cheaperhttp://www.altera.com/products/software/pld/products/q2/qts-index.html?xy=qts-gif


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- tb_exempel-- joal 2003-10-07-- Abstract: To demonstrate how multiple drivers can be-- generated in a test bench and-- how to avoid problems with that

LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;

-- ***********************************************LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;

ENTITY tb_exempel ISEND tb_exempel ;

ARCHITECTURE behav OF tb_exempel IS component tt_buffer is port(rd: in std_logic; out_buffer: inout std_logic_vector(7 downto 0)); end component; signal rd: std_logic; signal out_buffer: std_logic_vector(7 downto 0);BEGIN u1: tt_buffer port map (rd,out_buffer); process begin

rd<='1'; wait for 500 ns; rd<='0'; wait;

end process; process begin

wait for 1 us; out_buffer<="10101010"; wait;

end process;END behav;

VHDL Test bench problem


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- tb_exempel-- joal 2003-10-07-- Abstract: To demonstrate how multiple drivers can be-- generated in a test bench and-- how to avoid problems with that

LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;

-- ***********************************************LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;

ENTITY tb_exempel ISEND tb_exempel ;

ARCHITECTURE behav OF tb_exempel IS component tt_buffer is port(rd: in std_logic; out_buffer: inout std_logic_vector(7 downto 0)); end component; signal rd: std_logic; signal out_buffer: std_logic_vector(7 downto 0);BEGIN u1: tt_buffer port map (rd,out_buffer); process begin

rd<='1'; wait for 500 ns; rd<='0'; wait;

end process; process begin-- out_buffer driver in this process must have a start value – otherwise ’U’ is used and can't be resolved!!!! out_buffer<="ZZZZZZZZ";

wait for 1 us; out_buffer<="10101010"; wait;

end process;END behav;



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Before code corrected

rd

out_buffer UUUUUUUU 10101010

After code corrected

rd

out_buffer 01010101 10101010

1 s


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------------------------------------------------------------------------ The capacitor definition begins.....------------------------------------------------------------------------ Schematic of the capacitor component:---- Ta1 o----||----o Tb1------------------------------------------------------------------------LIBRARY DISCIPLINES; USE DISCIPLINES.ELECTROMAGNETIC_SYSTEM.ALL;

ENTITY Capacitance IS GENERIC (val : REAL); PORT (TERMINAL p,m : ELECTRICAL);END;

ARCHITECTURE behav OF Capacitance IS

QUANTITY u_c ACROSS i_c THROUGH p TO m;

BEGIN

i_c==val * u_c'dot;END;

IEEE 1076.1-1999 /VHDL-AMS, Analog modeling added http://www.eda.org/vhdl-ams/


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VHDL-AMS, Analog modeling added

joal 2005 ht:1 em3 custom designed integrated circuits 1 lecture 7 and 8

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