josh ruggiero cse 420 – april 23 rd 2007. mch – memory controller hub bridges connection from...
TRANSCRIPT
![Page 1: Josh Ruggiero CSE 420 – April 23 rd 2007. MCH – Memory Controller Hub Bridges connection from CPU to RAM and Video Bus (AGP/PCI-X) Connects to South](https://reader035.vdocument.in/reader035/viewer/2022070412/56649f225503460f94c3ac44/html5/thumbnails/1.jpg)
Josh RuggieroCSE 420 – April 23rd 2007
![Page 2: Josh Ruggiero CSE 420 – April 23 rd 2007. MCH – Memory Controller Hub Bridges connection from CPU to RAM and Video Bus (AGP/PCI-X) Connects to South](https://reader035.vdocument.in/reader035/viewer/2022070412/56649f225503460f94c3ac44/html5/thumbnails/2.jpg)
MCH – Memory Controller Hub Bridges connection from CPU to RAM and
Video Bus (AGP/PCI-X) Connects to South Bridge A Northbridge with integrated video is
called a GMCH – Graphics and Memory Controller Hub
![Page 3: Josh Ruggiero CSE 420 – April 23 rd 2007. MCH – Memory Controller Hub Bridges connection from CPU to RAM and Video Bus (AGP/PCI-X) Connects to South](https://reader035.vdocument.in/reader035/viewer/2022070412/56649f225503460f94c3ac44/html5/thumbnails/3.jpg)
ICH – I/O Controller Hub Bridge connection from Memory Controller
Hub to slower devices like USB devices, PCI-X, IDE(SATA/PATA), Real Time Clock, BIOS, onboard sound and more
![Page 4: Josh Ruggiero CSE 420 – April 23 rd 2007. MCH – Memory Controller Hub Bridges connection from CPU to RAM and Video Bus (AGP/PCI-X) Connects to South](https://reader035.vdocument.in/reader035/viewer/2022070412/56649f225503460f94c3ac44/html5/thumbnails/4.jpg)
![Page 5: Josh Ruggiero CSE 420 – April 23 rd 2007. MCH – Memory Controller Hub Bridges connection from CPU to RAM and Video Bus (AGP/PCI-X) Connects to South](https://reader035.vdocument.in/reader035/viewer/2022070412/56649f225503460f94c3ac44/html5/thumbnails/5.jpg)
![Page 6: Josh Ruggiero CSE 420 – April 23 rd 2007. MCH – Memory Controller Hub Bridges connection from CPU to RAM and Video Bus (AGP/PCI-X) Connects to South](https://reader035.vdocument.in/reader035/viewer/2022070412/56649f225503460f94c3ac44/html5/thumbnails/6.jpg)
Originally codenamed Broadwater Set out to be the first chipset to support
Core 2 Duo processors Coupled with ICH8 to provide next
generation I/O support Supports 533/800/1066 FSB Next generation of Intel
Integrated Graphics
![Page 7: Josh Ruggiero CSE 420 – April 23 rd 2007. MCH – Memory Controller Hub Bridges connection from CPU to RAM and Video Bus (AGP/PCI-X) Connects to South](https://reader035.vdocument.in/reader035/viewer/2022070412/56649f225503460f94c3ac44/html5/thumbnails/7.jpg)
Features ◦ 6 Serial ATA ports◦ PCI Express◦ Intel High Definition Audio◦ 10 USB ports◦ BIOS loaded on SPI or FWH◦ Integrated Gigabit Ethernet
![Page 8: Josh Ruggiero CSE 420 – April 23 rd 2007. MCH – Memory Controller Hub Bridges connection from CPU to RAM and Video Bus (AGP/PCI-X) Connects to South](https://reader035.vdocument.in/reader035/viewer/2022070412/56649f225503460f94c3ac44/html5/thumbnails/8.jpg)
http://download.intel.com/design/chipsets/datashts/31305302.pdf
http://en.wikipedia.org/wiki/Southbridge_%28computing%29
http://en.wikipedia.org/wiki/Northbridge http://download.intel.com/design/chipsets/
datashts/31305602.pdf